[MIPS GlobalISel] Select G_UMULH

[Petar.Avramovic]

Summary

Legalize G_UMULO and select G_UMULH for MIPS32.

[atanasyan]

LGTM

llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp

bool MipsInstructionSelector::select(MachineInstr &I,
   if (selectImpl(I, CoverageInfo)) {
     return true;
   }
 
   MachineInstr *MI = nullptr;
   using namespace TargetOpcode;
 
   switch (I.getOpcode()) {
+  case G_UMULH: {
+    unsigned PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
+    MachineInstr *PseudoMULTu, *PseudoMove;
+
+    PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu))
+                      .addDef(PseudoMULTuReg)
+                      .add(I.getOperand(1))
+                      .add(I.getOperand(2));
+    if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI))
+      return false;
+
+    PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI))
+                     .addDef(I.getOperand(0).getReg())
+                     .addUse(PseudoMULTuReg);
+    if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
+      return false;
+
+    I.eraseFromParent();
+    return true;
+  }
   case G_GEP: {
     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
              .add(I.getOperand(0))
              .add(I.getOperand(1))
              .add(I.getOperand(2));
     break;
   }
   case G_FRAME_INDEX: {

llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp

MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
   getActionDefinitionsBuilder({G_ADD, G_SUB})
       .legalFor({s32})
       .clampScalar(0, s32, s32);
 
   getActionDefinitionsBuilder(G_MUL)
       .legalFor({s32})
       .minScalar(0, s32);
 
-  getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE})
+  getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO})
       .lowerFor({{s32, s1}});
 
+  getActionDefinitionsBuilder(G_UMULH)
+      .legalFor({s32});
+
   getActionDefinitionsBuilder({G_LOAD, G_STORE})
       .legalForTypesWithMemDesc({{s32, p0, 8, 8},
                                  {s32, p0, 16, 8},
                                  {s32, p0, 32, 8},
                                  {p0, p0, 32, 8}})
       .minScalar(0, s32);
 
   getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})

llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp

MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   unsigned NumOperands = MI.getNumOperands();
   const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
 
   switch (Opc) {
   case G_TRUNC:
   case G_ADD:
   case G_SUB:
   case G_MUL:
+  case G_UMULH:
   case G_LOAD:
   case G_STORE:
   case G_ZEXTLOAD:
   case G_SEXTLOAD:
   case G_GEP:
   case G_AND:
   case G_OR:
   case G_XOR:

llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
 --- |
 
   define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
+  define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void }
 
 ...
 ---
 name:            mul_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
bb.0.entry:
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %2:gprb(s32) = G_MUL %0, %1
     $v0 = COPY %2(s32)
     RetRA implicit $v0
 
 ...
+---
+name:            umul_with_overflow
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: $a0, $a1, $a2
+
+    ; MIPS32-LABEL: name: umul_with_overflow
+    ; MIPS32: liveins: $a0, $a1, $a2
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+    ; MIPS32: [[PseudoMULTu:%[0-9]+]]:acc64 = PseudoMULTu [[COPY]], [[COPY1]]
+    ; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoMULTu]]
+    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 0
+    ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[PseudoMFHI]], [[ORi]]
+    ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]]
+    ; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi 0
+    ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi [[LUi1]], 1
+    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi1]]
+    ; MIPS32: SB [[AND]], [[COPY2]], 0 :: (store 1 into %ir.pcarry_flag)
+    ; MIPS32: RetRA
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:gprb(p0) = COPY $a2
+    %6:gprb(s32) = G_UMULH %0, %1
+    %7:gprb(s32) = G_CONSTANT i32 0
+    %8:gprb(s32) = G_ICMP intpred(ne), %6(s32), %7
+    %9:gprb(s32) = G_CONSTANT i32 1
+    %10:gprb(s32) = COPY %8(s32)
+    %5:gprb(s32) = G_AND %10, %9
+    G_STORE %5(s32), %2(p0) :: (store 1 into %ir.pcarry_flag)
+    RetRA
+
+...

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
 --- |
 
   define void @mul_i32() {entry: ret void}
   define void @mul_i8_sext() {entry: ret void}
   define void @mul_i8_zext() {entry: ret void}
   define void @mul_i8_aext() {entry: ret void}
   define void @mul_i16_sext() {entry: ret void}
   define void @mul_i16_zext() {entry: ret void}
   define void @mul_i16_aext() {entry: ret void}
+  define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void }
 
 ...
 ---
 name:            mul_i32
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
bb.1.entry:
     %3:_(s32) = COPY $a1
     %1:_(s16) = G_TRUNC %3(s32)
     %4:_(s16) = G_MUL %1, %0
     %5:_(s32) = G_ANYEXT %4(s16)
     $v0 = COPY %5(s32)
     RetRA implicit $v0
 
 ...
+---
+name:            umul_with_overflow
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: $a0, $a1, $a2
+
+    ; MIPS32-LABEL: name: umul_with_overflow
+    ; MIPS32: liveins: $a0, $a1, $a2
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+    ; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[COPY1]]
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
+    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+    ; MIPS32: G_STORE [[AND]](s32), [[COPY2]](p0) :: (store 1 into %ir.pcarry_flag)
+    ; MIPS32: RetRA
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(p0) = COPY $a2
+    %3:_(s32), %4:_(s1) = G_UMULO %0, %1
+    G_STORE %4(s1), %2(p0) :: (store 1 into %ir.pcarry_flag)
+    RetRA
+
+...

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll

 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    mul $2, $5, $4
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %mul = mul i16 %b, %a
   ret i16 %mul
 }
+
+declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
+define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) {
+; MIPS32-LABEL: umul_with_overflow:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    multu $4, $5
+; MIPS32-NEXT:    mfhi $4
+; MIPS32-NEXT:    lui $5, 0
+; MIPS32-NEXT:    ori $5, $5, 0
+; MIPS32-NEXT:    xor $4, $4, $5
+; MIPS32-NEXT:    sltu $4, $zero, $4
+; MIPS32-NEXT:    lui $5, 0
+; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    and $4, $4, $5
+; MIPS32-NEXT:    sb $4, 0($6)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+  %res = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %lhs, i32 %rhs)
+  %carry_flag = extractvalue { i32, i1 } %res, 1
+  store i1 %carry_flag, i1* %pcarry_flag
+  ret void
+}

llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
 --- |
 
   define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
+  define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void }
 
 ...
 ---
 name:            mul_i32
 alignment:       2
 legalized:       true
 tracksRegLiveness: true
 body:             |
bb.0.entry:
     ; MIPS32: RetRA implicit $v0
     %0:_(s32) = COPY $a0
     %1:_(s32) = COPY $a1
     %2:_(s32) = G_MUL %0, %1
     $v0 = COPY %2(s32)
     RetRA implicit $v0
 
 ...
+---
+name:            umul_with_overflow
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: $a0, $a1, $a2
+
+    ; MIPS32-LABEL: name: umul_with_overflow
+    ; MIPS32: liveins: $a0, $a1, $a2
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+    ; MIPS32: [[UMULH:%[0-9]+]]:gprb(s32) = G_UMULH [[COPY]], [[COPY1]]
+    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
+    ; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C1]]
+    ; MIPS32: G_STORE [[AND]](s32), [[COPY2]](p0) :: (store 1 into %ir.pcarry_flag)
+    ; MIPS32: RetRA
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(p0) = COPY $a2
+    %6:_(s32) = G_UMULH %0, %1
+    %7:_(s32) = G_CONSTANT i32 0
+    %8:_(s32) = G_ICMP intpred(ne), %6(s32), %7
+    %9:_(s32) = G_CONSTANT i32 1
+    %10:_(s32) = COPY %8(s32)
+    %5:_(s32) = G_AND %10, %9
+    G_STORE %5(s32), %2(p0) :: (store 1 into %ir.pcarry_flag)
+    RetRA
+
+...