[NFC][GlobalISel]: Add a convenience method to MachineInstrBuilder to simplify getOperand(i).getReg()

[aditya_nandakumar]

Summary

It's a common pattern in GISel to have a MachineInstrBuilder from which we get various regs (commonly MIB->getOperand(0).getReg()). This adds a helper method and the above can be replaced with MIB.getOperandReg(0).

[arsenm]

lib/Target/AArch64/AArch64LegalizerInfo.cpp

501

Why does buildGEP use register inputs instead of SrcOp/DstOp like most of the other build functions?

[aditya_nandakumar]

lib/Target/AArch64/AArch64LegalizerInfo.cpp

501

I believe this was written way before the improvements to MachineIRBuilder and hasn't been updated since.

[aemerson]

If we're going to add a helper to shave some characters off, we might as well go for something really short like getOpReg().

[aditya_nandakumar]

In D57608#1381719, @aemerson wrote:

If we're going to add a helper to shave some characters off, we might as well go for something really short like getOpReg().

That works for me as well. While this seems really trivial, this is repeated lots of times and gets annoying very quickly - kind of like MI->getMF() vs MI->getParent()->getParent().

[kparzysz]

In D57608#1381719, @aemerson wrote:

If we're going to add a helper to shave some characters off, we might as well go for something really short like getOpReg().

Or simply getReg(unsigned OpIdx)---this would keep the names identical. Also, should there be something like this for subregs as well?

[arsenm]

In D57608#1382034, @kparzysz wrote:

In D57608#1381719, @aemerson wrote:

If we're going to add a helper to shave some characters off, we might as well go for something really short like getOpReg().

Or simply getReg(unsigned OpIdx)---this would keep the names identical. Also, should there be something like this for subregs as well?

No, subregisters should never exist for G_* instructions

[aditya_nandakumar]

Updated to use shorter name.

[aemerson]

LGTM.

[aditya_nandakumar]

r353223

include/llvm/CodeGen/MachineInstrBuilder.h

public:
   operator MachineInstr*() const { return MI; }
   MachineInstr *operator->() const { return MI; }
   operator MachineBasicBlock::iterator() const { return MI; }
 
   /// If conversion operators fail, use this method to get the MachineInstr
   /// explicitly.
   MachineInstr *getInstr() const { return MI; }
 
+  /// Get the register for the operand index.
+  /// The operand at the index should be a register (asserted by
+  /// MachineOperand).
+  unsigned getReg(unsigned Idx) { return MI->getOperand(Idx).getReg(); }
+
   /// Add a new virtual register operand.
   const MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
                                     unsigned SubReg = 0) const {
     assert((flags & 0x1) == 0 &&
            "Passing in 'true' to addReg is forbidden! Use enums instead.");
     MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
                                                flags & RegState::Define,
                                                flags & RegState::Implicit,

lib/Target/AArch64/AArch64InstructionSelector.cpp

if (auto *GV = dyn_cast<GlobalValue>(V)) {
       MovI->addOperand(
           MF, MachineOperand::CreateBA(cast<BlockAddress>(V),
                                        MovZ->getOperand(1).getOffset(), Flags));
     }
     MovI->addOperand(MF, MachineOperand::CreateImm(Offset));
     constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI);
     return DstReg;
   };
-  unsigned DstReg = BuildMovK(MovZ->getOperand(0).getReg(),
+  unsigned DstReg = BuildMovK(MovZ.getReg(0),
                               AArch64II::MO_G1 | AArch64II::MO_NC, 16, 0);
   DstReg = BuildMovK(DstReg, AArch64II::MO_G2 | AArch64II::MO_NC, 32, 0);
   BuildMovK(DstReg, AArch64II::MO_G3, 48, I.getOperand(0).getReg());
   return;
 }
 
 bool AArch64InstructionSelector::select(MachineInstr &I,
                                         CodeGenCoverage &CoverageInfo) const {

lib/Target/AArch64/AArch64LegalizerInfo.cpp

MIRBuilder.buildLoad(
                                PtrSize, /* Align = */ PtrSize));
 
   unsigned DstPtr;
   if (Align > PtrSize) {
     // Realign the list to the actual required alignment.
     auto AlignMinus1 = MIRBuilder.buildConstant(IntPtrTy, Align - 1);
 
     unsigned ListTmp = MRI.createGenericVirtualRegister(PtrTy);
-    MIRBuilder.buildGEP(ListTmp, List, AlignMinus1->getOperand(0).getReg());
+    MIRBuilder.buildGEP(ListTmp, List, AlignMinus1.getReg(0));
 
     DstPtr = MRI.createGenericVirtualRegister(PtrTy);
     MIRBuilder.buildPtrMask(DstPtr, ListTmp, Log2_64(Align));
   } else
     DstPtr = List;
 
   uint64_t ValSize = MRI.getType(Dst).getSizeInBits() / 8;
   MIRBuilder.buildLoad(