[RISCV] Allow parsing of bare symbols with offsets

[lewis-revill]

Summary

This patch allows symbols followed by an expression for an offset to be parsed as bare symbols.

[lewis-revill]

Should this only support constant offsets to a symbol? It seems sensible to only support offsets to the symbol, IE add/sub rather than more complex expressions, but the RHS could be any expression at the moment.

[asb]

Is this being used in the wild and does it work sensibly with binutils? I'm seeing that binutils seems to be associating the addend with both the emitted R_RISCV_PCREL_HI20 relocation and R_RISCV_RELAX relocation. Maybe this is just a binutils bug and the addend is ignored by the linker but this does seem surprising...

$ cat t.s 
lla a5, a_symbol + (0xFF << 3)
$ ./riscv32-unknown-elf-as t.s
$ ./riscv32-unknown-elf-readelf -r a.out 

Relocation section '.rela.text' at offset 0xec contains 4 entries:
 Offset     Info    Type            Sym.Value  Sym. Name + Addend
00000000  00000617 R_RISCV_PCREL_HI2 00000000   a_symbol + 7f8
00000000  00000033 R_RISCV_RELAX                7f8
00000004  00000418 R_RISCV_PCREL_LO1 00000000   .L0  + 0
00000004  00000033 R_RISCV_RELAX                0

[jrtc27]

In D57332#1549661, @asb wrote:

Is this being used in the wild and does it work sensibly with binutils? I'm seeing that binutils seems to be associating the addend with both the emitted R_RISCV_PCREL_HI20 relocation and R_RISCV_RELAX relocation. Maybe this is just a binutils bug and the addend is ignored by the linker but this does seem surprising...

$ cat t.s 
lla a5, a_symbol + (0xFF << 3)
$ ./riscv32-unknown-elf-as t.s
$ ./riscv32-unknown-elf-readelf -r a.out 

Relocation section '.rela.text' at offset 0xec contains 4 entries:
 Offset     Info    Type            Sym.Value  Sym. Name + Addend
00000000  00000617 R_RISCV_PCREL_HI2 00000000   a_symbol + 7f8
00000000  00000033 R_RISCV_RELAX                7f8
00000004  00000418 R_RISCV_PCREL_LO1 00000000   .L0  + 0
00000004  00000033 R_RISCV_RELAX                0

Yes, FreeRTOS at least uses it, and we've had to manually patch the source to refer to just the bare symbol and follow it with an addi in order to support LLVM. The RELAX addend is probably a bug but I don't think it actually ever gets read.

[asb]

This patch seems good, but needs rebasing. Thanks!

[lewis-revill]

Rebased

[lenary]

@asb are we happy for this to land? You were happy with it without explicitly approving it.

[asb]

Adding explicit LGTM in the Phabrictor UI. Thanks again Lewis!

[lenary]

@hans please can you backport rL369097 to the 9.0 branch?

[hans]

In D57332#1632995, @lenary wrote:

@hans please can you backport rL369097 to the 9.0 branch?

Merged in r369338.

llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

if (Sym->isVariable()) {
     const MCExpr *V = Sym->getVariableValue(/*SetUsed=*/false);
     if (!isa<MCSymbolRefExpr>(V)) {
       getLexer().UnLex(Tok); // Put back if it's not a bare symbol.
       return MatchOperand_NoMatch;
     }
     Res = V;
   } else
     Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
+
+  MCBinaryExpr::Opcode Opcode;
+  switch (getLexer().getKind()) {
+  default:
+    Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64()));
+    return MatchOperand_Success;
+  case AsmToken::Plus:
+    Opcode = MCBinaryExpr::Add;
+    break;
+  case AsmToken::Minus:
+    Opcode = MCBinaryExpr::Sub;
+    break;
+  }
+
+  const MCExpr *Expr;
+  if (getParser().parseExpression(Expr))
+    return MatchOperand_ParseFail;
+  Res = MCBinaryExpr::create(Opcode, Res, Expr, getContext());
   Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64()));
   return MatchOperand_Success;
 }
 
 OperandMatchResultTy RISCVAsmParser::parseCallSymbol(OperandVector &Operands) {
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
   const MCExpr *Res;

llvm/trunk/test/MC/RISCV/rvi-pseudos.s

 lla a3, ra
 
 # CHECK: .Lpcrel_hi4:
 # CHECK: auipc a4, %pcrel_hi(f1)
 # CHECK: addi  a4, a4, %pcrel_lo(.Lpcrel_hi4)
 lla a4, f1
 
 # CHECK: .Lpcrel_hi5:
+# CHECK: auipc a5, %pcrel_hi(a_symbol+2040)
+# CHECK: addi  a5, a5, %pcrel_lo(.Lpcrel_hi5)
+lla a5, a_symbol + (0xFF << 3)
+
+# CHECK: .Lpcrel_hi6:
 # CHECK-NOPIC: auipc a0, %pcrel_hi(a_symbol)
-# CHECK-NOPIC: addi  a0, a0, %pcrel_lo(.Lpcrel_hi5)
+# CHECK-NOPIC: addi  a0, a0, %pcrel_lo(.Lpcrel_hi6)
 # CHECK-PIC:      auipc a0, %got_pcrel_hi(a_symbol)
-# CHECK-PIC-RV32: lw    a0, %pcrel_lo(.Lpcrel_hi5)(a0)
-# CHECK-PIC-RV64: ld    a0, %pcrel_lo(.Lpcrel_hi5)(a0)
+# CHECK-PIC-RV32: lw    a0, %pcrel_lo(.Lpcrel_hi6)(a0)
+# CHECK-PIC-RV64: ld    a0, %pcrel_lo(.Lpcrel_hi6)(a0)
 la a0, a_symbol
 
-# CHECK: .Lpcrel_hi6:
+# CHECK: .Lpcrel_hi7:
 # CHECK-NOPIC: auipc a1, %pcrel_hi(another_symbol)
-# CHECK-NOPIC: addi  a1, a1, %pcrel_lo(.Lpcrel_hi6)
+# CHECK-NOPIC: addi  a1, a1, %pcrel_lo(.Lpcrel_hi7)
 # CHECK-PIC:      auipc a1, %got_pcrel_hi(another_symbol)
-# CHECK-PIC-RV32: lw    a1, %pcrel_lo(.Lpcrel_hi6)(a1)
-# CHECK-PIC-RV64: ld    a1, %pcrel_lo(.Lpcrel_hi6)(a1)
+# CHECK-PIC-RV32: lw    a1, %pcrel_lo(.Lpcrel_hi7)(a1)
+# CHECK-PIC-RV64: ld    a1, %pcrel_lo(.Lpcrel_hi7)(a1)
 la a1, another_symbol
 
 # Check that we can load the address of symbols that are spelled like a register
-# CHECK: .Lpcrel_hi7:
+# CHECK: .Lpcrel_hi8:
 # CHECK-NOPIC: auipc a2, %pcrel_hi(zero)
-# CHECK-NOPIC: addi  a2, a2, %pcrel_lo(.Lpcrel_hi7)
+# CHECK-NOPIC: addi  a2, a2, %pcrel_lo(.Lpcrel_hi8)
 # CHECK-PIC:      auipc a2, %got_pcrel_hi(zero)
-# CHECK-PIC-RV32: lw    a2, %pcrel_lo(.Lpcrel_hi7)(a2)
-# CHECK-PIC-RV64: ld    a2, %pcrel_lo(.Lpcrel_hi7)(a2)
+# CHECK-PIC-RV32: lw    a2, %pcrel_lo(.Lpcrel_hi8)(a2)
+# CHECK-PIC-RV64: ld    a2, %pcrel_lo(.Lpcrel_hi8)(a2)
 la a2, zero
 
-# CHECK: .Lpcrel_hi8:
+# CHECK: .Lpcrel_hi9:
 # CHECK-NOPIC: auipc a3, %pcrel_hi(ra)
-# CHECK-NOPIC: addi  a3, a3, %pcrel_lo(.Lpcrel_hi8)
+# CHECK-NOPIC: addi  a3, a3, %pcrel_lo(.Lpcrel_hi9)
 # CHECK-PIC:      auipc a3, %got_pcrel_hi(ra)
-# CHECK-PIC-RV32: lw    a3, %pcrel_lo(.Lpcrel_hi8)(a3)
-# CHECK-PIC-RV64: ld    a3, %pcrel_lo(.Lpcrel_hi8)(a3)
+# CHECK-PIC-RV32: lw    a3, %pcrel_lo(.Lpcrel_hi9)(a3)
+# CHECK-PIC-RV64: ld    a3, %pcrel_lo(.Lpcrel_hi9)(a3)
 la a3, ra
 
-# CHECK: .Lpcrel_hi9:
+# CHECK: .Lpcrel_hi10:
 # CHECK-NOPIC: auipc a4, %pcrel_hi(f1)
-# CHECK-NOPIC: addi  a4, a4, %pcrel_lo(.Lpcrel_hi9)
+# CHECK-NOPIC: addi  a4, a4, %pcrel_lo(.Lpcrel_hi10)
 # CHECK-PIC:      auipc a4, %got_pcrel_hi(f1)
-# CHECK-PIC-RV32: lw    a4, %pcrel_lo(.Lpcrel_hi9)(a4)
-# CHECK-PIC-RV64: ld    a4, %pcrel_lo(.Lpcrel_hi9)(a4)
+# CHECK-PIC-RV32: lw    a4, %pcrel_lo(.Lpcrel_hi10)(a4)
+# CHECK-PIC-RV64: ld    a4, %pcrel_lo(.Lpcrel_hi10)(a4)
 la a4, f1
 
-# CHECK: .Lpcrel_hi10:
+# CHECK: .Lpcrel_hi11:
 # CHECK: auipc a0, %tls_ie_pcrel_hi(a_symbol)
-# CHECK-RV32: lw    a0, %pcrel_lo(.Lpcrel_hi10)(a0)
-# CHECK-RV64: ld    a0, %pcrel_lo(.Lpcrel_hi10)(a0)
+# CHECK-RV32: lw    a0, %pcrel_lo(.Lpcrel_hi11)(a0)
+# CHECK-RV64: ld    a0, %pcrel_lo(.Lpcrel_hi11)(a0)
 la.tls.ie a0, a_symbol
 
-# CHECK: .Lpcrel_hi11:
+# CHECK: .Lpcrel_hi12:
 # CHECK: auipc a1, %tls_ie_pcrel_hi(another_symbol)
-# CHECK-RV32: lw    a1, %pcrel_lo(.Lpcrel_hi11)(a1)
-# CHECK-RV64: ld    a1, %pcrel_lo(.Lpcrel_hi11)(a1)
+# CHECK-RV32: lw    a1, %pcrel_lo(.Lpcrel_hi12)(a1)
+# CHECK-RV64: ld    a1, %pcrel_lo(.Lpcrel_hi12)(a1)
 la.tls.ie a1, another_symbol
 
 # Check that we can load the address of symbols that are spelled like a register
-# CHECK: .Lpcrel_hi12:
+# CHECK: .Lpcrel_hi13:
 # CHECK: auipc a2, %tls_ie_pcrel_hi(zero)
-# CHECK-RV32: lw    a2, %pcrel_lo(.Lpcrel_hi12)(a2)
-# CHECK-RV64: ld    a2, %pcrel_lo(.Lpcrel_hi12)(a2)
+# CHECK-RV32: lw    a2, %pcrel_lo(.Lpcrel_hi13)(a2)
+# CHECK-RV64: ld    a2, %pcrel_lo(.Lpcrel_hi13)(a2)
 la.tls.ie a2, zero
 
-# CHECK: .Lpcrel_hi13:
+# CHECK: .Lpcrel_hi14:
 # CHECK: auipc a3, %tls_ie_pcrel_hi(ra)
-# CHECK-RV32: lw    a3, %pcrel_lo(.Lpcrel_hi13)(a3)
-# CHECK-RV64: ld    a3, %pcrel_lo(.Lpcrel_hi13)(a3)
+# CHECK-RV32: lw    a3, %pcrel_lo(.Lpcrel_hi14)(a3)
+# CHECK-RV64: ld    a3, %pcrel_lo(.Lpcrel_hi14)(a3)
 la.tls.ie a3, ra
 
-# CHECK: .Lpcrel_hi14:
+# CHECK: .Lpcrel_hi15:
 # CHECK: auipc a4, %tls_ie_pcrel_hi(f1)
-# CHECK-RV32: lw    a4, %pcrel_lo(.Lpcrel_hi14)(a4)
-# CHECK-RV64: ld    a4, %pcrel_lo(.Lpcrel_hi14)(a4)
+# CHECK-RV32: lw    a4, %pcrel_lo(.Lpcrel_hi15)(a4)
+# CHECK-RV64: ld    a4, %pcrel_lo(.Lpcrel_hi15)(a4)
 la.tls.ie a4, f1
 
-# CHECK: .Lpcrel_hi15:
+# CHECK: .Lpcrel_hi16:
 # CHECK: auipc a0, %tls_gd_pcrel_hi(a_symbol)
-# CHECK: addi  a0, a0, %pcrel_lo(.Lpcrel_hi15)
+# CHECK: addi  a0, a0, %pcrel_lo(.Lpcrel_hi16)
 la.tls.gd a0, a_symbol
 
-# CHECK: .Lpcrel_hi16:
+# CHECK: .Lpcrel_hi17:
 # CHECK: auipc a1, %tls_gd_pcrel_hi(another_symbol)
-# CHECK: addi  a1, a1, %pcrel_lo(.Lpcrel_hi16)
+# CHECK: addi  a1, a1, %pcrel_lo(.Lpcrel_hi17)
 la.tls.gd a1, another_symbol
 
 # Check that we can load the address of symbols that are spelled like a register
-# CHECK: .Lpcrel_hi17:
+# CHECK: .Lpcrel_hi18:
 # CHECK: auipc a2, %tls_gd_pcrel_hi(zero)
-# CHECK: addi  a2, a2, %pcrel_lo(.Lpcrel_hi17)
+# CHECK: addi  a2, a2, %pcrel_lo(.Lpcrel_hi18)
 la.tls.gd a2, zero
 
-# CHECK: .Lpcrel_hi18:
+# CHECK: .Lpcrel_hi19:
 # CHECK: auipc a3, %tls_gd_pcrel_hi(ra)
-# CHECK: addi  a3, a3, %pcrel_lo(.Lpcrel_hi18)
+# CHECK: addi  a3, a3, %pcrel_lo(.Lpcrel_hi19)
 la.tls.gd a3, ra
 
-# CHECK: .Lpcrel_hi19:
+# CHECK: .Lpcrel_hi20:
 # CHECK: auipc a4, %tls_gd_pcrel_hi(f1)
-# CHECK: addi  a4, a4, %pcrel_lo(.Lpcrel_hi19)
+# CHECK: addi  a4, a4, %pcrel_lo(.Lpcrel_hi20)
 la.tls.gd a4, f1
 
-# CHECK: .Lpcrel_hi20:
+# CHECK: .Lpcrel_hi21:
 # CHECK: auipc a0, %pcrel_hi(a_symbol)
-# CHECK: lb  a0, %pcrel_lo(.Lpcrel_hi20)(a0)
+# CHECK: lb  a0, %pcrel_lo(.Lpcrel_hi21)(a0)
 lb a0, a_symbol
 
-# CHECK: .Lpcrel_hi21:
+# CHECK: .Lpcrel_hi22:
 # CHECK: auipc a1, %pcrel_hi(a_symbol)
-# CHECK: lh  a1, %pcrel_lo(.Lpcrel_hi21)(a1)
+# CHECK: lh  a1, %pcrel_lo(.Lpcrel_hi22)(a1)
 lh a1, a_symbol
 
-# CHECK: .Lpcrel_hi22:
+# CHECK: .Lpcrel_hi23:
 # CHECK: auipc a2, %pcrel_hi(a_symbol)
-# CHECK: lhu  a2, %pcrel_lo(.Lpcrel_hi22)(a2)
+# CHECK: lhu  a2, %pcrel_lo(.Lpcrel_hi23)(a2)
 lhu a2, a_symbol
 
-# CHECK: .Lpcrel_hi23:
+# CHECK: .Lpcrel_hi24:
 # CHECK: auipc a3, %pcrel_hi(a_symbol)
-# CHECK: lw  a3, %pcrel_lo(.Lpcrel_hi23)(a3)
+# CHECK: lw  a3, %pcrel_lo(.Lpcrel_hi24)(a3)
 lw a3, a_symbol
 
-# CHECK: .Lpcrel_hi24:
+# CHECK: .Lpcrel_hi25:
 # CHECK: auipc a4, %pcrel_hi(a_symbol)
-# CHECK: sb  a3, %pcrel_lo(.Lpcrel_hi24)(a4)
+# CHECK: sb  a3, %pcrel_lo(.Lpcrel_hi25)(a4)
 sb a3, a_symbol, a4
 
-# CHECK: .Lpcrel_hi25:
+# CHECK: .Lpcrel_hi26:
 # CHECK: auipc a4, %pcrel_hi(a_symbol)
-# CHECK: sh  a3, %pcrel_lo(.Lpcrel_hi25)(a4)
+# CHECK: sh  a3, %pcrel_lo(.Lpcrel_hi26)(a4)
 sh a3, a_symbol, a4
 
-# CHECK: .Lpcrel_hi26:
+# CHECK: .Lpcrel_hi27:
 # CHECK: auipc a4, %pcrel_hi(a_symbol)
-# CHECK: sw  a3, %pcrel_lo(.Lpcrel_hi26)(a4)
+# CHECK: sw  a3, %pcrel_lo(.Lpcrel_hi27)(a4)
 sw a3, a_symbol, a4
 
 # Check that we can load the address of symbols that are spelled like a register
-# CHECK: .Lpcrel_hi27:
+# CHECK: .Lpcrel_hi28:
 # CHECK: auipc a2, %pcrel_hi(zero)
-# CHECK: lw  a2, %pcrel_lo(.Lpcrel_hi27)(a2)
+# CHECK: lw  a2, %pcrel_lo(.Lpcrel_hi28)(a2)
 lw a2, zero
 
-# CHECK: .Lpcrel_hi28:
+# CHECK: .Lpcrel_hi29:
 # CHECK: auipc a4, %pcrel_hi(zero)
-# CHECK: sw  a3, %pcrel_lo(.Lpcrel_hi28)(a4)
+# CHECK: sw  a3, %pcrel_lo(.Lpcrel_hi29)(a4)
 sw a3, zero, a4