[LLD][ELF] Implement option to force PIC compatible Thunks

[peter.smith]

Summary

By default LLD will generate position independent Thunks when the --pie or --shared option is used. Reference to absolute addresses is permitted in other cases. For some embedded systems position independent thunks are needed for code that executes before the MMU has been set up. The option --pic-veneer is used by ld.bfd to force position independent thunks.

The patch adds an option --pic-thunk with --pic-veneer as an alias to support this option. The --pic-veneer option is needed for the Linux kernel on Arm.

Fixes pr39886 (https://bugs.llvm.org/show_bug.cgi?id=39886)

[grimar]

You need to add the new option(s) to lld\docs\ld.lld.1 I think.

ELF/Driver.cpp

822 ↗

(On Diff #177485)

Should it have Config->Pic argument as a default (and a OPT_no_pic_thunk)?

Config->PicThunk = Args.hasArg(OPT_pic_thunk, OPT_no_pic_thunk, Config->Pic);

ELF/Thunks.cpp

653 ↗

(On Diff #177485)

Then you could remove this helper.

test/ELF/arm-force-pi-thunk.s

12 ↗

(On Diff #177485)

I would add empty lines before/after this comment.

[peter.smith]

Thanks very much for the comments, I've applied the suggested changes and updated the docs.

[grimar]

The code now looks good to me, thanks!
(I do not know much about ARM and thunks to give a sign off I think)

[falstaff84]

In my test case using Linux compiled for Arm using allyesconfig and ld.lld with these changes applied linking fails as follows:

...
ld.lld: error: relocation R_ARM_MOVT_PREL out of range: -4403772844 is not in [-2147483648, 2147483647]
...

I guess this is since we are using R_ARM_MOVT_PREL in ARMV7PILongThunk. Not sure whether we really care as this is more a constructed case with an insanely big kernel (with ld.bfd the linked kernel ends up at 201MiB!).

ld.bfd seems to use a different approach which allows the kernel to successfully link. See also:
https://lore.kernel.org/patchwork/patch/1021192/#1213770

[peter.smith]

In D55505#1342203, @falstaff84 wrote:

In my test case using Linux compiled for Arm using allyesconfig and ld.lld with these changes applied linking fails as follows:

...
ld.lld: error: relocation R_ARM_MOVT_PREL out of range: -4403772844 is not in [-2147483648, 2147483647]
...

I guess this is since we are using R_ARM_MOVT_PREL in ARMV7PILongThunk. Not sure whether we really care as this is more a constructed case with an insanely big kernel (with ld.bfd the linked kernel ends up at 201MiB!).

ld.bfd seems to use a different approach which allows the kernel to successfully link. See also:
https://lore.kernel.org/patchwork/patch/1021192/#1213770

I'll address the MOVT/MOVW relocation overflow when I get back to the office on Monday. At a first pass I think the overflow calculation for MOVT/MOVW isn't permissive enough, at least when used from the thunks. In any case I'll use a separate patch.

[ruiu]

Generally looking good.

What is a reason to add the option as --pic-thunk with an alias of --pic-veneer? If existing code uses --pic-veneer, maybe we could just add that option?

[peter.smith]

In D55505#1343979, @ruiu wrote:

Generally looking good.

What is a reason to add the option as --pic-thunk with an alias of --pic-veneer? If existing code uses --pic-veneer, maybe we could just add that option?

It was only to be consistent with LLD's use of thunk. I'll update the patch with just --pic-veneer as the command line option to select it.

[peter.smith]

Updated to remove --pic-thunk command line option. We now use only the ld.bfd option --pic-veneer. No other changes.

[peter.smith]

I've created D56396 to cover the relocation out of range errors seen when linking the linux kernel.

[peter.smith]

Ping. I think that all the currently requested changes have been made and the out of range link errors problem caused by enabling it has been fixed in D56396.

[ruiu]

LGTM

lld/trunk/ELF/Config.h

struct Configuration {
   bool LTONewPassManager;
   bool MergeArmExidx;
   bool MipsN32Abi = false;
   bool NoinhibitExec;
   bool Nostdlib;
   bool OFormatBinary;
   bool Omagic;
   bool OptRemarksWithHotness;
+  bool PicThunk;
   bool Pie;
   bool PrintGcSections;
   bool PrintIcfSections;
   bool Relocatable;
   bool RelrPackDynRelocs;
   bool SaveTemps;
   bool SingleRoRx;
   bool Shared;

lld/trunk/ELF/Driver.cpp

static void setConfigs(opt::InputArgList &Args) {
   uint16_t M = Config->EMachine;
 
   Config->CopyRelocs = (Config->Relocatable || Config->EmitRelocs);
   Config->Is64 = (K == ELF64LEKind || K == ELF64BEKind);
   Config->IsLE = (K == ELF32LEKind || K == ELF64LEKind);
   Config->Endianness = Config->IsLE ? endianness::little : endianness::big;
   Config->IsMips64EL = (K == ELF64LEKind && M == EM_MIPS);
   Config->Pic = Config->Pie || Config->Shared;
+  Config->PicThunk = Args.hasArg(OPT_pic_veneer, Config->Pic);
   Config->Wordsize = Config->Is64 ? 8 : 4;
 
   // ELF defines two different ways to store relocation addends as shown below:
   //
   //  Rel:  Addends are stored to the location where relocations are applied.
   //  Rela: Addends are stored as part of relocation entry.
   //
   // In other words, Rela makes it easy to read addends at the price of extra

lld/trunk/ELF/Options.td

 defm pack_dyn_relocs:
   Eq<"pack-dyn-relocs", "Pack dynamic relocations in the given format">,
   MetaVarName<"[none,android,relr,android+relr]">;
 
 defm use_android_relr_tags: B<"use-android-relr-tags",
     "Use SHT_ANDROID_RELR / DT_ANDROID_RELR* tags instead of SHT_RELR / DT_RELR*",
     "Use SHT_RELR / DT_RELR* tags (default)">;
 
+def pic_veneer: F<"pic-veneer">,
+  HelpText<"Always generate position independent thunks (veneers)">;
+
 defm pie: B<"pie",
     "Create a position independent executable",
     "Do not create a position independent executable (default)">;
 
 defm print_gc_sections: B<"print-gc-sections",
     "List removed unused sections",
     "Do not list removed unused sections (default)">;
 

lld/trunk/ELF/Thunks.cpp

 
 Thunk::Thunk(Symbol &D) : Destination(D), Offset(0) {}
 
 Thunk::~Thunk() = default;
 
 static Thunk *addThunkAArch64(RelType Type, Symbol &S) {
   if (Type != R_AARCH64_CALL26 && Type != R_AARCH64_JUMP26)
     fatal("unrecognized relocation type");
-  if (Config->Pic)
+  if (Config->PicThunk)
     return make<AArch64ADRPThunk>(S);
   return make<AArch64ABSLongThunk>(S);
 }
 
 // Creates a thunk for Thumb-ARM interworking.
 // Arm Architectures v5 and v6 do not support Thumb2 technology. This means
 // - MOVT and MOVW instructions cannot be used
 // - Only Thumb relocation that can generate a Thunk is a BL, this can always
 //   be transformed into a BLX
 static Thunk *addThunkPreArmv7(RelType Reloc, Symbol &S) {
   switch (Reloc) {
   case R_ARM_PC24:
   case R_ARM_PLT32:
   case R_ARM_JUMP24:
   case R_ARM_CALL:
   case R_ARM_THM_CALL:
-    if (Config->Pic)
+    if (Config->PicThunk)
       return make<ARMV5PILongThunk>(S);
     return make<ARMV5ABSLongThunk>(S);
   }
   fatal("relocation " + toString(Reloc) + " to " + toString(S) +
         " not supported for Armv5 or Armv6 targets");
 }
 
 // Create a thunk for Thumb long branch on V6-M.
if (!Config->ARMHasMovtMovw) {
     return addThunkV6M(Reloc, S);
   }
 
   switch (Reloc) {
   case R_ARM_PC24:
   case R_ARM_PLT32:
   case R_ARM_JUMP24:
   case R_ARM_CALL:
-    if (Config->Pic)
+    if (Config->PicThunk)
       return make<ARMV7PILongThunk>(S);
     return make<ARMV7ABSLongThunk>(S);
   case R_ARM_THM_JUMP19:
   case R_ARM_THM_JUMP24:
   case R_ARM_THM_CALL:
-    if (Config->Pic)
+    if (Config->PicThunk)
       return make<ThumbV7PILongThunk>(S);
     return make<ThumbV7ABSLongThunk>(S);
   }
   fatal("unrecognized relocation type");
 }
 
 static Thunk *addThunkMips(RelType Type, Symbol &S) {
   if ((S.StOther & STO_MIPS_MICROMIPS) && isMipsR6())
     return make<MicroMipsR6Thunk>(S);
   if (S.StOther & STO_MIPS_MICROMIPS)
     return make<MicroMipsThunk>(S);
   return make<MipsThunk>(S);
 }
 
 static Thunk *addThunkPPC64(RelType Type, Symbol &S) {
   assert(Type == R_PPC64_REL24 && "unexpected relocation type for thunk");
   if (S.isInPlt())
     return make<PPC64PltCallStub>(S);
 
-  if (Config->Pic)
+  if (Config->PicThunk)
     return make<PPC64PILongBranchThunk>(S);
 
   return make<PPC64PDLongBranchThunk>(S);
 }
 
 Thunk *addThunk(RelType Type, Symbol &S) {
   if (Config->EMachine == EM_AARCH64)
     return addThunkAArch64(Type, S);

lld/trunk/docs/ld.lld.1

 which produces output with no ELF header.
 .It Fl -omagic , Fl N
 Set the text and data sections to be readable and writable.
 .It Fl -opt-remarks-filename Ar file
 Write optimization remarks in YAML format to
 .Ar file .
 .It Fl -opt-remarks-with-hotness
 Include hotness information in the optimization remarks file.
+.It Fl -pic-veneer
+Always generate position independent thunks.
 .It Fl -pie
 Create a position independent executable.
 .It Fl -print-gc-sections
 List removed unused sections.
 .It Fl -print-icf-sections
 List identical folded sections.
 .It Fl -print-map
 Print a link map to the standard output.

lld/trunk/test/ELF/arm-force-pi-thunk.s

+// REQUIRES: arm
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
+// RUN: echo "SECTIONS { \
+// RUN:       . = SIZEOF_HEADERS; \
+// RUN:       .text_low : { *(.text_low) *(.text_low2) } \
+// RUN:       .text_high 0x2000000 : { *(.text_high) *(.text_high2) } \
+// RUN:       } " > %t.script
+// RUN: ld.lld --pic-veneer --script %t.script %t -o %t2 2>&1
+// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck %s
+
+// Test that we can force generation of position independent thunks even when
+// inputs are not pic.
+
+ .syntax unified
+ .section .text_low, "ax", %progbits
+ .thumb
+ .globl _start
+_start: bx lr
+ .globl low_target
+ .type low_target, %function
+low_target:
+ bl high_target
+ bl high_target2
+
+ .section .text_low2, "ax", %progbits
+ .thumb
+ .globl low_target2
+ .type low_target2, %function
+low_target2:
+ bl high_target
+ bl high_target2
+
+// CHECK: Disassembly of section .text_low:
+// CHECK-NEXT: _start:
+// CHECK-NEXT:       94:        70 47   bx      lr
+// CHECK: low_target:
+// CHECK-NEXT:       96:        00 f0 03 f8     bl      #6
+// CHECK-NEXT:       9a:        00 f0 07 f8     bl      #14
+// CHECK-NEXT:       9e:        d4 d4   bmi     #-88
+// CHECK: __ThumbV7PILongThunk_high_target:
+// CHECK-NEXT:       a0:        4f f6 55 7c     movw    r12, #65365
+// CHECK-NEXT:       a4:        c0 f2 ff 1c     movt    r12, #511
+// CHECK-NEXT:       a8:        fc 44   add     r12, pc
+// CHECK-NEXT:       aa:        60 47   bx      r12
+// CHECK: __ThumbV7PILongThunk_high_target2:
+// CHECK-NEXT:       ac:        4f f6 69 7c     movw    r12, #65385
+// CHECK-NEXT:       b0:        c0 f2 ff 1c     movt    r12, #511
+// CHECK-NEXT:       b4:        fc 44   add     r12, pc
+// CHECK-NEXT:       b6:        60 47   bx      r12
+// CHECK: low_target2:
+// CHECK-NEXT:       b8:        ff f7 f2 ff     bl      #-28
+// CHECK-NEXT:       bc:        ff f7 f6 ff     bl      #-20
+
+
+ .section .text_high, "ax", %progbits
+ .thumb
+ .globl high_target
+ .type high_target, %function
+high_target:
+ bl low_target
+ bl low_target2
+
+ .section .text_high2, "ax", %progbits
+ .thumb
+ .globl high_target2
+ .type high_target2, %function
+high_target2:
+ bl low_target
+ bl low_target2
+
+// CHECK: Disassembly of section .text_high:
+// CHECK-NEXT: high_target:
+// CHECK-NEXT:  2000000:        00 f0 02 f8     bl      #4
+// CHECK-NEXT:  2000004:        00 f0 06 f8     bl      #12
+// CHECK: __ThumbV7PILongThunk_low_target:
+// CHECK-NEXT:  2000008:        40 f2 83 0c     movw    r12, #131
+// CHECK-NEXT:  200000c:        cf f6 00 6c     movt    r12, #65024
+// CHECK-NEXT:  2000010:        fc 44   add     r12, pc
+// CHECK-NEXT:  2000012:        60 47   bx      r12
+// CHECK: __ThumbV7PILongThunk_low_target2:
+// CHECK-NEXT:  2000014:        40 f2 99 0c     movw    r12, #153
+// CHECK-NEXT:  2000018:        cf f6 00 6c     movt    r12, #65024
+// CHECK-NEXT:  200001c:        fc 44   add     r12, pc
+// CHECK-NEXT:  200001e:        60 47   bx      r12
+// CHECK: high_target2:
+// CHECK-NEXT:  2000020:        ff f7 f2 ff     bl      #-28
+// CHECK-NEXT:  2000024:        ff f7 f6 ff     bl      #-20