llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)

[MaskRay]

Summary

The convenience wrapper in STLExtras is available since rL342102.

[MaskRay]

.

[MaskRay]

Reflow nearby lines with: git diff -U0 --no-color 'HEAD^' | ~/llvm/tools/clang/tools/clang-format/clang-format-diff.py -i -p1

[dblaikie]

Haven't looked through all these manually, but sed seems reliable enough + clang-format (btw, if you use git, you can use git-clang-format to reformat everything in your change too)

[MaskRay]

In D52573#1247331, @dblaikie wrote:

Haven't looked through all these manually, but sed seems reliable enough + clang-format (btw, if you use git, you can use git-clang-format to reformat everything in your change too)

Thanks! I'll take a look at clang/tools/clang-format/git-clang-format

include/llvm/Analysis/LoopInfoImpl.h

for (DenseMap<BasicBlock*, LoopT*>::const_iterator I = BBMap.begin(),
          E = BBMap.end(); I != E; ++I)
     OS << "BB '" << I->first->getName() << "' level = "
        << I->second->getLoopDepth() << "\n";
 #endif
 }
 
 template <typename T>
 bool compareVectors(std::vector<T> &BB1, std::vector<T> &BB2) {
-  llvm::sort(BB1.begin(), BB1.end());
-  llvm::sort(BB2.begin(), BB2.end());
+  llvm::sort(BB1);
+  llvm::sort(BB2);
   return BB1 == BB2;
 }
 
 template <class BlockT, class LoopT>
 void addInnerLoopsToHeadersMap(DenseMap<BlockT *, const LoopT *> &LoopHeaders,
                                const LoopInfoBase<BlockT, LoopT> &LI,
                                const LoopT &L) {
   LoopHeaders[L.getHeader()] = &L;

include/llvm/CodeGen/SlotIndexes.h

void insertMBBInMaps(MachineBasicBlock *mbb) {
       MBBRanges[prevMBB->getNumber()].second = startIdx;
 
       assert(unsigned(mbb->getNumber()) == MBBRanges.size() &&
              "Blocks must be added in order");
       MBBRanges.push_back(std::make_pair(startIdx, endIdx));
       idx2MBBMap.push_back(IdxMBBPair(startIdx, mbb));
 
       renumberIndexes(newItr);
-      llvm::sort(idx2MBBMap.begin(), idx2MBBMap.end(), Idx2MBBCompare());
+      llvm::sort(idx2MBBMap, Idx2MBBCompare());
     }
 
     /// Free the resources that were required to maintain a SlotIndex.
     ///
     /// Once an index is no longer needed (for instance because the instruction
     /// at that index has been moved), the resources required to maintain the
     /// index can be relinquished to reduce memory use and improve renumbering
     /// performance. Any remaining SlotIndex objects that point to the same

include/llvm/ProfileData/InstrProf.h

Error InstrProfSymtab::create(const NameIterRange &IterRange) {
 
   finalizeSymtab();
   return Error::success();
 }
 
 void InstrProfSymtab::finalizeSymtab() {
   if (Sorted)
     return;
-  llvm::sort(MD5NameMap.begin(), MD5NameMap.end(), less_first());
-  llvm::sort(MD5FuncMap.begin(), MD5FuncMap.end(), less_first());
-  llvm::sort(AddrToMD5Map.begin(), AddrToMD5Map.end(), less_first());
+  llvm::sort(MD5NameMap, less_first());
+  llvm::sort(MD5FuncMap, less_first());
+  llvm::sort(AddrToMD5Map, less_first());
   AddrToMD5Map.erase(std::unique(AddrToMD5Map.begin(), AddrToMD5Map.end()),
                      AddrToMD5Map.end());
   Sorted = true;
 }
 
 StringRef InstrProfSymtab::getFuncNameOrExternalSymbol(uint64_t FuncMD5Hash) {
   StringRef ret = getFuncName(FuncMD5Hash);
   if (ret.empty())

include/llvm/Support/CFGUpdate.h

void LegalizeUpdates(ArrayRef<Update<NodePtr>> AllUpdates,
   for (size_t i = 0, e = AllUpdates.size(); i != e; ++i) {
     const auto &U = AllUpdates[i];
     if (!InverseGraph)
       Operations[{U.getFrom(), U.getTo()}] = int(i);
     else
       Operations[{U.getTo(), U.getFrom()}] = int(i);
   }
 
-  llvm::sort(Result.begin(), Result.end(),
+  llvm::sort(Result,
              [&Operations](const Update<NodePtr> &A, const Update<NodePtr> &B) {
                return Operations[{A.getFrom(), A.getTo()}] >
                       Operations[{B.getFrom(), B.getTo()}];
              });
 }
 
 } // end namespace cfg
 } // end namespace llvm
 
 #endif // LLVM_SUPPORT_CFGUPDATE_H

include/llvm/Support/GenericDomTreeConstruction.h

for (const auto &NodeToTN : DT.DomTreeNodes) {
         }
 
         continue;
       }
 
       // Make a copy and sort it such that it is possible to check if there are
       // no gaps between DFS numbers of adjacent children.
       SmallVector<TreeNodePtr, 8> Children(Node->begin(), Node->end());
-      llvm::sort(Children.begin(), Children.end(),
+      llvm::sort(Children,
                  [](const TreeNodePtr Ch1, const TreeNodePtr Ch2) {
                    return Ch1->getDFSNumIn() < Ch2->getDFSNumIn();
                  });
 
       auto PrintChildrenError = [Node, &Children, PrintNodeAndDFSNums](
           const TreeNodePtr FirstCh, const TreeNodePtr SecondCh) {
         assert(FirstCh);
 

include/llvm/Support/ScopedPrinter.h

for (const auto &Flag : Flags) {
         EnumMask = EnumMask3;
       bool IsEnum = (Flag.Value & EnumMask) != 0;
       if ((!IsEnum && (Value & Flag.Value) == Flag.Value) ||
           (IsEnum && (Value & EnumMask) == Flag.Value)) {
         SetFlags.push_back(Flag);
       }
     }
 
-    llvm::sort(SetFlags.begin(), SetFlags.end(), &flagName<TFlag>);
+    llvm::sort(SetFlags, &flagName<TFlag>);
 
     startLine() << Label << " [ (" << hex(Value) << ")\n";
     for (const auto &Flag : SetFlags) {
       startLine() << "  " << Flag.Name << " (" << hex(Flag.Value) << ")\n";
     }
     startLine() << "]\n";
   }
 

lib/Analysis/BlockFrequencyInfoImpl.cpp

if (W.Amount > W.Amount + OtherW.Amount)
     // Saturate on overflow.
     W.Amount = UINT64_MAX;
   else
     W.Amount += OtherW.Amount;
 }
 
 static void combineWeightsBySorting(WeightList &Weights) {
   // Sort so edges to the same node are adjacent.
-  llvm::sort(Weights.begin(), Weights.end(),
+  llvm::sort(Weights,
              [](const Weight &L,
                 const Weight &R) { return L.TargetNode < R.TargetNode; });
 
   // Combine adjacent edges.
   WeightList::iterator O = Weights.begin();
   for (WeightList::const_iterator I = O, L = O, E = Weights.end(); I != E;
        ++O, (I = L)) {
     *O = *I;
for (const auto *P : make_range(Irr.pred_begin(), Irr.pred_end())) {
                         << "\n");
       break;
     }
   }
   assert(Headers.size() >= 2 &&
          "Expected irreducible CFG; -loop-info is likely invalid");
   if (Headers.size() == InSCC.size()) {
     // Every block is a header.
-    llvm::sort(Headers.begin(), Headers.end());
+    llvm::sort(Headers);
     return;
   }
 
   // Look for extra headers from irreducible sub-SCCs.
   for (const auto &I : InSCC) {
     // Entry blocks are already headers.
     if (I.second)
       continue;
for (const auto &I : InSCC) {
     if (Headers.back() == Irr.Node)
       // Added this as a header.
       continue;
 
     // This is not a header.
     Others.push_back(Irr.Node);
     LLVM_DEBUG(dbgs() << "  => other = " << BFI.getBlockName(Irr.Node) << "\n");
   }
-  llvm::sort(Headers.begin(), Headers.end());
-  llvm::sort(Others.begin(), Others.end());
+  llvm::sort(Headers);
+  llvm::sort(Others);
 }
 
 static void createIrreducibleLoop(
     BlockFrequencyInfoImplBase &BFI, const IrreducibleGraph &G,
     LoopData *OuterLoop, std::list<LoopData>::iterator Insert,
     const std::vector<const IrreducibleGraph::IrrNode *> &SCC) {
   // Translate the SCC into RPO.
   LLVM_DEBUG(dbgs() << " - found-scc\n");

lib/Analysis/CFLAndersAliasAnalysis.cpp

for (const auto &OuterMapping : ReachSet.value_mappings()) {
     auto &AliasList = AliasMap[Val];
     for (const auto &InnerMapping : OuterMapping.second) {
       // Again, AliasMap only cares about top-level values
       if (InnerMapping.first.DerefLevel == 0)
         AliasList.push_back(OffsetValue{InnerMapping.first.Val, UnknownOffset});
     }
 
     // Sort AliasList for faster lookup
-    llvm::sort(AliasList.begin(), AliasList.end());
+    llvm::sort(AliasList);
   }
 }
 
 static void populateExternalRelations(
     SmallVectorImpl<ExternalRelation> &ExtRelations, const Function &Fn,
     const SmallVectorImpl<Value *> &RetVals, const ReachabilitySet &ReachSet) {
   // If a function only returns one of its argument X, then X will be both an
   // argument and a return value at the same time. This is an edge case that
for (const auto &FromRecord : Mapping.second.FromRecords) {
         ExtRelations.push_back(ExternalRelation{
             InterfaceValue{SrcIndex, SrcLevel},
             InterfaceValue{DstIndex, DstLevel}, UnknownOffset});
       }
     }
   }
 
   // Remove duplicates in ExtRelations
-  llvm::sort(ExtRelations.begin(), ExtRelations.end());
+  llvm::sort(ExtRelations);
   ExtRelations.erase(std::unique(ExtRelations.begin(), ExtRelations.end()),
                      ExtRelations.end());
 }
 
 static void populateExternalAttributes(
     SmallVectorImpl<ExternalAttribute> &ExtAttributes, const Function &Fn,
     const SmallVectorImpl<Value *> &RetVals, const AliasAttrMap &AMap) {
   for (const auto &Mapping : AMap.mappings()) {

lib/Analysis/CallGraph.cpp

void CallGraph::print(raw_ostream &OS) const {
   // this here to avoid slowing down the non-printing fast path.
 
   SmallVector<CallGraphNode *, 16> Nodes;
   Nodes.reserve(FunctionMap.size());
 
   for (const auto &I : *this)
     Nodes.push_back(I.second.get());
 
-  llvm::sort(Nodes.begin(), Nodes.end(),
+  llvm::sort(Nodes,
              [](CallGraphNode *LHS, CallGraphNode *RHS) {
     if (Function *LF = LHS->getFunction())
       if (Function *RF = RHS->getFunction())
         return LF->getName() < RF->getName();
 
     return RHS->getFunction() != nullptr;
   });
 

lib/Analysis/MemoryDependenceAnalysis.cpp

if (!Cache.empty()) {
 
     // If we already have a partially computed set of results, scan them to
     // determine what is dirty, seeding our initial DirtyBlocks worklist.
     for (auto &Entry : Cache)
       if (Entry.getResult().isDirty())
         DirtyBlocks.push_back(Entry.getBB());
 
     // Sort the cache so that we can do fast binary search lookups below.
-    llvm::sort(Cache.begin(), Cache.end());
+    llvm::sort(Cache);
 
     ++NumCacheDirtyNonLocal;
     // cerr << "CACHED CASE: " << DirtyBlocks.size() << " dirty: "
     //     << Cache.size() << " cached: " << *QueryInst;
   } else {
     // Seed DirtyBlocks with each of the preds of QueryInst's block.
     BasicBlock *QueryBB = QueryCS.getInstruction()->getParent();
     for (BasicBlock *Pred : PredCache.get(QueryBB))
if (Cache.size() != 1) {
       Cache.pop_back();
       MemoryDependenceResults::NonLocalDepInfo::iterator Entry =
           std::upper_bound(Cache.begin(), Cache.end(), Val);
       Cache.insert(Entry, Val);
     }
     break;
   default:
     // Added many values, do a full scale sort.
-    llvm::sort(Cache.begin(), Cache.end());
+    llvm::sort(Cache);
     break;
   }
 }
 
 /// Perform a dependency query based on pointer/pointeesize starting at the end
 /// of StartBB.
 ///
 /// Add any clobber/def results to the results vector and keep track of which
for (ValueIsLoadPair P : ReversePtrDepIt->second) {
         Entry.setResult(NewDirtyVal);
 
         if (Instruction *NewDirtyInst = NewDirtyVal.getInst())
           ReversePtrDepsToAdd.push_back(std::make_pair(NewDirtyInst, P));
       }
 
       // Re-sort the NonLocalDepInfo.  Changing the dirty entry to its
       // subsequent value may invalidate the sortedness.
-      llvm::sort(NLPDI.begin(), NLPDI.end());
+      llvm::sort(NLPDI);
     }
 
     ReverseNonLocalPtrDeps.erase(ReversePtrDepIt);
 
     while (!ReversePtrDepsToAdd.empty()) {
       ReverseNonLocalPtrDeps[ReversePtrDepsToAdd.back().first].insert(
           ReversePtrDepsToAdd.back().second);
       ReversePtrDepsToAdd.pop_back();

lib/Analysis/ScalarEvolution.cpp

for (const SCEV *T : Terms)
       dbgs() << *T << "\n";
   });
 
   // Remove duplicates.
   array_pod_sort(Terms.begin(), Terms.end());
   Terms.erase(std::unique(Terms.begin(), Terms.end()), Terms.end());
 
   // Put larger terms first.
-  llvm::sort(Terms.begin(), Terms.end(), [](const SCEV *LHS, const SCEV *RHS) {
+  llvm::sort(Terms, [](const SCEV *LHS, const SCEV *RHS) {
     return numberOfTerms(LHS) > numberOfTerms(RHS);
   });
 
   // Try to divide all terms by the element size. If term is not divisible by
   // element size, proceed with the original term.
   for (const SCEV *&Term : Terms) {
     const SCEV *Q, *R;
     SCEVDivision::divide(*this, Term, ElementSize, &Q, &R);

lib/Analysis/ScalarEvolutionExpander.cpp

SCEVExpander::replaceCongruentIVs(Loop *L, const DominatorTree *DT,
                                   SmallVectorImpl<WeakTrackingVH> &DeadInsts,
                                   const TargetTransformInfo *TTI) {
   // Find integer phis in order of increasing width.
   SmallVector<PHINode*, 8> Phis;
   for (PHINode &PN : L->getHeader()->phis())
     Phis.push_back(&PN);
 
   if (TTI)
-    llvm::sort(Phis.begin(), Phis.end(), [](Value *LHS, Value *RHS) {
+    llvm::sort(Phis, [](Value *LHS, Value *RHS) {
       // Put pointers at the back and make sure pointer < pointer = false.
       if (!LHS->getType()->isIntegerTy() || !RHS->getType()->isIntegerTy())
         return RHS->getType()->isIntegerTy() && !LHS->getType()->isIntegerTy();
       return RHS->getType()->getPrimitiveSizeInBits() <
              LHS->getType()->getPrimitiveSizeInBits();
     });
 
   unsigned NumElim = 0;

lib/Analysis/TargetLibraryInfo.cpp

 }
 
 static bool compareWithVectorFnName(const VecDesc &LHS, StringRef S) {
   return LHS.VectorFnName < S;
 }
 
 void TargetLibraryInfoImpl::addVectorizableFunctions(ArrayRef<VecDesc> Fns) {
   VectorDescs.insert(VectorDescs.end(), Fns.begin(), Fns.end());
-  llvm::sort(VectorDescs.begin(), VectorDescs.end(), compareByScalarFnName);
+  llvm::sort(VectorDescs, compareByScalarFnName);
 
   ScalarDescs.insert(ScalarDescs.end(), Fns.begin(), Fns.end());
-  llvm::sort(ScalarDescs.begin(), ScalarDescs.end(), compareByVectorFnName);
+  llvm::sort(ScalarDescs, compareByVectorFnName);
 }
 
 void TargetLibraryInfoImpl::addVectorizableFunctionsFromVecLib(
     enum VectorLibrary VecLib) {
   switch (VecLib) {
   case Accelerate: {
     const VecDesc VecFuncs[] = {
         // Floating-Point Arithmetic and Auxiliary Functions

lib/Bitcode/Reader/ValueList.cpp

 /// references.  The idea behind this is that we sometimes get constants (such
 /// as large arrays) which reference *many* forward ref constants.  Replacing
 /// each of these causes a lot of thrashing when building/reuniquing the
 /// constant.  Instead of doing this, we look at all the uses and rewrite all
 /// the place holders at once for any constant that uses a placeholder.
 void BitcodeReaderValueList::resolveConstantForwardRefs() {
   // Sort the values by-pointer so that they are efficient to look up with a
   // binary search.
-  llvm::sort(ResolveConstants.begin(), ResolveConstants.end());
+  llvm::sort(ResolveConstants);
 
   SmallVector<Constant *, 64> NewOps;
 
   while (!ResolveConstants.empty()) {
     Value *RealVal = operator[](ResolveConstants.back().second);
     Constant *Placeholder = ResolveConstants.back().first;
     ResolveConstants.pop_back();
 

lib/Bitcode/Writer/ValueEnumerator.cpp

for (const Use &U : V->uses())
     if (OM.lookup(U.getUser()).first)
       List.push_back(std::make_pair(&U, List.size()));
 
   if (List.size() < 2)
     // We may have lost some users.
     return;
 
   bool IsGlobalValue = OM.isGlobalValue(ID);
-  llvm::sort(List.begin(), List.end(), [&](const Entry &L, const Entry &R) {
+  llvm::sort(List, [&](const Entry &L, const Entry &R) {
     const Use *LU = L.first;
     const Use *RU = R.first;
     if (LU == RU)
       return false;
 
     auto LID = OM.lookup(LU->getUser()).first;
     auto RID = OM.lookup(RU->getUser()).first;
 
for (const Metadata *MD : MDs)
     Order.push_back(MetadataMap.lookup(MD));
 
   // Partition:
   //   - by function, then
   //   - by isa<MDString>
   // and then sort by the original/current ID.  Since the IDs are guaranteed to
   // be unique, the result of std::sort will be deterministic.  There's no need
   // for std::stable_sort.
-  llvm::sort(Order.begin(), Order.end(), [this](MDIndex LHS, MDIndex RHS) {
+  llvm::sort(Order, [this](MDIndex LHS, MDIndex RHS) {
     return std::make_tuple(LHS.F, getMetadataTypeOrder(LHS.get(MDs)), LHS.ID) <
            std::make_tuple(RHS.F, getMetadataTypeOrder(RHS.get(MDs)), RHS.ID);
   });
 
   // Rebuild MDs, index the metadata ranges for each function in FunctionMDs,
   // and fix up MetadataMap.
   std::vector<const Metadata *> OldMDs = std::move(MDs);
   MDs.reserve(OldMDs.size());

lib/CodeGen/AsmPrinter/CodeViewDebug.cpp

 }
 
 void CodeViewDebug::emitLocalVariableList(ArrayRef<LocalVariable> Locals) {
   // Get the sorted list of parameters and emit them first.
   SmallVector<const LocalVariable *, 6> Params;
   for (const LocalVariable &L : Locals)
     if (L.DIVar->isParameter())
       Params.push_back(&L);
-  llvm::sort(Params.begin(), Params.end(),
+  llvm::sort(Params,
              [](const LocalVariable *L, const LocalVariable *R) {
                return L->DIVar->getArg() < R->DIVar->getArg();
              });
   for (const LocalVariable *L : Params)
     emitLocalVariable(*L);
 
   // Next emit all non-parameters in the order that we found them.
   for (const LocalVariable &L : Locals)

lib/CodeGen/AsmPrinter/DebugLocEntry.h

void addValues(ArrayRef<DebugLocEntry::Value> Vals) {
     assert(all_of(Values, [](DebugLocEntry::Value V) {
           return V.isFragment();
         }) && "value must be a piece");
   }
 
   // Sort the pieces by offset.
   // Remove any duplicate entries by dropping all but the first.
   void sortUniqueValues() {
-    llvm::sort(Values.begin(), Values.end());
+    llvm::sort(Values);
     Values.erase(
         std::unique(
             Values.begin(), Values.end(), [](const Value &A, const Value &B) {
               return A.getExpression() == B.getExpression();
             }),
         Values.end());
   }
 

lib/CodeGen/AsmPrinter/DwarfDebug.cpp

ArrayRef<DbgVariable::FrameIndexExpr> DbgVariable::getFrameIndexExprs() const {
   if (FrameIndexExprs.size() == 1)
     return FrameIndexExprs;
 
   assert(llvm::all_of(FrameIndexExprs,
                       [](const FrameIndexExpr &A) {
                         return A.Expr->isFragment();
                       }) &&
          "multiple FI expressions without DW_OP_LLVM_fragment");
-  llvm::sort(FrameIndexExprs.begin(), FrameIndexExprs.end(),
+  llvm::sort(FrameIndexExprs,
              [](const FrameIndexExpr &A, const FrameIndexExpr &B) -> bool {
                return A.Expr->getFragmentInfo()->OffsetInBits <
                       B.Expr->getFragmentInfo()->OffsetInBits;
              });
 
   return FrameIndexExprs;
 }
 
if (isa<DILocalScope>(N->getScope()))
     return;
   if (DIE *D = TheCU.getOrCreateContextDIE(N->getScope()))
     D->addChild(TheCU.constructImportedEntityDIE(N));
 }
 
 /// Sort and unique GVEs by comparing their fragment offset.
 static SmallVectorImpl<DwarfCompileUnit::GlobalExpr> &
 sortGlobalExprs(SmallVectorImpl<DwarfCompileUnit::GlobalExpr> &GVEs) {
-  llvm::sort(GVEs.begin(), GVEs.end(),
+  llvm::sort(GVEs,
              [](DwarfCompileUnit::GlobalExpr A,
                 DwarfCompileUnit::GlobalExpr B) {
                // Sort order: first null exprs, then exprs without fragment
                // info, then sort by fragment offset in bits.
                // FIXME: Come up with a more comprehensive comparator so
                // the sorting isn't non-deterministic, and so the following
                // std::unique call works correctly.
                if (!A.Expr || !B.Expr)
void DwarfDebug::emitDebugARanges() {
   // Build a list of CUs used.
   std::vector<DwarfCompileUnit *> CUs;
   for (const auto &it : Spans) {
     DwarfCompileUnit *CU = it.first;
     CUs.push_back(CU);
   }
 
   // Sort the CU list (again, to ensure consistent output order).
-  llvm::sort(CUs.begin(), CUs.end(),
+  llvm::sort(CUs,
              [](const DwarfCompileUnit *A, const DwarfCompileUnit *B) {
                return A->getUniqueID() < B->getUniqueID();
              });
 
   // Emit an arange table for each CU we used.
   for (DwarfCompileUnit *CU : CUs) {
     std::vector<ArangeSpan> &List = Spans[CU];
 

lib/CodeGen/AsmPrinter/EHStreamer.cpp

void EHStreamer::emitExceptionTable() {
   // duplicate actions.
   SmallVector<const LandingPadInfo *, 64> LandingPads;
   LandingPads.reserve(PadInfos.size());
 
   for (unsigned i = 0, N = PadInfos.size(); i != N; ++i)
     LandingPads.push_back(&PadInfos[i]);
 
   // Order landing pads lexicographically by type id.
-  llvm::sort(LandingPads.begin(), LandingPads.end(),
+  llvm::sort(LandingPads,
              [](const LandingPadInfo *L,
                 const LandingPadInfo *R) { return L->TypeIds < R->TypeIds; });
 
   // Compute the actions table and gather the first action index for each
   // landing pad site.
   SmallVector<ActionEntry, 32> Actions;
   SmallVector<unsigned, 64> FirstActions;
   computeActionsTable(LandingPads, Actions, FirstActions);

lib/CodeGen/CodeGenPrepare.cpp

auto compareGEPOffset =
             const std::pair<GetElementPtrInst *, int64_t> &RHS) {
           if (LHS.first == RHS.first)
             return false;
           if (LHS.second != RHS.second)
             return LHS.second < RHS.second;
           return LargeOffsetGEPID[LHS.first] < LargeOffsetGEPID[RHS.first];
         };
     // Sorting all the GEPs of the same data structures based on the offsets.
-    llvm::sort(LargeOffsetGEPs.begin(), LargeOffsetGEPs.end(),
+    llvm::sort(LargeOffsetGEPs,
                compareGEPOffset);
     LargeOffsetGEPs.erase(
         std::unique(LargeOffsetGEPs.begin(), LargeOffsetGEPs.end()),
         LargeOffsetGEPs.end());
     // Skip if all the GEPs have the same offsets.
     if (LargeOffsetGEPs.front().second == LargeOffsetGEPs.back().second)
       continue;
     GetElementPtrInst *BaseGEP = LargeOffsetGEPs.begin()->first;

lib/CodeGen/GlobalISel/LegalizerInfo.cpp

for (unsigned TypeIdx = 0; TypeIdx != SpecifiedActions[OpcodeIdx].size();
           assert(BitsizeAndAction.first % ElementSize == 0);
           const uint16_t NumElements = BitsizeAndAction.first / ElementSize;
           NumElementsActions.push_back({NumElements, BitsizeAndAction.second});
         }
         setVectorNumElementAction(
             Opcode, TypeIdx, ElementSize,
             moreToWiderTypesAndLessToWidest(NumElementsActions));
       }
-      llvm::sort(ElementSizesSeen.begin(), ElementSizesSeen.end());
+      llvm::sort(ElementSizesSeen);
       SizeChangeStrategy VectorElementSizeChangeStrategy =
           &unsupportedForDifferentSizes;
       if (TypeIdx < VectorElementSizeChangeStrategies[OpcodeIdx].size() &&
           VectorElementSizeChangeStrategies[OpcodeIdx][TypeIdx] != nullptr)
         VectorElementSizeChangeStrategy =
             VectorElementSizeChangeStrategies[OpcodeIdx][TypeIdx];
       setScalarInVectorAction(
           Opcode, TypeIdx, VectorElementSizeChangeStrategy(ElementSizesSeen));

lib/CodeGen/LocalStackSlotAllocation.cpp

for (MachineInstr &MI : BB) {
           break;
         }
       }
     }
   }
 
   // Sort the frame references by local offset.
   // Use frame index as a tie-breaker in case MI's have the same offset.
-  llvm::sort(FrameReferenceInsns.begin(), FrameReferenceInsns.end());
+  llvm::sort(FrameReferenceInsns);
 
   MachineBasicBlock *Entry = &Fn.front();
 
   unsigned BaseReg = 0;
   int64_t BaseOffset = 0;
 
   // Loop through the frame references and allocate for them as necessary.
   for (int ref = 0, e = FrameReferenceInsns.size(); ref < e ; ++ref) {

lib/CodeGen/MIRCanonicalizerPass.cpp

for (auto *II : instructions) {
     II->print(OS);
     OS.flush();
 
     // Trim the assignment, or start from the begining in the case of a store.
     const size_t i = S.find("=");
     StringInstrMap.push_back({(i == std::string::npos) ? S : S.substr(i), II});
   }
 
-  llvm::sort(StringInstrMap.begin(), StringInstrMap.end(),
+  llvm::sort(StringInstrMap,
             [](const StringInstrPair &a, const StringInstrPair &b) -> bool {
               return (a.first < b.first);
             });
 
   for (auto &II : StringInstrMap) {
 
     LLVM_DEBUG({
       dbgs() << "Splicing ";

lib/CodeGen/MachineBasicBlock.cpp

 
 bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) const {
   livein_iterator I = find_if(
       LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
   return I != livein_end() && (I->LaneMask & LaneMask).any();
 }
 
 void MachineBasicBlock::sortUniqueLiveIns() {
-  llvm::sort(LiveIns.begin(), LiveIns.end(),
+  llvm::sort(LiveIns,
              [](const RegisterMaskPair &LI0, const RegisterMaskPair &LI1) {
                return LI0.PhysReg < LI1.PhysReg;
              });
   // Liveins are sorted by physreg now we can merge their lanemasks.
   LiveInVector::const_iterator I = LiveIns.begin();
   LiveInVector::const_iterator J;
   LiveInVector::iterator Out = LiveIns.begin();
   for (; I != LiveIns.end(); ++Out, I = J) {

lib/CodeGen/MachinePipeliner.cpp

if (NS.size() <= 2)
       continue;
     IntervalPressure RecRegPressure;
     RegPressureTracker RecRPTracker(RecRegPressure);
     RecRPTracker.init(&MF, &RegClassInfo, &LIS, BB, BB->end(), false, true);
     computeLiveOuts(MF, RecRPTracker, NS);
     RecRPTracker.closeBottom();
 
     std::vector<SUnit *> SUnits(NS.begin(), NS.end());
-    llvm::sort(SUnits.begin(), SUnits.end(),
+    llvm::sort(SUnits,
                [](const SUnit *A, const SUnit *B) {
       return A->NodeNum > B->NodeNum;
     });
 
     for (auto &SU : SUnits) {
       // Since we're computing the register pressure for a subset of the
       // instructions in a block, we need to set the tracker for each
       // instruction in the node-set. The tracker is set to the instruction
void SwingSchedulerDAG::checkValidNodeOrder(const NodeSetType &Circuits) const {
   for (unsigned i = 0, s = NodeOrder.size(); i < s; ++i)
     Indices.push_back(std::make_pair(NodeOrder[i], i));
 
   auto CompareKey = [](UnitIndex i1, UnitIndex i2) {
     return std::get<0>(i1) < std::get<0>(i2);
   };
 
   // sort, so that we can perform a binary search
-  llvm::sort(Indices.begin(), Indices.end(), CompareKey);
+  llvm::sort(Indices, CompareKey);
 
   bool Valid = true;
   (void)Valid;
   // for each SUnit in the NodeOrder, check whether
   // it appears after both a successor and a predecessor
   // of the SUnit. If this is the case, and the SUnit
   // is not part of circuit, then the NodeOrder is not
   // valid.

lib/CodeGen/MachineScheduler.cpp

for (SUnit *SU : MemOps) {
     unsigned BaseReg;
     int64_t Offset;
     if (TII->getMemOpBaseRegImmOfs(*SU->getInstr(), BaseReg, Offset, TRI))
       MemOpRecords.push_back(MemOpInfo(SU, BaseReg, Offset));
   }
   if (MemOpRecords.size() < 2)
     return;
 
-  llvm::sort(MemOpRecords.begin(), MemOpRecords.end());
+  llvm::sort(MemOpRecords);
   unsigned ClusterLength = 1;
   for (unsigned Idx = 0, End = MemOpRecords.size(); Idx < (End - 1); ++Idx) {
     SUnit *SUa = MemOpRecords[Idx].SU;
     SUnit *SUb = MemOpRecords[Idx+1].SU;
     if (TII->shouldClusterMemOps(*SUa->getInstr(), MemOpRecords[Idx].BaseReg,
                                  *SUb->getInstr(), MemOpRecords[Idx+1].BaseReg,
                                  ClusterLength) &&
         DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {

lib/CodeGen/ReachingDefAnalysis.cpp

bool ReachingDefAnalysis::runOnMachineFunction(MachineFunction &mf) {
   LoopTraversal::TraversalOrder TraversedMBBOrder = Traversal.traverse(mf);
   for (LoopTraversal::TraversedMBBInfo TraversedMBB : TraversedMBBOrder) {
     processBasicBlock(TraversedMBB);
   }
 
   // Sorting all reaching defs found for a ceartin reg unit in a given BB.
   for (MBBDefsInfo &MBBDefs : MBBReachingDefs) {
     for (MBBRegUnitDefs &RegUnitDefs : MBBDefs)
-      llvm::sort(RegUnitDefs.begin(), RegUnitDefs.end());
+      llvm::sort(RegUnitDefs);
   }
 
   return false;
 }
 
 void ReachingDefAnalysis::releaseMemory() {
   // Clear the internal vectors.
   MBBOutRegsInfos.clear();

lib/CodeGen/ScheduleDAGInstrs.cpp

void ScheduleDAGInstrs::reduceHugeMemNodeMaps(Value2SUsMap &stores,
   std::vector<unsigned> NodeNums;
   NodeNums.reserve(stores.size() + loads.size());
   for (auto &I : stores)
     for (auto *SU : I.second)
       NodeNums.push_back(SU->NodeNum);
   for (auto &I : loads)
     for (auto *SU : I.second)
       NodeNums.push_back(SU->NodeNum);
-  llvm::sort(NodeNums.begin(), NodeNums.end());
+  llvm::sort(NodeNums);
 
   // The N last elements in NodeNums will be removed, and the SU with
   // the lowest NodeNum of them will become the new BarrierChain to
   // let the not yet seen SUs have a dependency to the removed SUs.
   assert(N <= NodeNums.size());
   SUnit *newBarrierChain = &SUnits[*(NodeNums.end() - N)];
   if (BarrierChain) {
     // The aliasing and non-aliasing maps reduce independently of each

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

static void adjustCostForPairing(SmallVectorImpl<LoadedSlice> &LoadedSlices,
                                  LoadedSlice::Cost &GlobalLSCost) {
   unsigned NumberOfSlices = LoadedSlices.size();
   // If there is less than 2 elements, no pairing is possible.
   if (NumberOfSlices < 2)
     return;
 
   // Sort the slices so that elements that are likely to be next to each
   // other in memory are next to each other in the list.
-  llvm::sort(LoadedSlices.begin(), LoadedSlices.end(),
+  llvm::sort(LoadedSlices,
              [](const LoadedSlice &LHS, const LoadedSlice &RHS) {
     assert(LHS.Origin == RHS.Origin && "Different bases not implemented.");
     return LHS.getOffsetFromBase() < RHS.getOffsetFromBase();
   });
   const TargetLowering &TLI = LoadedSlices[0].DAG->getTargetLoweringInfo();
   // First (resp. Second) is the first (resp. Second) potentially candidate
   // to be placed in a paired load.
   const LoadedSlice *First = nullptr;
bool DAGCombiner::MergeConsecutiveStores(StoreSDNode *St) {
   getStoreMergeCandidates(St, StoreNodes, RootNode);
 
   // Check if there is anything to merge.
   if (StoreNodes.size() < 2)
     return false;
 
   // Sort the memory operands according to their distance from the
   // base pointer.
-  llvm::sort(StoreNodes.begin(), StoreNodes.end(),
+  llvm::sort(StoreNodes,
              [](MemOpLink LHS, MemOpLink RHS) {
                return LHS.OffsetFromBase < RHS.OffsetFromBase;
              });
 
   // Store Merge attempts to merge the lowest stores. This generally
   // works out as if successful, as the remaining stores are checked
   // after the first collection of stores is merged. However, in the
   // case that a non-mergeable store is found first, e.g., {p[-2],

lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
     // Reset UseCount to allow more matches.
     UseCount = 0;
   }
 
   if (!Cluster)
     return;
 
   // Sort them in increasing order.
-  llvm::sort(Offsets.begin(), Offsets.end());
+  llvm::sort(Offsets);
 
   // Check if the loads are close enough.
   SmallVector<SDNode*, 4> Loads;
   unsigned NumLoads = 0;
   int64_t BaseOff = Offsets[0];
   SDNode *BaseLoad = O2SMap[BaseOff];
   Loads.push_back(BaseLoad);
   for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

for (SDNode::use_iterator UI = FromNode->use_begin(),
       if (Use.getResNo() == FromResNo) {
         UseMemo Memo = { *UI, i, &Use };
         Uses.push_back(Memo);
       }
     }
   }
 
   // Sort the uses, so that all the uses from a given User are together.
-  llvm::sort(Uses.begin(), Uses.end());
+  llvm::sort(Uses);
 
   for (unsigned UseIndex = 0, UseIndexEnd = Uses.size();
        UseIndex != UseIndexEnd; ) {
     // We know that this user uses some value of From.  If it is the right
     // value, update it.
     SDNode *User = Uses[UseIndex].User;
 
     // This node is about to morph, remove its old self from the CSE maps.

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 }
 
 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
 #ifndef NDEBUG
   for (const CaseCluster &CC : Clusters)
     assert(CC.Low == CC.High && "Input clusters must be single-case");
 #endif
 
-  llvm::sort(Clusters.begin(), Clusters.end(),
+  llvm::sort(Clusters,
              [](const CaseCluster &a, const CaseCluster &b) {
     return a.Low->getValue().slt(b.Low->getValue());
   });
 
   // Merge adjacent clusters with the same destination.
   const unsigned N = Clusters.size();
   unsigned DstIndex = 0;
   for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
for (unsigned Op = 1, N = I.getNumArgOperands(); Op != N; Op += 2) {
       auto *GA = dyn_cast<GlobalAddressSDNode>(Val);
       if (!GA)
         report_fatal_error(
             "llvm.icall.branch.funnel operand must be a GlobalValue");
       Targets.push_back({Offset, DAG.getTargetGlobalAddress(
                                      GA->getGlobal(), getCurSDLoc(),
                                      Val.getValueType(), GA->getOffset())});
     }
-    llvm::sort(Targets.begin(), Targets.end(),
+    llvm::sort(Targets,
                [](const BranchFunnelTarget &T1, const BranchFunnelTarget &T2) {
                  return T1.Offset < T2.Offset;
                });
 
     for (auto &T : Targets) {
       Ops.push_back(DAG.getTargetConstant(T.Offset, getCurSDLoc(), MVT::i32));
       Ops.push_back(T.Target);
     }
for (unsigned i = First; i <= Last; ++i) {
     assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
     CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
     CB->Bits += Hi - Lo + 1;
     CB->ExtraProb += Clusters[i].Prob;
     TotalProb += Clusters[i].Prob;
   }
 
   BitTestInfo BTI;
-  llvm::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
+  llvm::sort(CBV, [](const CaseBits &a, const CaseBits &b) {
     // Sort by probability first, number of bits second, bit mask third.
     if (a.ExtraProb != b.ExtraProb)
       return a.ExtraProb > b.ExtraProb;
     if (a.Bits != b.Bits)
       return a.Bits > b.Bits;
     return a.Mask < b.Mask;
   });
 

lib/CodeGen/SlotIndexes.cpp

for (MachineBasicBlock &MBB : *mf) {
 
     MBBRanges[MBB.getNumber()].first = blockStartIndex;
     MBBRanges[MBB.getNumber()].second = SlotIndex(&indexList.back(),
                                                    SlotIndex::Slot_Block);
     idx2MBBMap.push_back(IdxMBBPair(blockStartIndex, &MBB));
   }
 
   // Sort the Idx2MBBMap
-  llvm::sort(idx2MBBMap.begin(), idx2MBBMap.end(), Idx2MBBCompare());
+  llvm::sort(idx2MBBMap, Idx2MBBCompare());
 
   LLVM_DEBUG(mf->print(dbgs(), this));
 
   // And we're done!
   return false;
 }
 
 void SlotIndexes::removeMachineInstrFromMaps(MachineInstr &MI) {

lib/CodeGen/StackColoring.cpp

std::stable_sort(SortedSlots.begin(), SortedSlots.end(),
     // We use -1 to denote a uninteresting slot. Place these slots at the end.
     if (LHS == -1) return false;
     if (RHS == -1) return true;
     // Sort according to size.
     return MFI->getObjectSize(LHS) > MFI->getObjectSize(RHS);
   });
 
   for (auto &s : LiveStarts)
-    llvm::sort(s.begin(), s.end());
+    llvm::sort(s);
 
   bool Changed = true;
   while (Changed) {
     Changed = false;
     for (unsigned I = 0; I < NumSlots; ++I) {
       if (SortedSlots[I] == -1)
         continue;
 

lib/CodeGen/StackMaps.cpp

StackMaps::parseRegisterLiveOutMask(const uint32_t *Mask) const {
   for (unsigned Reg = 0, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg)
     if ((Mask[Reg / 32] >> Reg % 32) & 1)
       LiveOuts.push_back(createLiveOutReg(Reg, TRI));
 
   // We don't need to keep track of a register if its super-register is already
   // in the list. Merge entries that refer to the same dwarf register and use
   // the maximum size that needs to be spilled.
 
-  llvm::sort(LiveOuts.begin(), LiveOuts.end(),
+  llvm::sort(LiveOuts,
              [](const LiveOutReg &LHS, const LiveOutReg &RHS) {
                // Only sort by the dwarf register number.
                return LHS.DwarfRegNum < RHS.DwarfRegNum;
              });
 
   for (auto I = LiveOuts.begin(), E = LiveOuts.end(); I != E; ++I) {
     for (auto II = std::next(I); II != E; ++II) {
       if (I->DwarfRegNum != II->DwarfRegNum) {

lib/CodeGen/StackSlotColoring.cpp

void StackSlotColoring::InitializeSlots() {
 
   using Pair = std::iterator_traits<LiveStacks::iterator>::value_type;
 
   SmallVector<Pair *, 16> Intervals;
 
   Intervals.reserve(LS->getNumIntervals());
   for (auto &I : *LS)
     Intervals.push_back(&I);
-  llvm::sort(Intervals.begin(), Intervals.end(),
+  llvm::sort(Intervals,
              [](Pair *LHS, Pair *RHS) { return LHS->first < RHS->first; });
 
   // Gather all spill slots into a list.
   LLVM_DEBUG(dbgs() << "Spill slot intervals:\n");
   for (auto *I : Intervals) {
     LiveInterval &li = I->second;
     LLVM_DEBUG(li.dump());
     int FI = TargetRegisterInfo::stackSlot2Index(li.reg);

lib/DebugInfo/CodeView/DebugCrossImpSubsection.cpp

Error DebugCrossModuleImportsSubsection::commit(
     BinaryStreamWriter &Writer) const {
   using T = decltype(&*Mappings.begin());
   std::vector<T> Ids;
   Ids.reserve(Mappings.size());
 
   for (const auto &M : Mappings)
     Ids.push_back(&M);
 
-  llvm::sort(Ids.begin(), Ids.end(), [this](const T &L1, const T &L2) {
+  llvm::sort(Ids, [this](const T &L1, const T &L2) {
     return Strings.getIdForString(L1->getKey()) <
            Strings.getIdForString(L2->getKey());
   });
 
   for (const auto &Item : Ids) {
     CrossModuleImport Imp;
     Imp.ModuleNameOffset = Strings.getIdForString(Item->getKey());
     Imp.Count = Item->getValue().size();
     if (auto EC = Writer.writeObject(Imp))
       return EC;
     if (auto EC = Writer.writeArray(makeArrayRef(Item->getValue())))
       return EC;
   }
   return Error::success();
 }

lib/DebugInfo/CodeView/DebugStringTableSubsection.cpp

 
 uint32_t DebugStringTableSubsection::size() const { return StringToId.size(); }
 
 std::vector<uint32_t> DebugStringTableSubsection::sortedIds() const {
   std::vector<uint32_t> Result;
   Result.reserve(IdToString.size());
   for (const auto &Entry : IdToString)
     Result.push_back(Entry.first);
-  llvm::sort(Result.begin(), Result.end());
+  llvm::sort(Result);
   return Result;
 }
 
 uint32_t DebugStringTableSubsection::getIdForString(StringRef S) const {
   auto Iter = StringToId.find(S);
   assert(Iter != StringToId.end());
   return Iter->second;
 }
 
 StringRef DebugStringTableSubsection::getStringForId(uint32_t Id) const {
   auto Iter = IdToString.find(Id);
   assert(Iter != IdToString.end());
   return Iter->second;
 }

lib/DebugInfo/DWARF/DWARFContext.cpp

 static ContributionCollection
 collectContributionData(DWARFContext::unit_iterator_range Units) {
   ContributionCollection Contributions;
   for (const auto &U : Units)
     Contributions.push_back(U->getStringOffsetsTableContribution());
   // Sort the contributions so that any invalid ones are placed at
   // the start of the contributions vector. This way they are reported
   // first.
-  llvm::sort(Contributions.begin(), Contributions.end(),
+  llvm::sort(Contributions,
              [](const Optional<StrOffsetsContributionDescriptor> &L,
                 const Optional<StrOffsetsContributionDescriptor> &R) {
                if (L && R) return L->Base < R->Base;
                return R.hasValue();
              });
 
   // Uniquify contributions, as it is possible that units (specifically
   // type units in dwo or dwp files) share contributions. We don't want

lib/DebugInfo/DWARF/DWARFDebugAranges.cpp

if (LowPC >= HighPC)
     return;
   Endpoints.emplace_back(LowPC, CUOffset, true);
   Endpoints.emplace_back(HighPC, CUOffset, false);
 }
 
 void DWARFDebugAranges::construct() {
   std::multiset<uint32_t> ValidCUs;  // Maintain the set of CUs describing
                                      // a current address range.
-  llvm::sort(Endpoints.begin(), Endpoints.end());
+  llvm::sort(Endpoints);
   uint64_t PrevAddress = -1ULL;
   for (const auto &E : Endpoints) {
     if (PrevAddress < E.Address && !ValidCUs.empty()) {
       // If the address range between two endpoints is described by some
       // CU, first try to extend the last range in Aranges. If we can't
       // do it, start a new range.
       if (!Aranges.empty() && Aranges.back().HighPC() == PrevAddress &&
           ValidCUs.find(Aranges.back().CUOffset) != ValidCUs.end()) {

lib/DebugInfo/DWARF/DWARFDebugLine.cpp

Error DWARFDebugLine::LineTable::parse(
 
   if (!State.Sequence.Empty)
     RecoverableErrorCallback(
         createStringError(errc::illegal_byte_sequence,
                     "last sequence in debug line table is not terminated!"));
 
   // Sort all sequences so that address lookup will work faster.
   if (!Sequences.empty()) {
-    llvm::sort(Sequences.begin(), Sequences.end(), Sequence::orderByLowPC);
+    llvm::sort(Sequences, Sequence::orderByLowPC);
     // Note: actually, instruction address ranges of sequences should not
     // overlap (in shared objects and executables). If they do, the address
     // lookup would still work, though, but result would be ambiguous.
     // We don't report warning in this case. For example,
     // sometimes .so compiled from multiple object files contains a few
     // rudimentary sequences for address ranges [0x0, 0xsomething).
   }
 

lib/DebugInfo/PDB/Native/GSIStreamBuilder.cpp

for (size_t BucketIdx = 0; BucketIdx < IPHR_HASH + 1; ++BucketIdx) {
     HashBuckets.push_back(ChainStartOff);
 
     // Sort each bucket by memcmp of the symbol's name.  It's important that
     // we use the same sorting algorithm as is used by the reference
     // implementation to ensure that the search for a record within a bucket
     // can properly early-out when it detects the record won't be found.  The
     // algorithm used here corredsponds to the function
     // caseInsensitiveComparePchPchCchCch in the reference implementation.
-    llvm::sort(Bucket.begin(), Bucket.end(),
+    llvm::sort(Bucket,
               [](const std::pair<StringRef, PSHashRecord> &Left,
                  const std::pair<StringRef, PSHashRecord> &Right) {
                 return gsiRecordLess(Left.first, Right.first);
               });
 
     for (const auto &Entry : Bucket)
       HashRecords.push_back(Entry.second);
   }

lib/IR/AsmWriter.cpp

static void predictValueUseListOrderImpl(const Value *V, const Function *F,
   if (List.size() < 2)
     // We may have lost some users.
     return;
 
   bool GetsReversed =
       !isa<GlobalVariable>(V) && !isa<Function>(V) && !isa<BasicBlock>(V);
   if (auto *BA = dyn_cast<BlockAddress>(V))
     ID = OM.lookup(BA->getBasicBlock()).first;
-  llvm::sort(List.begin(), List.end(), [&](const Entry &L, const Entry &R) {
+  llvm::sort(List, [&](const Entry &L, const Entry &R) {
     const Use *LU = L.first;
     const Use *RU = R.first;
     if (LU == RU)
       return false;
 
     auto LID = OM.lookup(LU->getUser()).first;
     auto RID = OM.lookup(RU->getUser()).first;
 

lib/IR/Attributes.cpp

AttributeSetNode *AttributeSetNode::get(LLVMContext &C,
   if (Attrs.empty())
     return nullptr;
 
   // Otherwise, build a key to look up the existing attributes.
   LLVMContextImpl *pImpl = C.pImpl;
   FoldingSetNodeID ID;
 
   SmallVector<Attribute, 8> SortedAttrs(Attrs.begin(), Attrs.end());
-  llvm::sort(SortedAttrs.begin(), SortedAttrs.end());
+  llvm::sort(SortedAttrs);
 
   for (const auto Attr : SortedAttrs)
     Attr.Profile(ID);
 
   void *InsertPoint;
   AttributeSetNode *PA =
     pImpl->AttrsSetNodes.FindNodeOrInsertPos(ID, InsertPoint);
 

lib/IR/Metadata.cpp

 
 void ReplaceableMetadataImpl::replaceAllUsesWith(Metadata *MD) {
   if (UseMap.empty())
     return;
 
   // Copy out uses since UseMap will get touched below.
   using UseTy = std::pair<void *, std::pair<OwnerTy, uint64_t>>;
   SmallVector<UseTy, 8> Uses(UseMap.begin(), UseMap.end());
-  llvm::sort(Uses.begin(), Uses.end(), [](const UseTy &L, const UseTy &R) {
+  llvm::sort(Uses, [](const UseTy &L, const UseTy &R) {
     return L.second.second < R.second.second;
   });
   for (const auto &Pair : Uses) {
     // Check that this Ref hasn't disappeared after RAUW (when updating a
     // previous Ref).
     if (!UseMap.count(Pair.first))
       continue;
 
void ReplaceableMetadataImpl::resolveAllUses(bool ResolveUsers) {
   if (!ResolveUsers) {
     UseMap.clear();
     return;
   }
 
   // Copy out uses since UseMap could get touched below.
   using UseTy = std::pair<void *, std::pair<OwnerTy, uint64_t>>;
   SmallVector<UseTy, 8> Uses(UseMap.begin(), UseMap.end());
-  llvm::sort(Uses.begin(), Uses.end(), [](const UseTy &L, const UseTy &R) {
+  llvm::sort(Uses, [](const UseTy &L, const UseTy &R) {
     return L.second.second < R.second.second;
   });
   UseMap.clear();
   for (const auto &Pair : Uses) {
     auto Owner = Pair.second.first;
     if (!Owner)
       continue;
     if (Owner.is<MetadataAsValue *>())

lib/IR/Verifier.cpp

void Verifier::visitBasicBlock(BasicBlock &BB) {
   // Ensure that basic blocks have terminators!
   Assert(BB.getTerminator(), "Basic Block does not have terminator!", &BB);
 
   // Check constraints that this basic block imposes on all of the PHI nodes in
   // it.
   if (isa<PHINode>(BB.front())) {
     SmallVector<BasicBlock*, 8> Preds(pred_begin(&BB), pred_end(&BB));
     SmallVector<std::pair<BasicBlock*, Value*>, 8> Values;
-    llvm::sort(Preds.begin(), Preds.end());
+    llvm::sort(Preds);
     for (const PHINode &PN : BB.phis()) {
       // Ensure that PHI nodes have at least one entry!
       Assert(PN.getNumIncomingValues() != 0,
              "PHI nodes must have at least one entry.  If the block is dead, "
              "the PHI should be removed!",
              &PN);
       Assert(PN.getNumIncomingValues() == Preds.size(),
              "PHINode should have one entry for each predecessor of its "
              "parent basic block!",
              &PN);
 
       // Get and sort all incoming values in the PHI node...
       Values.clear();
       Values.reserve(PN.getNumIncomingValues());
       for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i)
         Values.push_back(
             std::make_pair(PN.getIncomingBlock(i), PN.getIncomingValue(i)));
-      llvm::sort(Values.begin(), Values.end());
+      llvm::sort(Values);
 
       for (unsigned i = 0, e = Values.size(); i != e; ++i) {
         // Check to make sure that if there is more than one entry for a
         // particular basic block in this PHI node, that the incoming values are
         // all identical.
         //
         Assert(i == 0 || Values[i].first != Values[i - 1].first ||
                    Values[i].second == Values[i - 1].second,

lib/LTO/ThinLTOCodeGenerator.cpp

void ThinLTOCodeGenerator::run() {
   }
 
   // Compute the ordering we will process the inputs: the rough heuristic here
   // is to sort them per size so that the largest module get schedule as soon as
   // possible. This is purely a compile-time optimization.
   std::vector<int> ModulesOrdering;
   ModulesOrdering.resize(Modules.size());
   std::iota(ModulesOrdering.begin(), ModulesOrdering.end(), 0);
-  llvm::sort(ModulesOrdering.begin(), ModulesOrdering.end(),
+  llvm::sort(ModulesOrdering,
              [&](int LeftIndex, int RightIndex) {
                auto LSize = Modules[LeftIndex].getBuffer().size();
                auto RSize = Modules[RightIndex].getBuffer().size();
                return LSize > RSize;
              });
 
   // Parallel optimizer + codegen
   {

lib/MC/MachObjectWriter.cpp

for (const MCSymbol &Symbol : Asm.symbols()) {
     } else {
       MSD.SectionIndex = SectionIndexMap.lookup(&Symbol.getSection());
       assert(MSD.SectionIndex && "Invalid section index!");
       LocalSymbolData.push_back(MSD);
     }
   }
 
   // External and undefined symbols are required to be in lexicographic order.
-  llvm::sort(ExternalSymbolData.begin(), ExternalSymbolData.end());
-  llvm::sort(UndefinedSymbolData.begin(), UndefinedSymbolData.end());
+  llvm::sort(ExternalSymbolData);
+  llvm::sort(UndefinedSymbolData);
 
   // Set the symbol indices.
   Index = 0;
   for (auto *SymbolData :
        {&LocalSymbolData, &ExternalSymbolData, &UndefinedSymbolData})
     for (MachSymbolData &Entry : *SymbolData)
       Entry.Symbol->setIndex(Index++);
 

lib/MC/WinCOFFObjectWriter.cpp

 // Write the section header.
 void WinCOFFObjectWriter::writeSectionHeaders() {
   // Section numbers must be monotonically increasing in the section
   // header, but our Sections array is not sorted by section number,
   // so make a copy of Sections and sort it.
   std::vector<COFFSection *> Arr;
   for (auto &Section : Sections)
     Arr.push_back(Section.get());
-  llvm::sort(Arr.begin(), Arr.end(),
+  llvm::sort(Arr,
              [](const COFFSection *A, const COFFSection *B) {
                return A->Number < B->Number;
              });
 
   for (auto &Section : Arr) {
     if (Section->Number == -1)
       continue;
 

lib/ProfileData/Coverage/CoverageMapping.cpp

Counter CounterExpressionBuilder::simplify(Counter ExpressionTree) {
   extractTerms(ExpressionTree, +1, Terms);
 
   // If there are no terms, this is just a zero. The algorithm below assumes at
   // least one term.
   if (Terms.size() == 0)
     return Counter::getZero();
 
   // Group the terms by counter ID.
-  llvm::sort(Terms.begin(), Terms.end(), [](const Term &LHS, const Term &RHS) {
+  llvm::sort(Terms, [](const Term &LHS, const Term &RHS) {
     return LHS.CounterID < RHS.CounterID;
   });
 
   // Combine terms by counter ID to eliminate counters that sum to zero.
   auto Prev = Terms.begin();
   for (auto I = Prev + 1, E = Terms.end(); I != E; ++I) {
     if (I->CounterID == Prev->CounterID) {
       Prev->Factor += I->Factor;
void buildSegmentsImpl(ArrayRef<CountedRegion> Regions) {
 
     // Complete any remaining active regions.
     if (!ActiveRegions.empty())
       completeRegionsUntil(None, 0);
   }
 
   /// Sort a nested sequence of regions from a single file.
   static void sortNestedRegions(MutableArrayRef<CountedRegion> Regions) {
-    llvm::sort(Regions.begin(), Regions.end(), [](const CountedRegion &LHS,
+    llvm::sort(Regions, [](const CountedRegion &LHS,
                                                   const CountedRegion &RHS) {
       if (LHS.startLoc() != RHS.startLoc())
         return LHS.startLoc() < RHS.startLoc();
       if (LHS.endLoc() != RHS.endLoc())
         // When LHS completely contains RHS, we sort LHS first.
         return RHS.endLoc() < LHS.endLoc();
       // If LHS and RHS cover the same area, we need to sort them according
       // to their kinds so that the most suitable region will become "active"

 
 } // end anonymous namespace
 
 std::vector<StringRef> CoverageMapping::getUniqueSourceFiles() const {
   std::vector<StringRef> Filenames;
   for (const auto &Function : getCoveredFunctions())
     Filenames.insert(Filenames.end(), Function.Filenames.begin(),
                      Function.Filenames.end());
-  llvm::sort(Filenames.begin(), Filenames.end());
+  llvm::sort(Filenames);
   auto Last = std::unique(Filenames.begin(), Filenames.end());
   Filenames.erase(Last, Filenames.end());
   return Filenames;
 }
 
 static SmallBitVector gatherFileIDs(StringRef SourceFile,
                                     const FunctionRecord &Function) {
   SmallBitVector FilenameEquivalence(Function.Filenames.size(), false);

lib/ProfileData/GCOV.cpp

 }
 
 /// print -  Print source files with collected line count information.
 void FileInfo::print(raw_ostream &InfoOS, StringRef MainFilename,
                      StringRef GCNOFile, StringRef GCDAFile) {
   SmallVector<StringRef, 4> Filenames;
   for (const auto &LI : LineInfo)
     Filenames.push_back(LI.first());
-  llvm::sort(Filenames.begin(), Filenames.end());
+  llvm::sort(Filenames);
 
   for (StringRef Filename : Filenames) {
     auto AllLines = LineConsumer(Filename);
 
     std::string CoveragePath = getCoveragePath(Filename, MainFilename);
     std::unique_ptr<raw_ostream> CovStream = openCoveragePath(CoveragePath);
     raw_ostream &CovOS = *CovStream;
 

lib/ProfileData/ProfileSummaryBuilder.cpp

for (const auto &I : FS.getBodySamples())
     addCount(I.second.getSamples());
 }
 
 // The argument to this method is a vector of cutoff percentages and the return
 // value is a vector of (Cutoff, MinCount, NumCounts) triplets.
 void ProfileSummaryBuilder::computeDetailedSummary() {
   if (DetailedSummaryCutoffs.empty())
     return;
-  llvm::sort(DetailedSummaryCutoffs.begin(), DetailedSummaryCutoffs.end());
+  llvm::sort(DetailedSummaryCutoffs);
   auto Iter = CountFrequencies.begin();
   const auto End = CountFrequencies.end();
 
   uint32_t CountsSeen = 0;
   uint64_t CurrSum = 0, Count = 0;
 
   for (const uint32_t Cutoff : DetailedSummaryCutoffs) {
     assert(Cutoff <= 999999);

lib/Support/JSON.cpp

Expected<Value> parse(StringRef JSON) {
   return P.takeError();
 }
 char ParseError::ID = 0;
 
 static std::vector<const Object::value_type *> sortedElements(const Object &O) {
   std::vector<const Object::value_type *> Elements;
   for (const auto &E : O)
     Elements.push_back(&E);
-  llvm::sort(Elements.begin(), Elements.end(),
+  llvm::sort(Elements,
              [](const Object::value_type *L, const Object::value_type *R) {
                return L->first < R->first;
              });
   return Elements;
 }
 
 bool isUTF8(llvm::StringRef S, size_t *ErrOffset) {
   // Fast-path for ASCII, which is valid UTF-8.

lib/Support/SourceMgr.cpp

 SMDiagnostic::SMDiagnostic(const SourceMgr &sm, SMLoc L, StringRef FN,
                            int Line, int Col, SourceMgr::DiagKind Kind,
                            StringRef Msg, StringRef LineStr,
                            ArrayRef<std::pair<unsigned,unsigned>> Ranges,
                            ArrayRef<SMFixIt> Hints)
   : SM(&sm), Loc(L), Filename(FN), LineNo(Line), ColumnNo(Col), Kind(Kind),
     Message(Msg), LineContents(LineStr), Ranges(Ranges.vec()),
     FixIts(Hints.begin(), Hints.end()) {
-  llvm::sort(FixIts.begin(), FixIts.end());
+  llvm::sort(FixIts);
 }
 
 static void buildFixItLine(std::string &CaretLine, std::string &FixItLine,
                            ArrayRef<SMFixIt> FixIts, ArrayRef<char> SourceLine){
   if (FixIts.empty())
     return;
 
   const char *LineStart = SourceLine.begin();

lib/Support/Timer.cpp

if (FirstTimer)
     FirstTimer->Prev = &T.Next;
   T.Next = FirstTimer;
   T.Prev = &FirstTimer;
   FirstTimer = &T;
 }
 
 void TimerGroup::PrintQueuedTimers(raw_ostream &OS) {
   // Sort the timers in descending order by amount of time taken.
-  llvm::sort(TimersToPrint.begin(), TimersToPrint.end());
+  llvm::sort(TimersToPrint);
 
   TimeRecord Total;
   for (const PrintRecord &Record : TimersToPrint)
     Total += Record.Time;
 
   // Print out timing header.
   OS << "===" << std::string(73, '-') << "===\n";
   // Figure out how many spaces to indent TimerGroup name.

lib/TableGen/Record.cpp

if (UnsortedClasses.empty()) {
     return &AnyRecord;
   }
 
   FoldingSet<RecordRecTy> &ThePool =
       UnsortedClasses[0]->getRecords().RecordTypePool;
 
   SmallVector<Record *, 4> Classes(UnsortedClasses.begin(),
                                    UnsortedClasses.end());
-  llvm::sort(Classes.begin(), Classes.end(),
+  llvm::sort(Classes,
              [](Record *LHS, Record *RHS) {
                return LHS->getNameInitAsString() < RHS->getNameInitAsString();
              });
 
   FoldingSetNodeID ID;
   ProfileRecordRecTy(ID, Classes);
 
   void *IP = nullptr;

lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

bool AArch64A57FPLoadBalancing::runOnBasicBlock(MachineBasicBlock &MBB) {
   for (auto I = EC.begin(), E = EC.end(); I != E; ++I) {
     std::vector<Chain*> Cs(EC.member_begin(I), EC.member_end());
     if (Cs.empty()) continue;
     V.push_back(std::move(Cs));
   }
 
   // Now we have a set of sets, order them by start address so
   // we can iterate over them sequentially.
-  llvm::sort(V.begin(), V.end(),
+  llvm::sort(V,
              [](const std::vector<Chain*> &A,
                 const std::vector<Chain*> &B) {
       return A.front()->startsBefore(B.front());
     });
 
   // As we only have two colors, we can track the global (BB-level) balance of
   // odds versus evens. We aim to keep this near zero to keep both execution
   // units fed.
bool AArch64A57FPLoadBalancing::colorChainSet(std::vector<Chain*> GV,
   // sets first.
   // Tie-break equivalent sizes by sorting chains requiring fixups before
   // those without fixups. The logic here is that we should look at the
   // chains that we cannot change before we look at those we can,
   // so the parity counter is updated and we know what color we should
   // change them to!
   // Final tie-break with instruction order so pass output is stable (i.e. not
   // dependent on malloc'd pointer values).
-  llvm::sort(GV.begin(), GV.end(), [](const Chain *G1, const Chain *G2) {
+  llvm::sort(GV, [](const Chain *G1, const Chain *G2) {
       if (G1->size() != G2->size())
         return G1->size() > G2->size();
       if (G1->requiresFixup() != G2->requiresFixup())
         return G1->requiresFixup() > G2->requiresFixup();
       // Make sure startsBefore() produces a stable final order.
       assert((G1 == G2 || (G1->startsBefore(G2) ^ G2->startsBefore(G1))) &&
              "Starts before not total order!");
       return G1->startsBefore(G2);

lib/Target/AMDGPU/GCNIterativeScheduler.cpp

|| (dbgs() << "Max RP mismatch!!!\n"
       dbgs() << "RP after scheduling: ",
       RegionMaxRP.print(dbgs(), &ST),
       false));
 }
 
 // Sort recorded regions by pressure - highest at the front
 void GCNIterativeScheduler::sortRegionsByPressure(unsigned TargetOcc) {
   const auto &ST = MF.getSubtarget<GCNSubtarget>();
-  llvm::sort(Regions.begin(), Regions.end(),
+  llvm::sort(Regions,
     [&ST, TargetOcc](const Region *R1, const Region *R2) {
     return R2->MaxPressure.less(ST, R1->MaxPressure, TargetOcc);
   });
 }
 
 ///////////////////////////////////////////////////////////////////////////////
 // Legacy MaxOccupancy Strategy
 

lib/Target/AMDGPU/SIFormMemoryClauses.cpp

for (unsigned Idx = 1; Idx < E; ++Idx) {
     }
 
     if ((SubRegMask & ~LaneMask).any() || (SubRegMask & LaneMask).none())
       continue;
 
     CoveringSubregs.push_back(Idx);
   }
 
-  llvm::sort(CoveringSubregs.begin(), CoveringSubregs.end(),
+  llvm::sort(CoveringSubregs,
              [this](unsigned A, unsigned B) {
                LaneBitmask MaskA = TRI->getSubRegIndexLaneMask(A);
                LaneBitmask MaskB = TRI->getSubRegIndexLaneMask(B);
                unsigned NA = MaskA.getNumLanes();
                unsigned NB = MaskB.getNumLanes();
                if (NA != NB)
                  return NA > NB;
                return MaskA.getHighestLane() > MaskB.getHighestLane();

lib/Target/ARM/ARMBaseInstrInfo.cpp

void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
   MachineOperand STBase(MI->getOperand(2));
   STM.add(STBase).add(predOps(ARMCC::AL));
 
   // Sort the scratch registers into ascending order.
   const TargetRegisterInfo &TRI = getRegisterInfo();
   SmallVector<unsigned, 6> ScratchRegs;
   for(unsigned I = 5; I < MI->getNumOperands(); ++I)
     ScratchRegs.push_back(MI->getOperand(I).getReg());
-  llvm::sort(ScratchRegs.begin(), ScratchRegs.end(),
+  llvm::sort(ScratchRegs,
              [&TRI](const unsigned &Reg1,
                     const unsigned &Reg2) -> bool {
                return TRI.getEncodingValue(Reg1) <
                       TRI.getEncodingValue(Reg2);
              });
 
   for (const auto &Reg : ScratchRegs) {
     LDM.addReg(Reg, RegState::Define);

lib/Target/ARM/ARMFrameLowering.cpp

for (; i != 0; --i) {
       // Omitting the kill flags is conservatively correct even if the live-in
       // is not used after all.
       Regs.push_back(std::make_pair(Reg, /*isKill=*/!isLiveIn));
     }
 
     if (Regs.empty())
       continue;
 
-    llvm::sort(Regs.begin(), Regs.end(), [&](const RegAndKill &LHS,
+    llvm::sort(Regs, [&](const RegAndKill &LHS,
                                              const RegAndKill &RHS) {
       return TRI.getEncodingValue(LHS.first) < TRI.getEncodingValue(RHS.first);
     });
 
     if (Regs.size() > 1 || StrOpc== 0) {
       MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
                                     .addReg(ARM::SP)
                                     .setMIFlags(MIFlags)
for (; i != 0; --i) {
 
       LastReg = Reg;
       Regs.push_back(Reg);
     }
 
     if (Regs.empty())
       continue;
 
-    llvm::sort(Regs.begin(), Regs.end(), [&](unsigned LHS, unsigned RHS) {
+    llvm::sort(Regs, [&](unsigned LHS, unsigned RHS) {
       return TRI.getEncodingValue(LHS) < TRI.getEncodingValue(RHS);
     });
 
     if (Regs.size() > 1 || LdrOpc == 0) {
       MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
                                     .addReg(ARM::SP)
                                     .add(predOps(ARMCC::AL));
       for (unsigned i = 0, e = Regs.size(); i < e; ++i)

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
   if (MemOps.size() > 0)
     FormCandidates(MemOps);
 
   // Sort candidates so they get processed from end to begin of the basic
   // block later; This is necessary for liveness calculation.
   auto LessThan = [](const MergeCandidate* M0, const MergeCandidate *M1) {
     return M0->InsertPos < M1->InsertPos;
   };
-  llvm::sort(Candidates.begin(), Candidates.end(), LessThan);
+  llvm::sort(Candidates, LessThan);
 
   // Go through list of candidates and merge.
   bool Changed = false;
   for (const MergeCandidate *Candidate : Candidates) {
     if (Candidate->CanMergeToLSMulti || Candidate->CanMergeToLSDouble) {
       MachineInstr *Merged = MergeOpsUpdate(*Candidate);
       // Merge preceding/trailing base inc/dec into the merged op.
       if (Merged) {

 
 bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
                                  SmallVectorImpl<MachineInstr *> &Ops,
                                  unsigned Base, bool isLd,
                                  DenseMap<MachineInstr*, unsigned> &MI2LocMap) {
   bool RetVal = false;
 
   // Sort by offset (in reverse order).
-  llvm::sort(Ops.begin(), Ops.end(),
+  llvm::sort(Ops,
              [](const MachineInstr *LHS, const MachineInstr *RHS) {
                int LOffset = getMemoryOpOffset(*LHS);
                int ROffset = getMemoryOpOffset(*RHS);
                assert(LHS == RHS || LOffset != ROffset);
                return LOffset > ROffset;
              });
 
   // The loads / stores of the same base are in order. Scan them from first to

lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp

if (FPU != ARM::FK_INVALID)
     emitFPUDefaultAttributes();
 
   if (Arch != ARM::ArchKind::INVALID)
     emitArchDefaultAttributes();
 
   if (Contents.empty())
     return;
 
-  llvm::sort(Contents.begin(), Contents.end(), AttributeItem::LessTag);
+  llvm::sort(Contents, AttributeItem::LessTag);
 
   ARMELFStreamer &Streamer = getStreamer();
 
   // Switch to .ARM.attributes section
   if (AttributeSection) {
     Streamer.SwitchSection(AttributeSection);
   } else {
     AttributeSection = Streamer.getContext().getELFSection(

lib/Target/Hexagon/HexagonConstExtenders.cpp

bool HCE::runOnMachineFunction(MachineFunction &MF) {
 
   HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
   HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
   MDT = &getAnalysis<MachineDominatorTree>();
   MRI = &MF.getRegInfo();
   AssignmentMap IMap;
 
   collect(MF);
-  llvm::sort(Extenders.begin(), Extenders.end(),
+  llvm::sort(Extenders,
     [](const ExtDesc &A, const ExtDesc &B) {
       return ExtValue(A) < ExtValue(B);
     });
 
   bool Changed = false;
   LLVM_DEBUG(dbgs() << "Collected " << Extenders.size() << " extenders\n");
   for (unsigned I = 0, E = Extenders.size(); I != E; ) {
     unsigned B = I;

lib/Target/Hexagon/HexagonGenInsert.cpp

void HexagonGenInsert::buildOrderingBT(RegisterOrdering &RB,
   BitValueOrdering BVO(RB);
   RegisterCellLexCompare LexCmp(BVO, *CMS);
 
   using SortableVectorType = std::vector<unsigned>;
 
   SortableVectorType VRs;
   for (RegisterOrdering::iterator I = RB.begin(), E = RB.end(); I != E; ++I)
     VRs.push_back(I->first);
-  llvm::sort(VRs.begin(), VRs.end(), LexCmp);
+  llvm::sort(VRs, LexCmp);
   // Transfer the results to the outgoing register ordering.
   for (unsigned i = 0, n = VRs.size(); i < n; ++i)
     RO.insert(std::make_pair(VRs[i], i));
 }
 
 inline bool HexagonGenInsert::isIntClass(const TargetRegisterClass *RC) const {
   return RC == &Hexagon::IntRegsRegClass || RC == &Hexagon::DoubleRegsRegClass;
 }

lib/Target/Hexagon/HexagonStoreWidening.cpp

bool HexagonStoreWidening::processBasicBlock(MachineBasicBlock &MBB) {
 
   createStoreGroups(MBB, SGs);
 
   auto Less = [] (const MachineInstr *A, const MachineInstr *B) -> bool {
     return getStoreOffset(A) < getStoreOffset(B);
   };
   for (auto &G : SGs) {
     assert(G.size() > 1 && "Store group with fewer than 2 elements");
-    llvm::sort(G.begin(), G.end(), Less);
+    llvm::sort(G, Less);
 
     Changed |= processStoreGroup(G);
   }
 
   return Changed;
 }
 
 bool HexagonStoreWidening::runOnMachineFunction(MachineFunction &MFn) {

lib/Target/Hexagon/RDFDeadCode.cpp

bool DeadCodeElimination::erase(const SetVector<NodeId> &Nodes) {
   auto UsesFirst = [] (NodeAddr<RefNode*> A, NodeAddr<RefNode*> B) -> bool {
     uint16_t KindA = A.Addr->getKind(), KindB = B.Addr->getKind();
     if (KindA == NodeAttrs::Use && KindB == NodeAttrs::Def)
       return true;
     if (KindA == NodeAttrs::Def && KindB == NodeAttrs::Use)
       return false;
     return A.Id < B.Id;
   };
-  llvm::sort(DRNs.begin(), DRNs.end(), UsesFirst);
+  llvm::sort(DRNs, UsesFirst);
 
   if (trace())
     dbgs() << "Removing dead ref nodes:\n";
   for (NodeAddr<RefNode*> RA : DRNs) {
     if (trace())
       dbgs() << "  " << PrintNode<RefNode*>(RA, DFG) << '\n';
     if (DFG.IsUse(RA))
       DFG.unlinkUse(RA, true);

lib/Target/Hexagon/RDFGraph.cpp

void DataFlowGraph::buildPhis(BlockRefsMap &PhiM, RegisterSet &AllRefs,
   for (RegisterRef I : MaxDF)
     MaxRefs.push_back(MaxCoverIn(I, AllRefs));
 
   // Now, for each R in MaxRefs, get the alias closure of R. If the closure
   // only has R in it, create a phi a def for R. Otherwise, create a phi,
   // and add a def for each S in the closure.
 
   // Sort the refs so that the phis will be created in a deterministic order.
-  llvm::sort(MaxRefs.begin(), MaxRefs.end());
+  llvm::sort(MaxRefs);
   // Remove duplicates.
   auto NewEnd = std::unique(MaxRefs.begin(), MaxRefs.end());
   MaxRefs.erase(NewEnd, MaxRefs.end());
 
   auto Aliased = [this,&MaxRefs](RegisterRef RR,
                                  std::vector<unsigned> &Closure) -> bool {
     for (unsigned I : Closure)
       if (PRI.alias(RR, MaxRefs[I]))

lib/Target/Hexagon/RDFLiveness.cpp

if (StmtA) {
         return false;
       // Both are phis. There is no ordering between phis (in terms of
       // the data-flow), so tie-break this via node id comparison.
       return A < B;
     }
   };
 
   std::vector<NodeId> Tmp(Owners.begin(), Owners.end());
-  llvm::sort(Tmp.begin(), Tmp.end(), Less);
+  llvm::sort(Tmp, Less);
 
   // The vector is a list of instructions, so that defs coming from
   // the same instruction don't need to be artificially ordered.
   // Then, when computing the initial segment, and iterating over an
   // instruction, pick the defs that contribute to the covering (i.e. is
   // not covered by previously added defs). Check the defs individually,
   // i.e. first check each def if is covered or not (without adding them
   // to the tracking set), and then add all the selected ones.
void Liveness::computeLiveIns() {
   LiveMap[&MF.front()].insert(DFG.getLiveIns());
 
   if (Trace) {
     // Dump the liveness map
     for (MachineBasicBlock &B : MF) {
       std::vector<RegisterRef> LV;
       for (auto I = B.livein_begin(), E = B.livein_end(); I != E; ++I)
         LV.push_back(RegisterRef(I->PhysReg, I->LaneMask));
-      llvm::sort(LV.begin(), LV.end());
+      llvm::sort(LV);
       dbgs() << printMBBReference(B) << "\t rec = {";
       for (auto I : LV)
         dbgs() << ' ' << Print<RegisterRef>(I, DFG);
       dbgs() << " }\n";
       //dbgs() << "\tcomp = " << Print<RegisterAggr>(LiveMap[&B], DFG) << '\n';
 
       LV.clear();
       const RegisterAggr &LG = LiveMap[&B];
       for (auto I = LG.rr_begin(), E = LG.rr_end(); I != E; ++I)
         LV.push_back(*I);
-      llvm::sort(LV.begin(), LV.end());
+      llvm::sort(LV);
       dbgs() << "\tcomp = {";
       for (auto I : LV)
         dbgs() << ' ' << Print<RegisterRef>(I, DFG);
       dbgs() << " }\n";
 
     }
   }
 }

lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp

void MipsELFObjectWriter::sortRelocs(const MCAssembler &Asm,
   // rather than it being split across a pair of relocations.
   if (hasRelocationAddend())
     return;
 
   if (Relocs.size() < 2)
     return;
 
   // Sort relocations by the address they are applied to.
-  llvm::sort(Relocs.begin(), Relocs.end(),
+  llvm::sort(Relocs,
              [](const ELFRelocationEntry &A, const ELFRelocationEntry &B) {
                return A.Offset < B.Offset;
              });
 
   std::list<MipsRelocationEntry> Sorted;
   std::list<ELFRelocationEntry> Remainder;
 
   LLVM_DEBUG(dumpRelocs("R: ", Relocs));

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

void collectValueRotInfo() {
     }
 
     // Now that we've collected the various ValueRotInfo instances, we need to
     // sort them.
     ValueRotsVec.clear();
     for (auto &I : ValueRots) {
       ValueRotsVec.push_back(I.second);
     }
-    llvm::sort(ValueRotsVec.begin(), ValueRotsVec.end());
+    llvm::sort(ValueRotsVec);
   }
 
   // In 64-bit mode, rlwinm and friends have a rotation operator that
   // replicates the low-order 32 bits into the high-order 32-bits. The mask
   // indices of these instructions can only be in the lower 32 bits, so they
   // can only represent some 64-bit bit groups. However, when they can be used,
   // the 32-bit replication can be used to represent, as a single bit group,
   // otherwise separate bit groups. We'll convert to replicated-32-bit bit

lib/Target/WebAssembly/WebAssemblyRegColoring.cpp

for (unsigned i = 0; i < NumVRegs; ++i) {
     SortedIntervals.push_back(LI);
   }
   LLVM_DEBUG(dbgs() << '\n');
 
   // Sort them to put arguments first (since we don't want to rename live-in
   // registers), by weight next, and then by position.
   // TODO: Investigate more intelligent sorting heuristics. For starters, we
   // should try to coalesce adjacent live intervals before non-adjacent ones.
-  llvm::sort(SortedIntervals.begin(), SortedIntervals.end(),
+  llvm::sort(SortedIntervals,
              [MRI](LiveInterval *LHS, LiveInterval *RHS) {
                if (MRI->isLiveIn(LHS->reg) != MRI->isLiveIn(RHS->reg))
                  return MRI->isLiveIn(LHS->reg);
                if (LHS->weight != RHS->weight)
                  return LHS->weight > RHS->weight;
                if (LHS->empty() || RHS->empty())
                  return !LHS->empty() && RHS->empty();
                return *LHS < *RHS;

lib/Target/X86/X86SpeculativeLoadHardening.cpp

if (!UncondSucc)
       continue;
 
     assert(SuccCounts[UncondSucc] == 1 &&
            "We should never have more than one edge to the unconditional "
            "successor at this point because every other edge must have been "
            "split above!");
 
     // Sort and unique the codes to minimize them.
-    llvm::sort(UncondCodeSeq.begin(), UncondCodeSeq.end());
+    llvm::sort(UncondCodeSeq);
     UncondCodeSeq.erase(std::unique(UncondCodeSeq.begin(), UncondCodeSeq.end()),
                         UncondCodeSeq.end());
 
     // Build a checking version of the successor.
     BuildCheckingBlockForSuccAndConds(MBB, *UncondSucc, /*SuccCount*/ 1,
                                       UncondBr, UncondBr, UncondCodeSeq);
   }
 

lib/Target/XCore/XCoreFrameLowering.cpp

SpillList.push_back(StackSlotInfo(XFI->getLRSpillSlot(),
                                       XCore::LR));
   }
   if (fetchFP) {
     int Offset = MFI.getObjectOffset(XFI->getFPSpillSlot());
     SpillList.push_back(StackSlotInfo(XFI->getFPSpillSlot(),
                                       Offset,
                                       FramePtr));
   }
-  llvm::sort(SpillList.begin(), SpillList.end(), CompareSSIOffset);
+  llvm::sort(SpillList, CompareSSIOffset);
 }
 
 /// Creates an ordered list of EH info register 'spills'.
 /// These slots are only used by the unwinder and calls to llvm.eh.return().
 /// Registers are ordered according to their frame offset.
 /// As offsets are negative, the largest offsets will be first.
 static void GetEHSpillList(SmallVectorImpl<StackSlotInfo> &SpillList,
                            MachineFrameInfo &MFI, XCoreFunctionInfo *XFI,
                            const Constant *PersonalityFn,
                            const TargetLowering *TL) {
   assert(XFI->hasEHSpillSlot() && "There are no EH register spill slots");
   const int *EHSlot = XFI->getEHSpillSlot();
   SpillList.push_back(
       StackSlotInfo(EHSlot[0], MFI.getObjectOffset(EHSlot[0]),
                     TL->getExceptionPointerRegister(PersonalityFn)));
   SpillList.push_back(
       StackSlotInfo(EHSlot[0], MFI.getObjectOffset(EHSlot[1]),
                     TL->getExceptionSelectorRegister(PersonalityFn)));
-  llvm::sort(SpillList.begin(), SpillList.end(), CompareSSIOffset);
+  llvm::sort(SpillList, CompareSSIOffset);
 }
 
 static MachineMemOperand *getFrameIndexMMO(MachineBasicBlock &MBB,
                                            int FrameIndex,
                                            MachineMemOperand::Flags flags) {
   MachineFunction *MF = MBB.getParent();
   const MachineFrameInfo &MFI = MF->getFrameInfo();
   MachineMemOperand *MMO = MF->getMachineMemOperand(

lib/Target/XCore/XCoreLowerThreadLocal.cpp

switch (OpCode) {
     default:
       llvm_unreachable("Unhandled constant expression!\n");
   }
 }
 
 static bool replaceConstantExprOp(ConstantExpr *CE, Pass *P) {
   do {
     SmallVector<WeakTrackingVH, 8> WUsers(CE->user_begin(), CE->user_end());
-    llvm::sort(WUsers.begin(), WUsers.end());
+    llvm::sort(WUsers);
     WUsers.erase(std::unique(WUsers.begin(), WUsers.end()), WUsers.end());
     while (!WUsers.empty())
       if (WeakTrackingVH WU = WUsers.pop_back_val()) {
         if (PHINode *PN = dyn_cast<PHINode>(WU)) {
           for (int I = 0, E = PN->getNumIncomingValues(); I < E; ++I)
             if (PN->getIncomingValue(I) == CE) {
               BasicBlock *PredBB = PN->getIncomingBlock(I);
               if (PredBB->getTerminator()->getNumSuccessors() > 1)

lib/Transforms/Coroutines/CoroFrame.cpp

class BlockToIndexMapping {
   SmallVector<BasicBlock *, SmallVectorThreshold> V;
 
 public:
   size_t size() const { return V.size(); }
 
   BlockToIndexMapping(Function &F) {
     for (BasicBlock &BB : F)
       V.push_back(&BB);
-    llvm::sort(V.begin(), V.end());
+    llvm::sort(V);
   }
 
   size_t blockToIndex(BasicBlock *BB) const {
     auto *I = std::lower_bound(V.begin(), V.end(), BB);
     assert(I != V.end() && *I == BB && "BasicBlockNumberng: Unknown block");
     return I - V.begin();
   }
 

lib/Transforms/IPO/LowerTypeTests.cpp

for (GlobalClassesTy::member_iterator MI = GlobalClasses.member_begin(I);
          MI != GlobalClasses.member_end(); ++MI) {
       if (auto *MD = MI->dyn_cast<Metadata *>())
         MaxUniqueId = std::max(MaxUniqueId, TypeIdInfo[MD].UniqueId);
       else if (auto *BF = MI->dyn_cast<ICallBranchFunnel *>())
         MaxUniqueId = std::max(MaxUniqueId, BF->UniqueId);
     }
     Sets.emplace_back(I, MaxUniqueId);
   }
-  llvm::sort(Sets.begin(), Sets.end(),
+  llvm::sort(Sets,
              [](const std::pair<GlobalClassesTy::iterator, unsigned> &S1,
                 const std::pair<GlobalClassesTy::iterator, unsigned> &S2) {
                return S1.second < S2.second;
              });
 
   // For each disjoint set we found...
   for (const auto &S : Sets) {
     // Build the list of type identifiers in this disjoint set.
     std::vector<Metadata *> TypeIds;
     std::vector<GlobalTypeMember *> Globals;
     std::vector<ICallBranchFunnel *> ICallBranchFunnels;
     for (GlobalClassesTy::member_iterator MI =
              GlobalClasses.member_begin(S.first);
          MI != GlobalClasses.member_end(); ++MI) {
       if (MI->is<Metadata *>())
         TypeIds.push_back(MI->get<Metadata *>());
       else if (MI->is<GlobalTypeMember *>())
         Globals.push_back(MI->get<GlobalTypeMember *>());
       else
         ICallBranchFunnels.push_back(MI->get<ICallBranchFunnel *>());
     }
 
     // Order type identifiers by unique ID for determinism. This ordering is
     // stable as there is a one-to-one mapping between metadata and unique IDs.
-    llvm::sort(TypeIds.begin(), TypeIds.end(), [&](Metadata *M1, Metadata *M2) {
+    llvm::sort(TypeIds, [&](Metadata *M1, Metadata *M2) {
       return TypeIdInfo[M1].UniqueId < TypeIdInfo[M2].UniqueId;
     });
 
     // Same for the branch funnels.
-    llvm::sort(ICallBranchFunnels.begin(), ICallBranchFunnels.end(),
+    llvm::sort(ICallBranchFunnels,
                [&](ICallBranchFunnel *F1, ICallBranchFunnel *F2) {
                  return F1->UniqueId < F2->UniqueId;
                });
 
     // Build bitsets for this disjoint set.
     buildBitSetsFromDisjointSet(TypeIds, Globals, ICallBranchFunnels);
   }
 

lib/Transforms/IPO/SampleProfile.cpp

SampleProfileLoader::findIndirectCallFunctionSamples(
   if (const FunctionSamplesMap *M = FS->findFunctionSamplesMapAt(LineLocation(
           FunctionSamples::getOffset(DIL), DIL->getBaseDiscriminator()))) {
     if (M->empty())
       return R;
     for (const auto &NameFS : *M) {
       Sum += NameFS.second.getEntrySamples();
       R.push_back(&NameFS.second);
     }
-    llvm::sort(R.begin(), R.end(),
+    llvm::sort(R,
                [](const FunctionSamples *L, const FunctionSamples *R) {
                  if (L->getEntrySamples() != R->getEntrySamples())
                    return L->getEntrySamples() > R->getEntrySamples();
                  return FunctionSamples::getGUID(L->getName()) <
                         FunctionSamples::getGUID(R->getName());
                });
   }
   return R;

 }
 
 /// Returns the sorted CallTargetMap \p M by count in descending order.
 static SmallVector<InstrProfValueData, 2> SortCallTargets(
     const SampleRecord::CallTargetMap &M) {
   SmallVector<InstrProfValueData, 2> R;
   for (auto I = M.begin(); I != M.end(); ++I)
     R.push_back({FunctionSamples::getGUID(I->getKey()), I->getValue()});
-  llvm::sort(R.begin(), R.end(),
+  llvm::sort(R,
              [](const InstrProfValueData &L, const InstrProfValueData &R) {
                if (L.Count == R.Count)
                  return L.Value > R.Value;
                else
                  return L.Count > R.Count;
              });
   return R;
 }

lib/Transforms/Scalar/GVNHoist.cpp

void computeInsertionPoints(const VNtoInsns &Map, HoistingPointList &HPL,
     std::vector<VNType> Ranks;
     for (const auto &Entry : Map) {
       Ranks.push_back(Entry.first);
     }
 
     // TODO: Remove fully-redundant expressions.
     // Get instruction from the Map, assume that all the Instructions
     // with same VNs have same rank (this is an approximation).
-    llvm::sort(Ranks.begin(), Ranks.end(),
+    llvm::sort(Ranks,
                [this, &Map](const VNType &r1, const VNType &r2) {
                  return (rank(*Map.lookup(r1).begin()) <
                          rank(*Map.lookup(r2).begin()));
                });
 
     // - Sort VNs according to their rank, and start with lowest ranked VN
     // - Take a VN and for each instruction with same VN
     //   - Find the dominance frontier in the inverse graph (PDF)

lib/Transforms/Scalar/GVNSink.cpp

 public:
   ModelledPHI() = default;
 
   ModelledPHI(const PHINode *PN) {
     // BasicBlock comes first so we sort by basic block pointer order, then by value pointer order.
     SmallVector<std::pair<BasicBlock *, Value *>, 4> Ops;
     for (unsigned I = 0, E = PN->getNumIncomingValues(); I != E; ++I)
       Ops.push_back({PN->getIncomingBlock(I), PN->getIncomingValue(I)});
-    llvm::sort(Ops.begin(), Ops.end());
+    llvm::sort(Ops);
     for (auto &P : Ops) {
       Blocks.push_back(P.first);
       Values.push_back(P.second);
     }
   }
 
   /// Create a dummy ModelledPHI that will compare unequal to any other ModelledPHI
   /// without the same ID.
InstructionUseExpr(Instruction *I, ArrayRecycler<Value *> &R,
                      BumpPtrAllocator &A)
       : GVNExpression::BasicExpression(I->getNumUses()) {
     allocateOperands(R, A);
     setOpcode(I->getOpcode());
     setType(I->getType());
 
     for (auto &U : I->uses())
       op_push_back(U.getUser());
-    llvm::sort(op_begin(), op_end());
+    llvm::sort(op);
   }
 
   void setMemoryUseOrder(unsigned MUO) { MemoryUseOrder = MUO; }
   void setVolatile(bool V) { Volatile = V; }
 
   hash_code getHashValue() const override {
     return hash_combine(GVNExpression::BasicExpression::getHashValue(),
                         MemoryUseOrder, Volatile);
for (auto *B : predecessors(BBEnd)) {
     auto *T = B->getTerminator();
     if (isa<BranchInst>(T) || isa<SwitchInst>(T))
       Preds.push_back(B);
     else
       return 0;
   }
   if (Preds.size() < 2)
     return 0;
-  llvm::sort(Preds.begin(), Preds.end());
+  llvm::sort(Preds);
 
   unsigned NumOrigPreds = Preds.size();
   // We can only sink instructions through unconditional branches.
   for (auto I = Preds.begin(); I != Preds.end();) {
     if ((*I)->getTerminator()->getNumSuccessors() != 1)
       I = Preds.erase(I);
     else
       ++I;

lib/Transforms/Scalar/GuardWidening.cpp

if (CurrentChecks.size() < 3) {
       RangeChecksOut.insert(RangeChecksOut.end(), CurrentChecks.begin(),
                             CurrentChecks.end());
       continue;
     }
 
     // CurrentChecks.size() will typically be 3 here, but so far there has been
     // no need to hard-code that fact.
 
-    llvm::sort(CurrentChecks.begin(), CurrentChecks.end(),
+    llvm::sort(CurrentChecks,
                [&](const GuardWideningImpl::RangeCheck &LHS,
                    const GuardWideningImpl::RangeCheck &RHS) {
       return LHS.getOffsetValue().slt(RHS.getOffsetValue());
     });
 
     // Note: std::sort should not invalidate the ChecksStart iterator.
 
     ConstantInt *MinOffset = CurrentChecks.front().getOffset(),

lib/Transforms/Scalar/LoopSink.cpp

if (BBsToSinkInto.empty())
     return false;
 
   // Copy the final BBs into a vector and sort them using the total ordering
   // of the loop block numbers as iterating the set doesn't give a useful
   // order. No need to stable sort as the block numbers are a total ordering.
   SmallVector<BasicBlock *, 2> SortedBBsToSinkInto;
   SortedBBsToSinkInto.insert(SortedBBsToSinkInto.begin(), BBsToSinkInto.begin(),
                              BBsToSinkInto.end());
-  llvm::sort(SortedBBsToSinkInto.begin(), SortedBBsToSinkInto.end(),
+  llvm::sort(SortedBBsToSinkInto,
              [&](BasicBlock *A, BasicBlock *B) {
                return LoopBlockNumber.find(A)->second <
                       LoopBlockNumber.find(B)->second;
              });
 
   BasicBlock *MoveBB = *SortedBBsToSinkInto.begin();
   // FIXME: Optimize the efficiency for cloned value replacement. The current
   //        implementation is O(SortedBBsToSinkInto.size() * I.num_uses()).

lib/Transforms/Scalar/LoopStrengthReduce.cpp

 #endif
 
 /// Test whether this use as a formula which has the same registers as the given
 /// formula.
 bool LSRUse::HasFormulaWithSameRegs(const Formula &F) const {
   SmallVector<const SCEV *, 4> Key = F.BaseRegs;
   if (F.ScaledReg) Key.push_back(F.ScaledReg);
   // Unstable sort by host order ok, because this is only used for uniquifying.
-  llvm::sort(Key.begin(), Key.end());
+  llvm::sort(Key);
   return Uniquifier.count(Key);
 }
 
 /// The function returns a probability of selecting formula without Reg.
 float LSRUse::getNotSelectedProbability(const SCEV *Reg) const {
   unsigned FNum = 0;
   for (const Formula &F : Formulae)
     if (F.referencesReg(Reg))
       FNum++;
   return ((float)(Formulae.size() - FNum)) / Formulae.size();
 }
 
 /// If the given formula has not yet been inserted, add it to the list, and
 /// return true. Return false otherwise.  The formula must be in canonical form.
 bool LSRUse::InsertFormula(const Formula &F, const Loop &L) {
   assert(F.isCanonical(L) && "Invalid canonical representation");
 
   if (!Formulae.empty() && RigidFormula)
     return false;
 
   SmallVector<const SCEV *, 4> Key = F.BaseRegs;
   if (F.ScaledReg) Key.push_back(F.ScaledReg);
   // Unstable sort by host order ok, because this is only used for uniquifying.
-  llvm::sort(Key.begin(), Key.end());
+  llvm::sort(Key);
 
   if (!Uniquifier.insert(Key).second)
     return false;
 
   // Using a register to hold the value of 0 is not profitable.
   assert((!F.ScaledReg || !F.ScaledReg->isZero()) &&
          "Zero allocated in a scaled register!");
 #ifndef NDEBUG
for (size_t FIdx = 0, NumForms = LU.Formulae.size();
           if (RegUses.isRegUsedByUsesOtherThan(Reg, LUIdx))
             Key.push_back(Reg);
         }
         if (F.ScaledReg &&
             RegUses.isRegUsedByUsesOtherThan(F.ScaledReg, LUIdx))
           Key.push_back(F.ScaledReg);
         // Unstable sort by host order ok, because this is only used for
         // uniquifying.
-        llvm::sort(Key.begin(), Key.end());
+        llvm::sort(Key);
 
         std::pair<BestFormulaeTy::const_iterator, bool> P =
           BestFormulae.insert(std::make_pair(Key, FIdx));
         if (P.second)
           continue;
 
         Formula &Best = LU.Formulae[P.first->second];
 

lib/Transforms/Scalar/MergeICmps.cpp

BCECmpChain::BCECmpChain(const std::vector<BasicBlock *> &Blocks, PHINode &Phi,
   EntryBlock_ = Comparisons[0].BB;
   Comparisons_ = std::move(Comparisons);
 #ifdef MERGEICMPS_DOT_ON
   errs() << "BEFORE REORDERING:\n\n";
   dump();
 #endif  // MERGEICMPS_DOT_ON
   // Reorder blocks by LHS. We can do that without changing the
   // semantics because we are only accessing dereferencable memory.
-  llvm::sort(Comparisons_.begin(), Comparisons_.end(),
+  llvm::sort(Comparisons_,
              [](const BCECmpBlock &a, const BCECmpBlock &b) {
                return a.Lhs() < b.Lhs();
              });
 #ifdef MERGEICMPS_DOT_ON
   errs() << "AFTER REORDERING:\n\n";
   dump();
 #endif  // MERGEICMPS_DOT_ON
 }

lib/Transforms/Scalar/NewGVN.cpp

static bool isCopyOfAPHI(const Value *V) {
   auto *CO = getCopyOf(V);
   return CO && isa<PHINode>(CO);
 }
 
 // Sort PHI Operands into a canonical order.  What we use here is an RPO
 // order. The BlockInstRange numbers are generated in an RPO walk of the basic
 // blocks.
 void NewGVN::sortPHIOps(MutableArrayRef<ValPair> Ops) const {
-  llvm::sort(Ops.begin(), Ops.end(),
+  llvm::sort(Ops,
              [&](const ValPair &P1, const ValPair &P2) {
     return BlockInstRange.lookup(P1.second).first <
            BlockInstRange.lookup(P2.second).first;
   });
 }
 
 // Return true if V is a value that will always be available (IE can
 // be placed anywhere) in the function.  We don't do globals here
if (alwaysAvailable(Leader)) {
         // the scope of those constants.
         ValueDFSStack EliminationStack;
 
         // Convert the members to DFS ordered sets and then merge them.
         SmallVector<ValueDFS, 8> DFSOrderedSet;
         convertClassToDFSOrdered(*CC, DFSOrderedSet, UseCounts, ProbablyDead);
 
         // Sort the whole thing.
-        llvm::sort(DFSOrderedSet.begin(), DFSOrderedSet.end());
+        llvm::sort(DFSOrderedSet);
         for (auto &VD : DFSOrderedSet) {
           int MemberDFSIn = VD.DFSIn;
           int MemberDFSOut = VD.DFSOut;
           Value *Def = VD.Def.getPointer();
           bool FromStore = VD.Def.getInt();
           Use *U = VD.U;
           // We ignore void things because we can't get a value from them.
           if (Def && Def->getType()->isVoidTy())
for (auto *Member : *CC)
       if (!isa<Instruction>(Member) ||
           !InstructionsToErase.count(cast<Instruction>(Member)))
         MembersLeft.insert(Member);
     CC->swap(MembersLeft);
 
     // If we have possible dead stores to look at, try to eliminate them.
     if (CC->getStoreCount() > 0) {
       convertClassToLoadsAndStores(*CC, PossibleDeadStores);
-      llvm::sort(PossibleDeadStores.begin(), PossibleDeadStores.end());
+      llvm::sort(PossibleDeadStores);
       ValueDFSStack EliminationStack;
       for (auto &VD : PossibleDeadStores) {
         int MemberDFSIn = VD.DFSIn;
         int MemberDFSOut = VD.DFSOut;
         Instruction *Member = cast<Instruction>(VD.Def.getPointer());
         if (EliminationStack.empty() ||
             !EliminationStack.isInScope(MemberDFSIn, MemberDFSOut)) {
           // Sync to our current scope.

lib/Transforms/Scalar/PlaceSafepoints.cpp

if (enableBackedgeSafepoints(F)) {
 
     auto &PollLocations = PBS->PollLocations;
 
     auto OrderByBBName = [](Instruction *a, Instruction *b) {
       return a->getParent()->getName() < b->getParent()->getName();
     };
     // We need the order of list to be stable so that naming ends up stable
     // when we split edges.  This makes test cases much easier to write.
-    llvm::sort(PollLocations.begin(), PollLocations.end(), OrderByBBName);
+    llvm::sort(PollLocations, OrderByBBName);
 
     // We can sometimes end up with duplicate poll locations.  This happens if
     // a single loop is visited more than once.   The fact this happens seems
     // wrong, but it does happen for the split-backedge.ll test case.
     PollLocations.erase(std::unique(PollLocations.begin(),
                                     PollLocations.end()),
                         PollLocations.end());
 

lib/Transforms/Scalar/RewriteStatepointsForGC.cpp

for (User *U : Def->users()) {
         // ConstantExpr use itself or null.  In either case
         // (recursively in the first, directly in the second), the oop
         // it is ultimately dependent on is null and this particular
         // use does not need to be fixed up.
         Uses.push_back(cast<Instruction>(U));
       }
     }
 
-    llvm::sort(Uses.begin(), Uses.end());
+    llvm::sort(Uses);
     auto Last = std::unique(Uses.begin(), Uses.end());
     Uses.erase(Last, Uses.end());
 
     for (Instruction *Use : Uses) {
       if (isa<PHINode>(Use)) {
         PHINode *Phi = cast<PHINode>(Use);
         for (unsigned i = 0; i < Phi->getNumIncomingValues(); i++) {
           if (Def == Phi->getIncomingValue(i)) {

lib/Transforms/Scalar/SROA.cpp

if (SROARandomShuffleSlices) {
     std::mt19937 MT(static_cast<unsigned>(
         std::chrono::system_clock::now().time_since_epoch().count()));
     std::shuffle(Slices.begin(), Slices.end(), MT);
   }
 #endif
 
   // Sort the uses. This arranges for the offsets to be in ascending order,
   // and the sizes to be in descending order.
-  llvm::sort(Slices.begin(), Slices.end());
+  llvm::sort(Slices);
 }
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 
 void AllocaSlices::print(raw_ostream &OS, const_iterator I,
                          StringRef Indent) const {
   printSlice(OS, I, Indent);
   OS << "\n";
auto RankVectorTypes = [&DL](VectorType *RHSTy, VectorType *LHSTy) {
       assert(DL.getTypeSizeInBits(RHSTy) == DL.getTypeSizeInBits(LHSTy) &&
              "Cannot have vector types of different sizes!");
       assert(RHSTy->getElementType()->isIntegerTy() &&
              "All non-integer types eliminated!");
       assert(LHSTy->getElementType()->isIntegerTy() &&
              "All non-integer types eliminated!");
       return RHSTy->getNumElements() < LHSTy->getNumElements();
     };
-    llvm::sort(CandidateTys.begin(), CandidateTys.end(), RankVectorTypes);
+    llvm::sort(CandidateTys, RankVectorTypes);
     CandidateTys.erase(
         std::unique(CandidateTys.begin(), CandidateTys.end(), RankVectorTypes),
         CandidateTys.end());
   } else {
 // The only way to have the same element type in every vector type is to
 // have the same vector type. Check that and remove all but one.
 #ifndef NDEBUG
     for (VectorType *VTy : CandidateTys) {
for (Slice &S : AS) {
           isa<StoreInst>(S.getUse()->getUser())) {
         S.makeUnsplittable();
         IsSorted = false;
       }
     }
   }
 
   if (!IsSorted)
-    llvm::sort(AS.begin(), AS.end());
+    llvm::sort(AS);
 
   /// Describes the allocas introduced by rewritePartition in order to migrate
   /// the debug info.
   struct Fragment {
     AllocaInst *Alloca;
     uint64_t Offset;
     uint64_t Size;
     Fragment(AllocaInst *AI, uint64_t O, uint64_t S)

lib/Transforms/Scalar/SimpleLoopUnswitch.cpp

for (auto *ClonedBB : ClonedLoopBlocks)
     if (!BlocksInClonedLoop.count(ClonedBB))
       UnloopedBlockSet.insert(ClonedBB);
 
   // Copy the cloned exits and sort them in ascending loop depth, we'll work
   // backwards across these to process them inside out. The order shouldn't
   // matter as we're just trying to build up the map from inside-out; we use
   // the map in a more stably ordered way below.
   auto OrderedClonedExitsInLoops = ClonedExitsInLoops;
-  llvm::sort(OrderedClonedExitsInLoops.begin(), OrderedClonedExitsInLoops.end(),
+  llvm::sort(OrderedClonedExitsInLoops,
              [&](BasicBlock *LHS, BasicBlock *RHS) {
                return ExitLoopMap.lookup(LHS)->getLoopDepth() <
                       ExitLoopMap.lookup(RHS)->getLoopDepth();
              });
 
   // Populate the existing ExitLoopMap with everything reachable from each
   // exit, starting from the inner most exit.
   while (!UnloopedBlockSet.empty() && !OrderedClonedExitsInLoops.empty()) {

lib/Transforms/Utils/ImportedFunctionsInliningStatistics.cpp

Ostream << "-- Summary:\n"
                  InlinedNotImportedFunctionsToImportingModuleCount,
                  NotImportedFuncCount, "non-imported functions");
   Ostream.flush();
   dbgs() << Out;
 }
 
 void ImportedFunctionsInliningStatistics::calculateRealInlines() {
   // Removing duplicated Callers.
-  llvm::sort(NonImportedCallers.begin(), NonImportedCallers.end());
+  llvm::sort(NonImportedCallers);
   NonImportedCallers.erase(
       std::unique(NonImportedCallers.begin(), NonImportedCallers.end()),
       NonImportedCallers.end());
 
   for (const auto &Name : NonImportedCallers) {
     auto &Node = *NodesMap[Name];
     if (!Node.Visited)
       dfs(Node);

lib/Transforms/Utils/LowerSwitch.cpp

 unsigned LowerSwitch::Clusterify(CaseVector& Cases, SwitchInst *SI) {
   unsigned numCmps = 0;
 
   // Start with "simple" cases
   for (auto Case : SI->cases())
     Cases.push_back(CaseRange(Case.getCaseValue(), Case.getCaseValue(),
                               Case.getCaseSuccessor()));
 
-  llvm::sort(Cases.begin(), Cases.end(), CaseCmp());
+  llvm::sort(Cases, CaseCmp());
 
   // Merge case into clusters
   if (Cases.size() >= 2) {
     CaseItr I = Cases.begin();
     for (CaseItr J = std::next(I), E = Cases.end(); J != E; ++J) {
       int64_t nextValue = J->Low->getSExtValue();
       int64_t currentValue = I->High->getSExtValue();
       BasicBlock* nextBB = J->BB;

lib/Transforms/Utils/PredicateInfo.cpp

 // TODO: Use this algorithm to perform fast single-variable renaming in
 // promotememtoreg and memoryssa.
 void PredicateInfo::renameUses(SmallPtrSetImpl<Value *> &OpSet) {
   // Sort OpsToRename since we are going to iterate it.
   SmallVector<Value *, 8> OpsToRename(OpSet.begin(), OpSet.end());
   auto Comparator = [&](const Value *A, const Value *B) {
     return valueComesBefore(OI, A, B);
   };
-  llvm::sort(OpsToRename.begin(), OpsToRename.end(), Comparator);
+  llvm::sort(OpsToRename, Comparator);
   ValueDFS_Compare Compare(OI);
   // Compute liveness, and rename in O(uses) per Op.
   for (auto *Op : OpsToRename) {
     LLVM_DEBUG(dbgs() << "Visiting " << *Op << "\n");
     unsigned Counter = 0;
     SmallVector<ValueDFS, 16> OrderedUses;
     const auto &ValueInfo = getValueInfo(Op);
     // Insert the possible copies into the def/use list.

lib/Transforms/Utils/PromoteMemoryToRegister.cpp

static bool promoteSingleBlockAlloca(AllocaInst *AI, const AllocaInfo &Info,
   StoresByIndexTy StoresByIndex;
 
   for (User *U : AI->users())
     if (StoreInst *SI = dyn_cast<StoreInst>(U))
       StoresByIndex.push_back(std::make_pair(LBI.getInstructionIndex(SI), SI));
 
   // Sort the stores by their index, making it efficient to do a lookup with a
   // binary search.
-  llvm::sort(StoresByIndex.begin(), StoresByIndex.end(), less_first());
+  llvm::sort(StoresByIndex, less_first());
 
   // Walk all of the loads from this alloca, replacing them with the nearest
   // store above them, if any.
   for (auto UI = AI->user_begin(), E = AI->user_end(); UI != E;) {
     LoadInst *LI = dyn_cast<LoadInst>(*UI++);
     if (!LI)
       continue;
 
for (unsigned AllocaNum = 0; AllocaNum != Allocas.size(); ++AllocaNum) {
     // the standard SSA construction algorithm.  Determine which blocks need phi
     // nodes and see if we can optimize out some work by avoiding insertion of
     // dead phi nodes.
     IDF.setLiveInBlocks(LiveInBlocks);
     IDF.setDefiningBlocks(DefBlocks);
     SmallVector<BasicBlock *, 32> PHIBlocks;
     IDF.calculate(PHIBlocks);
     if (PHIBlocks.size() > 1)
-      llvm::sort(PHIBlocks.begin(), PHIBlocks.end(),
+      llvm::sort(PHIBlocks,
                  [this](BasicBlock *A, BasicBlock *B) {
                    return BBNumbers.lookup(A) < BBNumbers.lookup(B);
                  });
 
     unsigned CurrentVersion = 0;
     for (BasicBlock *BB : PHIBlocks)
       QueuePhiNode(BB, AllocaNum, CurrentVersion);
   }
if (SomePHI->getNumIncomingValues() == getNumPreds(BB))
       continue;
 
     // Get the preds for BB.
     SmallVector<BasicBlock *, 16> Preds(pred_begin(BB), pred_end(BB));
 
     // Ok, now we know that all of the PHI nodes are missing entries for some
     // basic blocks.  Start by sorting the incoming predecessors for efficient
     // access.
-    llvm::sort(Preds.begin(), Preds.end());
+    llvm::sort(Preds);
 
     // Now we loop through all BB's which have entries in SomePHI and remove
     // them from the Preds list.
     for (unsigned i = 0, e = SomePHI->getNumIncomingValues(); i != e; ++i) {
       // Do a log(n) search of the Preds list for the entry we want.
       SmallVectorImpl<BasicBlock *>::iterator EntIt = std::lower_bound(
           Preds.begin(), Preds.end(), SomePHI->getIncomingBlock(i));
       assert(EntIt != Preds.end() && *EntIt == SomePHI->getIncomingBlock(i) &&

lib/Transforms/Utils/SimplifyCFG.cpp

static bool ReduceSwitchRange(SwitchInst *SI, IRBuilder<> &Builder,
 
   // This transform is agnostic to the signedness of the input or case values. We
   // can treat the case values as signed or unsigned. We can optimize more common
   // cases such as a sequence crossing zero {-4,0,4,8} if we interpret case values
   // as signed.
   SmallVector<int64_t,4> Values;
   for (auto &C : SI->cases())
     Values.push_back(C.getCaseValue()->getValue().getSExtValue());
-  llvm::sort(Values.begin(), Values.end());
+  llvm::sort(Values);
 
   // If the switch is already dense, there's nothing useful to do here.
   if (isSwitchDense(Values))
     return false;
 
   // First, transform the values such that they start at zero and ascend.
   int64_t Base = Values[0];
   for (auto &V : Values)

lib/Transforms/Utils/SplitModule.cpp

static void findPartitions(Module *M, ClusterIDMapType &ClusterIDMap,
   // When size is the same, use leader's name.
   for (ClusterMapType::iterator I = GVtoClusterMap.begin(),
                                 E = GVtoClusterMap.end(); I != E; ++I)
     if (I->isLeader())
       Sets.push_back(
           std::make_pair(std::distance(GVtoClusterMap.member_begin(I),
                                        GVtoClusterMap.member_end()), I));
 
-  llvm::sort(Sets.begin(), Sets.end(),
+  llvm::sort(Sets,
              [](const SortType &a, const SortType &b) {
                if (a.first == b.first)
                  return a.second->getData()->getName() >
                         b.second->getData()->getName();
                else
                  return a.first > b.first;
              });
 

tools/dsymutil/DwarfLinker.cpp

bool DwarfLinker::RelocationManager::findValidRelocs(
 
   if (ValidRelocs.empty())
     return false;
 
   // Sort the relocations by offset. We will walk the DIEs linearly in
   // the file, this allows us to just keep an index in the relocation
   // array that we advance during our walk, rather than resorting to
   // some associative container. See DwarfLinker::NextValidReloc.
-  llvm::sort(ValidRelocs.begin(), ValidRelocs.end());
+  llvm::sort(ValidRelocs);
   return true;
 }
 
 /// Look for relocations in the debug_info section that match
 /// entries in the debug map. These relocations will drive the Dwarf
 /// link by indicating which DIEs refer to symbols present in the
 /// linked binary.
 /// \returns whether there are any valid relocations in the debug info.

tools/dsymutil/DwarfStreamer.cpp

void DwarfStreamer::emitUnitRangesEntries(CompileUnit &Unit,
   const auto &FunctionRanges = Unit.getFunctionRanges();
   for (auto Range = FunctionRanges.begin(), End = FunctionRanges.end();
        Range != End; ++Range)
     Ranges.push_back(std::make_pair(Range.start() + Range.value(),
                                     Range.stop() + Range.value()));
 
   // The object addresses where sorted, but again, the linked
   // addresses might end up in a different order.
-  llvm::sort(Ranges.begin(), Ranges.end());
+  llvm::sort(Ranges);
 
   if (!Ranges.empty()) {
     MS->SwitchSection(MC->getObjectFileInfo()->getDwarfARangesSection());
 
     MCSymbol *BeginLabel = Asm->createTempSymbol("Barange");
     MCSymbol *EndLabel = Asm->createTempSymbol("Earange");
 
     unsigned HeaderSize =

tools/llvm-config/llvm-config.cpp

if (Arg.startswith("-")) {
             std::string path(
                 GetComponentLibraryPath(AvailableComponents[j].Library, false));
             if (DirSep == "\\") {
               std::replace(path.begin(), path.end(), '/', '\\');
             }
             if (DyLibExists && !sys::fs::exists(path)) {
               Components =
                   GetAllDyLibComponents(IsInDevelopmentTree, true, DirSep);
-              llvm::sort(Components.begin(), Components.end());
+              llvm::sort(Components);
               break;
             }
           }
         }
 
         for (unsigned I = 0; I < Components.size(); ++I) {
           if (I) {
             OS << ' ';

tools/llvm-dwarfdump/llvm-dwarfdump.cpp

static void filterByAccelName(ArrayRef<std::string> Names, DWARFContext &DICtx,
                               raw_ostream &OS) {
   SmallVector<DWARFDie, 4> Dies;
   for (const auto &Name : Names) {
     getDies(DICtx, DICtx.getAppleNames(), Name, Dies);
     getDies(DICtx, DICtx.getAppleTypes(), Name, Dies);
     getDies(DICtx, DICtx.getAppleNamespaces(), Name, Dies);
     getDies(DICtx, DICtx.getDebugNames(), Name, Dies);
   }
-  llvm::sort(Dies.begin(), Dies.end());
+  llvm::sort(Dies);
   Dies.erase(std::unique(Dies.begin(), Dies.end()), Dies.end());
 
   for (DWARFDie Die : Dies)
     Die.dump(OS, 0, getDumpOpts());
 }
 
 /// Handle the --lookup option and dump the DIEs and line info for the given
 /// address.

tools/llvm-exegesis/lib/Analysis.cpp

 //     Subunits = [(P2,p=0.875), (P1,p=0.875), (P5,p=0.875), (P5,p=0.875)]
 //     RemainingPressure = 0.0
 // We stop as there is no remaining budget to distribute.
 void distributePressure(float RemainingPressure,
                         llvm::SmallVector<uint16_t, 32> Subunits,
                         llvm::SmallVector<float, 32> &DensePressure) {
   // Find the number of subunits with minimal pressure (they are at the
   // front).
-  llvm::sort(Subunits.begin(), Subunits.end(),
-             [&DensePressure](const uint16_t A, const uint16_t B) {
-               return DensePressure[A] < DensePressure[B];
-             });
+  llvm::sort(Subunits, [&DensePressure](const uint16_t A, const uint16_t B) {
   const auto getPressureForSubunit = [&DensePressure,
                                       &Subunits](size_t I) -> float & {
     return DensePressure[Subunits[I]];
   };
   size_t NumMinimalSU = 1;
   while (NumMinimalSU < Subunits.size() &&
          getPressureForSubunit(NumMinimalSU) == getPressureForSubunit(0)) {
     ++NumMinimalSU;
void distributePressure(float RemainingPressure,
   }
 }
 
 std::vector<std::pair<uint16_t, float>> computeIdealizedProcResPressure(
     const llvm::MCSchedModel &SM,
     llvm::SmallVector<llvm::MCWriteProcResEntry, 8> WPRS) {
   // DensePressure[I] is the port pressure for Proc Resource I.
   llvm::SmallVector<float, 32> DensePressure(SM.getNumProcResourceKinds());
-  llvm::sort(WPRS.begin(), WPRS.end(),
+  llvm::sort(WPRS,
              [](const llvm::MCWriteProcResEntry &A,
                 const llvm::MCWriteProcResEntry &B) {
                return A.ProcResourceIdx < B.ProcResourceIdx;
              });
   for (const llvm::MCWriteProcResEntry &WPR : WPRS) {
     // Get units for the entry.
     const llvm::MCProcResourceDesc *const ProcResDesc =
         SM.getProcResource(WPR.ProcResourceIdx);

tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp

void RegisterFile::collectWrites(SmallVectorImpl<WriteRef> &Writes,
   // Handle potential partial register updates.
   for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) {
     const WriteRef &WR = RegisterMappings[*I].first;
     if (WR.isValid())
       Writes.push_back(WR);
   }
 
   // Remove duplicate entries and resize the input vector.
-  llvm::sort(Writes.begin(), Writes.end(),
+  llvm::sort(Writes,
              [](const WriteRef &Lhs, const WriteRef &Rhs) {
                return Lhs.getWriteState() < Rhs.getWriteState();
              });
   auto It = std::unique(Writes.begin(), Writes.end());
   Writes.resize(std::distance(Writes.begin(), It));
 
   LLVM_DEBUG({
     for (const WriteRef &WR : Writes) {

tools/llvm-mca/lib/InstrBuilder.cpp

for (unsigned I = 0, E = SCDesc.NumWriteProcResEntries; I < E; ++I) {
     if (PR.SuperIdx) {
       uint64_t Super = ProcResourceMasks[PR.SuperIdx];
       SuperResources[Super] += PRE->Cycles;
     }
   }
 
   // Sort elements by mask popcount, so that we prioritize resource units over
   // resource groups, and smaller groups over larger groups.
-  llvm::sort(Worklist.begin(), Worklist.end(),
+  llvm::sort(Worklist,
              [](const ResourcePlusCycles &A, const ResourcePlusCycles &B) {
                unsigned popcntA = countPopulation(A.first);
                unsigned popcntB = countPopulation(B.first);
                if (popcntA < popcntB)
                  return true;
                if (popcntA > popcntB)
                  return false;
                return A.first < B.first;

tools/llvm-nm/llvm-nm.cpp

if (NumericSort)
       Cmp = compareSymbolAddress;
     else if (SizeSort)
       Cmp = compareSymbolSize;
     else
       Cmp = compareSymbolName;
 
     if (ReverseSort)
       Cmp = [=](const NMSymbol &A, const NMSymbol &B) { return Cmp(B, A); };
-    llvm::sort(SymbolList.begin(), SymbolList.end(), Cmp);
+    llvm::sort(SymbolList, Cmp);
   }
 
   if (!PrintFileName) {
     if (OutputFormat == posix && MultipleFiles && printName) {
       outs() << '\n' << CurrentFilename << ":\n";
     } else if (OutputFormat == bsd && MultipleFiles && printName) {
       outs() << "\n" << CurrentFilename << ":\n";
     } else if (OutputFormat == sysv) {

tools/llvm-objdump/COFFDump.cpp

for (const SectionRef &Section : Obj->sections()) {
     if (Name != ".pdata")
       continue;
 
     const coff_section *Pdata = Obj->getCOFFSection(Section);
     for (const RelocationRef &Reloc : Section.relocations())
       Rels.push_back(Reloc);
 
     // Sort relocations by address.
-    llvm::sort(Rels.begin(), Rels.end(), RelocAddressLess);
+    llvm::sort(Rels, RelocAddressLess);
 
     ArrayRef<uint8_t> Contents;
     error(Obj->getSectionContents(Pdata, Contents));
     if (Contents.empty())
       continue;
 
     RFStart = reinterpret_cast<const RuntimeFunction *>(Contents.data());
     NumRFs = Contents.size() / sizeof(RuntimeFunction);

tools/llvm-objdump/MachODump.cpp

static void DisassembleMachO(StringRef Filename, MachOObjectFile *MachOOF,
   std::vector<SymbolRef> Symbols;
   SmallVector<uint64_t, 8> FoundFns;
   uint64_t BaseSegmentAddress;
 
   getSectionsAndSymbols(MachOOF, Sections, Symbols, FoundFns,
                         BaseSegmentAddress);
 
   // Sort the symbols by address, just in case they didn't come in that way.
-  llvm::sort(Symbols.begin(), Symbols.end(), SymbolSorter());
+  llvm::sort(Symbols, SymbolSorter());
 
   // Build a data in code table that is sorted on by the address of each entry.
   uint64_t BaseAddress = 0;
   if (Header.filetype == MachO::MH_OBJECT)
     BaseAddress = Sections[0].getAddress();
   else
     BaseAddress = BaseSegmentAddress;
   DiceTable Dices;

tools/llvm-objdump/llvm-objdump.cpp

if (isArmElf(Obj)) {
           TextMappingSymsAddr.push_back(Address - SectionAddr);
         if (Name.startswith("$a"))
           TextMappingSymsAddr.push_back(Address - SectionAddr);
         if (Name.startswith("$t"))
           TextMappingSymsAddr.push_back(Address - SectionAddr);
       }
     }
 
-    llvm::sort(DataMappingSymsAddr.begin(), DataMappingSymsAddr.end());
-    llvm::sort(TextMappingSymsAddr.begin(), TextMappingSymsAddr.end());
+    llvm::sort(DataMappingSymsAddr);
+    llvm::sort(TextMappingSymsAddr);
 
     if (Obj->isELF() && Obj->getArch() == Triple::amdgcn) {
       // AMDGPU disassembler uses symbolizer for printing labels
       std::unique_ptr<MCRelocationInfo> RelInfo(
         TheTarget->createMCRelocationInfo(TripleName, Ctx));
       if (RelInfo) {
         std::unique_ptr<MCSymbolizer> Symbolizer(
           TheTarget->createMCSymbolizer(
             TripleName, nullptr, nullptr, &Symbols, &Ctx, std::move(RelInfo)));
         DisAsm->setSymbolizer(std::move(Symbolizer));
       }
     }
 
     // Make a list of all the relocations for this section.
     std::vector<RelocationRef> Rels;
     if (InlineRelocs) {
       for (const SectionRef &RelocSec : SectionRelocMap[Section]) {
         for (const RelocationRef &Reloc : RelocSec.relocations()) {
           Rels.push_back(Reloc);
         }
       }
     }
 
     // Sort relocations by address.
-    llvm::sort(Rels.begin(), Rels.end(), RelocAddressLess);
+    llvm::sort(Rels, RelocAddressLess);
 
     StringRef SegmentName = "";
     if (const MachOObjectFile *MachO = dyn_cast<const MachOObjectFile>(Obj)) {
       DataRefImpl DR = Section.getRawDataRefImpl();
       SegmentName = MachO->getSectionFinalSegmentName(DR);
     }
     StringRef SectionName;
     error(Section.getName(SectionName));

tools/llvm-pdbutil/DumpOutputStyle.cpp

else {
           std::max_element(IS->name_ids().begin(), IS->name_ids().end());
       uint32_t Digits = NumDigits(*MaxID);
 
       P.formatLine("{0} | {1}", fmt_align("ID", AlignStyle::Right, Digits),
                    "String");
 
       std::vector<uint32_t> SortedIDs(IS->name_ids().begin(),
                                       IS->name_ids().end());
-      llvm::sort(SortedIDs.begin(), SortedIDs.end());
+      llvm::sort(SortedIDs);
       for (uint32_t I : SortedIDs) {
         auto ES = IS->getStringForID(I);
         llvm::SmallString<32> Str;
         if (!ES) {
           consumeError(ES.takeError());
           Str = "Error reading string";
         } else if (!ES->empty()) {
           Str.append("'");

tools/llvm-pdbutil/PrettyTypeDumper.cpp

if (Layout->immediatePadding() < opts::pretty::ImmediatePaddingThreshold) {
       ++Discarded;
       continue;
     }
 
     Filtered.push_back(std::move(Layout));
   }
 
   if (Comp)
-    llvm::sort(Filtered.begin(), Filtered.end(), Comp);
+    llvm::sort(Filtered, Comp);
   return Filtered;
 }
 
 TypeDumper::TypeDumper(LinePrinter &P) : PDBSymDumper(true), Printer(P) {}
 
 void TypeDumper::start(const PDBSymbolExe &Exe) {
   if (opts::pretty::Enums) {
     if (auto Enums = Exe.findAllChildren<PDBSymbolTypeEnum>()) {

tools/llvm-pdbutil/llvm-pdbutil.cpp

if (shouldDumpSymLevel(opts::pretty::SymLevel::Functions)) {
           while (auto Function = Functions->getNext()) {
             Printer.NewLine();
             Dumper.start(*Function, FunctionDumper::PointerType::None);
           }
         } else {
           std::vector<std::unique_ptr<PDBSymbolFunc>> Funcs;
           while (auto Func = Functions->getNext())
             Funcs.push_back(std::move(Func));
-          llvm::sort(Funcs.begin(), Funcs.end(),
+          llvm::sort(Funcs,
                      opts::pretty::compareFunctionSymbols);
           for (const auto &Func : Funcs) {
             Printer.NewLine();
             Dumper.start(*Func, FunctionDumper::PointerType::None);
           }
         }
       }
     }
     if (shouldDumpSymLevel(opts::pretty::SymLevel::Data)) {
       if (auto Vars = GlobalScope->findAllChildren<PDBSymbolData>()) {
         VariableDumper Dumper(Printer);
         if (opts::pretty::SymbolOrder == opts::pretty::SymbolSortMode::None) {
           while (auto Var = Vars->getNext())
             Dumper.start(*Var);
         } else {
           std::vector<std::unique_ptr<PDBSymbolData>> Datas;
           while (auto Var = Vars->getNext())
             Datas.push_back(std::move(Var));
-          llvm::sort(Datas.begin(), Datas.end(),
+          llvm::sort(Datas,
                      opts::pretty::compareDataSymbols);
           for (const auto &Var : Datas)
             Dumper.start(*Var);
         }
       }
     }
     if (shouldDumpSymLevel(opts::pretty::SymLevel::Thunks)) {
       if (auto Thunks = GlobalScope->findAllChildren<PDBSymbolThunk>()) {

tools/llvm-readobj/COFFDumper.cpp

void COFFDumper::cacheRelocations() {
 
   for (const SectionRef &S : Obj->sections()) {
     const coff_section *Section = Obj->getCOFFSection(S);
 
     for (const RelocationRef &Reloc : S.relocations())
       RelocMap[Section].push_back(Reloc);
 
     // Sort relocations by address.
-    llvm::sort(RelocMap[Section].begin(), RelocMap[Section].end(),
-               relocAddressLess);
+    llvm::sort(RelocMap[Section], relocAddressLess);
   }
 }
 
 void COFFDumper::printDataDirectory(uint32_t Index, const std::string &FieldName) {
   const data_directory *Data;
   if (Obj->getDataDirectory(Index, Data))
     return;
   W.printHex(FieldName + "RVA", Data->RelativeVirtualAddress);

tools/llvm-xray/xray-account.cpp

for (auto FT : FunctionLatencies) {
 
     Row.Function = FuncIdHelper.SymbolOrNumber(FuncId);
     Row.DebugInfo = FuncIdHelper.FileLineAndColumn(FuncId);
   }
 
   // Sort the data according to user-provided flags.
   switch (AccountSortOutput) {
   case SortField::FUNCID:
-    llvm::sort(Results.begin(), Results.end(),
+    llvm::sort(Results,
                [](const TupleType &L, const TupleType &R) {
                  if (AccountSortOrder == SortDirection::ASCENDING)
                    return std::get<0>(L) < std::get<0>(R);
                  if (AccountSortOrder == SortDirection::DESCENDING)
                    return std::get<0>(L) > std::get<0>(R);
                  llvm_unreachable("Unknown sort direction");
                });
     break;
   case SortField::COUNT:
-    llvm::sort(Results.begin(), Results.end(),
+    llvm::sort(Results,
                [](const TupleType &L, const TupleType &R) {
                  if (AccountSortOrder == SortDirection::ASCENDING)
                    return std::get<1>(L) < std::get<1>(R);
                  if (AccountSortOrder == SortDirection::DESCENDING)
                    return std::get<1>(L) > std::get<1>(R);
                  llvm_unreachable("Unknown sort direction");
                });
     break;
   default:
     // Here we need to look into the ResultRow for the rest of the data that
     // we want to sort by.
-    llvm::sort(Results.begin(), Results.end(),
+    llvm::sort(Results,
                [&](const TupleType &L, const TupleType &R) {
                  auto &LR = std::get<2>(L);
                  auto &RR = std::get<2>(R);
                  switch (AccountSortOutput) {
                  case SortField::COUNT:
                    if (AccountSortOrder == SortDirection::ASCENDING)
                      return LR.Count < RR.Count;
                    if (AccountSortOrder == SortDirection::DESCENDING)

tools/yaml2obj/yaml2macho.cpp

case MachO::LC_DYLD_INFO_ONLY:
       WriteQueue.push_back(std::make_pair(DyldInfoOnlyCmd->lazy_bind_off,
                                           &MachOWriter::writeLazyBindOpcodes));
       WriteQueue.push_back(std::make_pair(DyldInfoOnlyCmd->export_off,
                                           &MachOWriter::writeExportTrie));
       break;
     }
   }
 
-  llvm::sort(WriteQueue.begin(), WriteQueue.end(),
+  llvm::sort(WriteQueue,
              [](const writeOperation &a, const writeOperation &b) {
                return a.first < b.first;
              });
 
   for (auto writeOp : WriteQueue) {
     ZeroToOffset(OS, writeOp.first);
     if (auto Err = (this->*writeOp.second)(OS))
       return Err;

unittests/ADT/StringMapTest.cpp

 TEST_F(StringMapTest, IterMapKeys) {
   StringMap<int> Map;
   Map["A"] = 1;
   Map["B"] = 2;
   Map["C"] = 3;
   Map["D"] = 3;
 
   auto Keys = to_vector<4>(Map.keys());
-  llvm::sort(Keys.begin(), Keys.end());
+  llvm::sort(Keys);
 
   SmallVector<StringRef, 4> Expected = {"A", "B", "C", "D"};
   EXPECT_EQ(Expected, Keys);
 }
 
 TEST_F(StringMapTest, IterSetKeys) {
   StringSet<> Set;
   Set.insert("A");
   Set.insert("B");
   Set.insert("C");
   Set.insert("D");
 
   auto Keys = to_vector<4>(Set.keys());
-  llvm::sort(Keys.begin(), Keys.end());
+  llvm::sort(Keys);
 
   SmallVector<StringRef, 4> Expected = {"A", "B", "C", "D"};
   EXPECT_EQ(Expected, Keys);
 }
 
 // Create a non-default constructable value
 struct StringMapTestStruct {
   StringMapTestStruct(int i) : i(i) {}

unittests/Analysis/LazyCallGraphTest.cpp

TEST(LazyCallGraphTest, BasicGraphFormation) {
   EXPECT_EQ(CG.end(), I);
 
   // Build vectors and sort them for the rest of the assertions to make them
   // independent of order.
   std::vector<std::string> Nodes;
 
   for (LazyCallGraph::Edge &E : A1.populate())
     Nodes.push_back(E.getFunction().getName());
-  llvm::sort(Nodes.begin(), Nodes.end());
+  llvm::sort(Nodes);
   EXPECT_EQ("a2", Nodes[0]);
   EXPECT_EQ("b2", Nodes[1]);
   EXPECT_EQ("c3", Nodes[2]);
   Nodes.clear();
 
   A2.populate();
   EXPECT_EQ(A2->end(), std::next(A2->begin()));
   EXPECT_EQ("a3", A2->begin()->getFunction().getName());
   A3.populate();
   EXPECT_EQ(A3->end(), std::next(A3->begin()));
   EXPECT_EQ("a1", A3->begin()->getFunction().getName());
 
   for (LazyCallGraph::Edge &E : B1.populate())
     Nodes.push_back(E.getFunction().getName());
-  llvm::sort(Nodes.begin(), Nodes.end());
+  llvm::sort(Nodes);
   EXPECT_EQ("b2", Nodes[0]);
   EXPECT_EQ("d3", Nodes[1]);
   Nodes.clear();
 
   B2.populate();
   EXPECT_EQ(B2->end(), std::next(B2->begin()));
   EXPECT_EQ("b3", B2->begin()->getFunction().getName());
   B3.populate();
   EXPECT_EQ(B3->end(), std::next(B3->begin()));
   EXPECT_EQ("b1", B3->begin()->getFunction().getName());
 
   for (LazyCallGraph::Edge &E : C1.populate())
     Nodes.push_back(E.getFunction().getName());
-  llvm::sort(Nodes.begin(), Nodes.end());
+  llvm::sort(Nodes);
   EXPECT_EQ("c2", Nodes[0]);
   EXPECT_EQ("d2", Nodes[1]);
   Nodes.clear();
 
   C2.populate();
   EXPECT_EQ(C2->end(), std::next(C2->begin()));
   EXPECT_EQ("c3", C2->begin()->getFunction().getName());
   C3.populate();
TEST(LazyCallGraphTest, BasicGraphFormation) {
   // Now lets look at the RefSCCs and SCCs.
   CG.buildRefSCCs();
   auto J = CG.postorder_ref_scc_begin();
 
   LazyCallGraph::RefSCC &D = *J++;
   ASSERT_EQ(1, D.size());
   for (LazyCallGraph::Node &N : *D.begin())
     Nodes.push_back(N.getFunction().getName());
-  llvm::sort(Nodes.begin(), Nodes.end());
+  llvm::sort(Nodes);
   EXPECT_EQ(3u, Nodes.size());
   EXPECT_EQ("d1", Nodes[0]);
   EXPECT_EQ("d2", Nodes[1]);
   EXPECT_EQ("d3", Nodes[2]);
   Nodes.clear();
   EXPECT_FALSE(D.isParentOf(D));
   EXPECT_FALSE(D.isChildOf(D));
   EXPECT_FALSE(D.isAncestorOf(D));
   EXPECT_FALSE(D.isDescendantOf(D));
   EXPECT_EQ(&D, &*CG.postorder_ref_scc_begin());
 
   LazyCallGraph::RefSCC &C = *J++;
   ASSERT_EQ(1, C.size());
   for (LazyCallGraph::Node &N : *C.begin())
     Nodes.push_back(N.getFunction().getName());
-  llvm::sort(Nodes.begin(), Nodes.end());
+  llvm::sort(Nodes);
   EXPECT_EQ(3u, Nodes.size());
   EXPECT_EQ("c1", Nodes[0]);
   EXPECT_EQ("c2", Nodes[1]);
   EXPECT_EQ("c3", Nodes[2]);
   Nodes.clear();
   EXPECT_TRUE(C.isParentOf(D));
   EXPECT_FALSE(C.isChildOf(D));
   EXPECT_TRUE(C.isAncestorOf(D));
   EXPECT_FALSE(C.isDescendantOf(D));
   EXPECT_EQ(&C, &*std::next(CG.postorder_ref_scc_begin()));
 
   LazyCallGraph::RefSCC &B = *J++;
   ASSERT_EQ(1, B.size());
   for (LazyCallGraph::Node &N : *B.begin())
     Nodes.push_back(N.getFunction().getName());
-  llvm::sort(Nodes.begin(), Nodes.end());
+  llvm::sort(Nodes);
   EXPECT_EQ(3u, Nodes.size());
   EXPECT_EQ("b1", Nodes[0]);
   EXPECT_EQ("b2", Nodes[1]);
   EXPECT_EQ("b3", Nodes[2]);
   Nodes.clear();
   EXPECT_TRUE(B.isParentOf(D));
   EXPECT_FALSE(B.isChildOf(D));
   EXPECT_TRUE(B.isAncestorOf(D));
   EXPECT_FALSE(B.isDescendantOf(D));
   EXPECT_FALSE(B.isAncestorOf(C));
   EXPECT_FALSE(C.isAncestorOf(B));
   EXPECT_EQ(&B, &*std::next(CG.postorder_ref_scc_begin(), 2));
 
   LazyCallGraph::RefSCC &A = *J++;
   ASSERT_EQ(1, A.size());
   for (LazyCallGraph::Node &N : *A.begin())
     Nodes.push_back(N.getFunction().getName());
-  llvm::sort(Nodes.begin(), Nodes.end());
+  llvm::sort(Nodes);
   EXPECT_EQ(3u, Nodes.size());
   EXPECT_EQ("a1", Nodes[0]);
   EXPECT_EQ("a2", Nodes[1]);
   EXPECT_EQ("a3", Nodes[2]);
   Nodes.clear();
   EXPECT_TRUE(A.isParentOf(B));
   EXPECT_TRUE(A.isParentOf(C));
   EXPECT_FALSE(A.isParentOf(D));
TEST(LazyCallGraphTest, InnerSCCFormation) {
   LazyCallGraph::RefSCC &RC = *I++;
   EXPECT_EQ(CG.postorder_ref_scc_end(), I);
 
   // Now walk the four SCCs which should be in post-order.
   auto J = RC.begin();
   LazyCallGraph::SCC &D = *J++;
   for (LazyCallGraph::Node &N : D)
     Nodes.push_back(N.getFunction().getName());
-  llvm::sort(Nodes.begin(), Nodes.end());
+  llvm::sort(Nodes);
   EXPECT_EQ(3u, Nodes.size());
   EXPECT_EQ("d1", Nodes[0]);
   EXPECT_EQ("d2", Nodes[1]);
   EXPECT_EQ("d3", Nodes[2]);
   Nodes.clear();
 
   LazyCallGraph::SCC &B = *J++;
   for (LazyCallGraph::Node &N : B)
     Nodes.push_back(N.getFunction().getName());
-  llvm::sort(Nodes.begin(), Nodes.end());
+  llvm::sort(Nodes);
   EXPECT_EQ(3u, Nodes.size());
   EXPECT_EQ("b1", Nodes[0]);
   EXPECT_EQ("b2", Nodes[1]);
   EXPECT_EQ("b3", Nodes[2]);
   Nodes.clear();
 
   LazyCallGraph::SCC &C = *J++;
   for (LazyCallGraph::Node &N : C)
     Nodes.push_back(N.getFunction().getName());
-  llvm::sort(Nodes.begin(), Nodes.end());
+  llvm::sort(Nodes);
   EXPECT_EQ(3u, Nodes.size());
   EXPECT_EQ("c1", Nodes[0]);
   EXPECT_EQ("c2", Nodes[1]);
   EXPECT_EQ("c3", Nodes[2]);
   Nodes.clear();
 
   LazyCallGraph::SCC &A = *J++;
   for (LazyCallGraph::Node &N : A)
     Nodes.push_back(N.getFunction().getName());
-  llvm::sort(Nodes.begin(), Nodes.end());
+  llvm::sort(Nodes);
   EXPECT_EQ(3u, Nodes.size());
   EXPECT_EQ("a1", Nodes[0]);
   EXPECT_EQ("a2", Nodes[1]);
   EXPECT_EQ("a3", Nodes[2]);
   Nodes.clear();
 
   EXPECT_EQ(RC.end(), J);
 }

unittests/Analysis/MemorySSATest.cpp

TEST_F(MemorySSATest, TestOptimizedDefsAreProperUses) {
   ASSERT_EQ(Walker->getClobberingMemoryAccess(StoreA2), StoreAAccess);
   ASSERT_EQ(StoreA2Access->getOptimized(), StoreAAccess);
 
   auto *StoreBAccess = cast<MemoryDef>(MSSA.getMemoryAccess(StoreB));
   ASSERT_LT(StoreAAccess->getID(), StoreBAccess->getID());
   ASSERT_LT(StoreBAccess->getID(), StoreA2Access->getID());
 
   auto SortVecByID = [](std::vector<const MemoryDef *> &Defs) {
-    llvm::sort(Defs.begin(), Defs.end(),
+    llvm::sort(Defs,
                [](const MemoryDef *LHS, const MemoryDef *RHS) {
                  return LHS->getID() < RHS->getID();
                });
   };
 
   auto SortedUserList = [&](const MemoryDef *MD) {
     std::vector<const MemoryDef *> Result;
     transform(MD->users(), std::back_inserter(Result),

unittests/Support/Path.cpp

for (fs::directory_iterator i(Twine(TestDirectory) + "/symlink", ec), e;
     if (ec == std::make_error_code(std::errc::no_such_file_or_directory)) {
       VisitedBrokenSymlinks.push_back(path::filename(i->path()));
       continue;
     }
 
     ASSERT_NO_ERROR(ec);
     VisitedNonBrokenSymlinks.push_back(path::filename(i->path()));
   }
-  llvm::sort(VisitedNonBrokenSymlinks.begin(), VisitedNonBrokenSymlinks.end());
-  llvm::sort(VisitedBrokenSymlinks.begin(), VisitedBrokenSymlinks.end());
+  llvm::sort(VisitedNonBrokenSymlinks);
+  llvm::sort(VisitedBrokenSymlinks);
   v_t ExpectedNonBrokenSymlinks = {"b", "d"};
   ASSERT_EQ(ExpectedNonBrokenSymlinks.size(), VisitedNonBrokenSymlinks.size());
   ASSERT_TRUE(std::equal(VisitedNonBrokenSymlinks.begin(),
                          VisitedNonBrokenSymlinks.end(),
                          ExpectedNonBrokenSymlinks.begin()));
   VisitedNonBrokenSymlinks.clear();
 
   v_t ExpectedBrokenSymlinks = {"a", "c", "e"};
for (fs::recursive_directory_iterator i(
     if (ec == std::make_error_code(std::errc::no_such_file_or_directory)) {
       VisitedBrokenSymlinks.push_back(path::filename(i->path()));
       continue;
     }
 
     ASSERT_NO_ERROR(ec);
     VisitedNonBrokenSymlinks.push_back(path::filename(i->path()));
   }
-  llvm::sort(VisitedNonBrokenSymlinks.begin(), VisitedNonBrokenSymlinks.end());
-  llvm::sort(VisitedBrokenSymlinks.begin(), VisitedBrokenSymlinks.end());
+  llvm::sort(VisitedNonBrokenSymlinks);
+  llvm::sort(VisitedBrokenSymlinks);
   ExpectedNonBrokenSymlinks = {"b", "bb", "d", "da", "dd", "ddd", "ddd"};
   ASSERT_EQ(ExpectedNonBrokenSymlinks.size(), VisitedNonBrokenSymlinks.size());
   ASSERT_TRUE(std::equal(VisitedNonBrokenSymlinks.begin(),
                          VisitedNonBrokenSymlinks.end(),
                          ExpectedNonBrokenSymlinks.begin()));
   VisitedNonBrokenSymlinks.clear();
 
   ExpectedBrokenSymlinks = {"a", "ba", "bc", "c", "e"};
for (fs::recursive_directory_iterator i(
     if (ec == std::make_error_code(std::errc::no_such_file_or_directory)) {
       VisitedBrokenSymlinks.push_back(path::filename(i->path()));
       continue;
     }
 
     ASSERT_NO_ERROR(ec);
     VisitedNonBrokenSymlinks.push_back(path::filename(i->path()));
   }
-  llvm::sort(VisitedNonBrokenSymlinks.begin(), VisitedNonBrokenSymlinks.end());
-  llvm::sort(VisitedBrokenSymlinks.begin(), VisitedBrokenSymlinks.end());
+  llvm::sort(VisitedNonBrokenSymlinks);
+  llvm::sort(VisitedBrokenSymlinks);
   ExpectedNonBrokenSymlinks = {"a", "b", "ba", "bb", "bc", "c", "d", "da", "dd",
                                "ddd", "e"};
   ASSERT_EQ(ExpectedNonBrokenSymlinks.size(), VisitedNonBrokenSymlinks.size());
   ASSERT_TRUE(std::equal(VisitedNonBrokenSymlinks.begin(),
                          VisitedNonBrokenSymlinks.end(),
                          ExpectedNonBrokenSymlinks.begin()));
   VisitedNonBrokenSymlinks.clear();
 

utils/TableGen/CTagsEmitter.cpp

void CTagsEmitter::run(raw_ostream &OS) {
   std::vector<Tag> Tags;
   // Collect tags.
   Tags.reserve(Classes.size() + Defs.size());
   for (const auto &C : Classes)
     Tags.push_back(Tag(C.first, locate(C.second.get())));
   for (const auto &D : Defs)
     Tags.push_back(Tag(D.first, locate(D.second.get())));
   // Emit tags.
-  llvm::sort(Tags.begin(), Tags.end());
+  llvm::sort(Tags);
   OS << "!_TAG_FILE_FORMAT\t1\t/original ctags format/\n";
   OS << "!_TAG_FILE_SORTED\t1\t/0=unsorted, 1=sorted, 2=foldcase/\n";
   for (const Tag &T : Tags)
     T.emit(OS);
 }
 
 namespace llvm {
 
 void EmitCTags(RecordKeeper &RK, raw_ostream &OS) { CTagsEmitter(RK).run(OS); }
 
 } // End llvm namespace.

utils/TableGen/CodeGenDAGPatterns.cpp

 
 /// getPredicateCheck - Return a single string containing all of this
 /// pattern's predicates concatenated with "&&" operators.
 ///
 std::string PatternToMatch::getPredicateCheck() const {
   SmallVector<const Predicate*,4> PredList;
   for (const Predicate &P : Predicates)
     PredList.push_back(&P);
-  llvm::sort(PredList.begin(), PredList.end(), deref<llvm::less>());
+  llvm::sort(PredList, deref<llvm::less>());
 
   std::string Check;
   for (unsigned i = 0, e = PredList.size(); i != e; ++i) {
     if (i != 0)
       Check += " && ";
     Check += '(' + PredList[i]->getCondString() + ')';
   }
   return Check;
std::vector<Predicate> CodeGenDAGPatterns::makePredList(ListInit *L) {
   for (Init *I : L->getValues()) {
     if (DefInit *Pred = dyn_cast<DefInit>(I))
       Preds.push_back(Pred->getDef());
     else
       llvm_unreachable("Non-def on the list");
   }
 
   // Sort so that different orders get canonicalized to the same string.
-  llvm::sort(Preds.begin(), Preds.end());
+  llvm::sort(Preds);
   return Preds;
 }
 
 void CodeGenDAGPatterns::AddPatternToMatch(TreePattern *Pattern,
                                            PatternToMatch &&PTM) {
   // Do some sanity checking on the pattern we're about to match.
   std::string Reason;
   if (!PTM.getSrcPattern()->canPatternMatch(Reason, *this)) {

utils/TableGen/CodeGenRegisters.cpp

 
 } // end anonymous namespace
 
 //===----------------------------------------------------------------------===//
 //                            CodeGenRegisterClass
 //===----------------------------------------------------------------------===//
 
 static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) {
-  llvm::sort(M.begin(), M.end(), deref<llvm::less>());
+  llvm::sort(M, deref<llvm::less>());
   M.erase(std::unique(M.begin(), M.end(), deref<llvm::equal>()), M.end());
 }
 
 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
   : TheDef(R),
     Name(R->getName()),
     TopoSigs(RegBank.getNumTopoSigs()),
     EnumValue(-1) {
CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
   CodeGenRegisterClass *BiggestSuperRegRC = getSubClassWithSubReg(SubIdx);
   if (!BiggestSuperRegRC)
     return None;
   BitVector SuperRegRCsBV = BiggestSuperRegRC->getSubClasses();
   std::vector<CodeGenRegisterClass *> SuperRegRCs;
   for (auto &RC : RegClasses)
     if (SuperRegRCsBV[RC.EnumValue])
       SuperRegRCs.emplace_back(&RC);
-  llvm::sort(SuperRegRCs.begin(), SuperRegRCs.end(), SizeOrder);
+  llvm::sort(SuperRegRCs, SizeOrder);
   assert(SuperRegRCs.front() == BiggestSuperRegRC && "Biggest class wasn't first");
 
   // Find all the subreg classes and order them by size too.
   std::vector<std::pair<CodeGenRegisterClass *, BitVector>> SuperRegClasses;
   for (auto &RC: RegClasses) {
     BitVector SuperRegClassesBV(RegClasses.size());
     RC.getSuperRegClasses(SubIdx, SuperRegClassesBV);
     if (SuperRegClassesBV.any())
       SuperRegClasses.push_back(std::make_pair(&RC, SuperRegClassesBV));
   }
-  llvm::sort(SuperRegClasses.begin(), SuperRegClasses.end(),
+  llvm::sort(SuperRegClasses,
              [&](const std::pair<CodeGenRegisterClass *, BitVector> &A,
                  const std::pair<CodeGenRegisterClass *, BitVector> &B) {
                return SizeOrder(A.first, B.first);
              });
 
   // Find the biggest subclass and subreg class such that R:subidx is in the
   // subreg class for all R in subclass.
   //

 void CodeGenRegisterClass::buildRegUnitSet(const CodeGenRegBank &RegBank,
   std::vector<unsigned> &RegUnits) const {
   std::vector<unsigned> TmpUnits;
   for (RegUnitIterator UnitI(Members); UnitI.isValid(); ++UnitI) {
     const RegUnit &RU = RegBank.getRegUnit(*UnitI);
     if (!RU.Artificial)
       TmpUnits.push_back(*UnitI);
   }
-  llvm::sort(TmpUnits.begin(), TmpUnits.end());
+  llvm::sort(TmpUnits);
   std::unique_copy(TmpUnits.begin(), TmpUnits.end(),
                    std::back_inserter(RegUnits));
 }
 
 //===----------------------------------------------------------------------===//
 //                               CodeGenRegBank
 //===----------------------------------------------------------------------===//
 
 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
                                const CodeGenHwModes &Modes) : CGH(Modes) {
   // Configure register Sets to understand register classes and tuples.
   Sets.addFieldExpander("RegisterClass", "MemberList");
   Sets.addFieldExpander("CalleeSavedRegs", "SaveList");
   Sets.addExpander("RegisterTuples",
                    llvm::make_unique<TupleExpander>(SynthDefs));
 
   // Read in the user-defined (named) sub-register indices.
   // More indices will be synthesized later.
   std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
-  llvm::sort(SRIs.begin(), SRIs.end(), LessRecord());
+  llvm::sort(SRIs, LessRecord());
   for (unsigned i = 0, e = SRIs.size(); i != e; ++i)
     getSubRegIdx(SRIs[i]);
   // Build composite maps from ComposedOf fields.
   for (auto &Idx : SubRegIndices)
     Idx.updateComponents(*this);
 
   // Read in the register definitions.
   std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
-  llvm::sort(Regs.begin(), Regs.end(), LessRecordRegister());
+  llvm::sort(Regs, LessRecordRegister());
   // Assign the enumeration values.
   for (unsigned i = 0, e = Regs.size(); i != e; ++i)
     getReg(Regs[i]);
 
   // Expand tuples and number the new registers.
   std::vector<Record*> Tups =
     Records.getAllDerivedDefinitions("RegisterTuples");
 
   for (Record *R : Tups) {
     std::vector<Record *> TupRegs = *Sets.expand(R);
-    llvm::sort(TupRegs.begin(), TupRegs.end(), LessRecordRegister());
+    llvm::sort(TupRegs, LessRecordRegister());
     for (Record *RC : TupRegs)
       getReg(RC);
   }
 
   // Now all the registers are known. Build the object graph of explicit
   // register-register references.
   for (auto &Reg : Registers)
     Reg.buildObjectGraph(*this);

utils/TableGen/CodeGenSchedule.cpp

for (const Record *EC : Classes) {
 
         OI.addPredicateForProcModel(ProcMask, OperandMask, Pred);
       }
     }
   }
 
   // Sort OpcodeMappings elements based on their CPU and predicate masks.
   // As a last resort, order elements by opcode identifier.
-  llvm::sort(OpcodeMappings.begin(), OpcodeMappings.end(),
+  llvm::sort(OpcodeMappings,
              [&](const OpcodeMapPair &Lhs, const OpcodeMapPair &Rhs) {
                unsigned LhsIdx = Opcode2Index[Lhs.first];
                unsigned RhsIdx = Opcode2Index[Rhs.first];
                std::pair<APInt, APInt> &LhsMasks = OpcodeMasks[LhsIdx];
                std::pair<APInt, APInt> &RhsMasks = OpcodeMasks[RhsIdx];
 
                if (LhsMasks.first != RhsMasks.first) {
                  if (LhsMasks.first.countPopulation() <
void CodeGenSchedModels::collectOptionalProcessorInfo() {
   collectPfmCounters();
 
   checkCompleteness();
 }
 
 /// Gather all processor models.
 void CodeGenSchedModels::collectProcModels() {
   RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor");
-  llvm::sort(ProcRecords.begin(), ProcRecords.end(), LessRecordFieldName());
+  llvm::sort(ProcRecords, LessRecordFieldName());
 
   // Reserve space because we can. Reallocation would be ok.
   ProcModels.reserve(ProcRecords.size()+1);
 
   // Use idx=0 for NoModel/NoItineraries.
   Record *NoModelDef = Records.getDef("NoSchedModel");
   Record *NoItinsDef = Records.getDef("NoItineraries");
   ProcModels.emplace_back(0, "NoSchedModel", NoModelDef, NoItinsDef);
for (Record *RWDef : RWDefs) {
         assert(RWDef->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
         scanSchedRW(RWDef, SRDefs, RWSet);
       }
     }
   }
   // Find all ReadWrites referenced by SchedAlias. AliasDefs needs to be sorted
   // for the loop below that initializes Alias vectors.
   RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias");
-  llvm::sort(AliasDefs.begin(), AliasDefs.end(), LessRecord());
+  llvm::sort(AliasDefs, LessRecord());
   for (Record *ADef : AliasDefs) {
     Record *MatchDef = ADef->getValueAsDef("MatchRW");
     Record *AliasDef = ADef->getValueAsDef("AliasRW");
     if (MatchDef->isSubClassOf("SchedWrite")) {
       if (!AliasDef->isSubClassOf("SchedWrite"))
         PrintFatalError(ADef->getLoc(), "SchedWrite Alias must be SchedWrite");
       scanSchedRW(AliasDef, SWDefs, RWSet);
     }
     else {
       assert(MatchDef->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
       if (!AliasDef->isSubClassOf("SchedRead"))
         PrintFatalError(ADef->getLoc(), "SchedRead Alias must be SchedRead");
       scanSchedRW(AliasDef, SRDefs, RWSet);
     }
   }
   // Sort and add the SchedReadWrites directly referenced by instructions or
   // itinerary resources. Index reads and writes in separate domains.
-  llvm::sort(SWDefs.begin(), SWDefs.end(), LessRecord());
+  llvm::sort(SWDefs, LessRecord());
   for (Record *SWDef : SWDefs) {
     assert(!getSchedRWIdx(SWDef, /*IsRead=*/false) && "duplicate SchedWrite");
     SchedWrites.emplace_back(SchedWrites.size(), SWDef);
   }
-  llvm::sort(SRDefs.begin(), SRDefs.end(), LessRecord());
+  llvm::sort(SRDefs, LessRecord());
   for (Record *SRDef : SRDefs) {
     assert(!getSchedRWIdx(SRDef, /*IsRead-*/true) && "duplicate SchedWrite");
     SchedReads.emplace_back(SchedReads.size(), SRDef);
   }
   // Initialize WriteSequence vectors.
   for (CodeGenSchedRW &CGRW : SchedWrites) {
     if (!CGRW.IsSequence)
       continue;
if (!Inst->TheDef->isValueUnset("SchedRW"))
       findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
 
     // ProcIdx == 0 indicates the class applies to all processors.
     unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/{0});
     InstrClassMap[Inst->TheDef] = SCIdx;
   }
   // Create classes for InstRW defs.
   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
-  llvm::sort(InstRWDefs.begin(), InstRWDefs.end(), LessRecord());
+  llvm::sort(InstRWDefs, LessRecord());
   LLVM_DEBUG(dbgs() << "\n+++ SCHED CLASSES (createInstRWClass) +++\n");
   for (Record *RWDef : InstRWDefs)
     createInstRWClass(RWDef);
 
   NumInstrSchedClasses = SchedClasses.size();
 
   bool EnableDump = false;
   LLVM_DEBUG(EnableDump = true);
LLVM_DEBUG(
                    << '\n';
         });
   }
 }
 
 // Gather the read/write types for each itinerary class.
 void CodeGenSchedModels::collectProcItinRW() {
   RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");
-  llvm::sort(ItinRWDefs.begin(), ItinRWDefs.end(), LessRecord());
+  llvm::sort(ItinRWDefs, LessRecord());
   for (Record *RWDef  : ItinRWDefs) {
     if (!RWDef->getValueInit("SchedModel")->isComplete())
       PrintFatalError(RWDef->getLoc(), "SchedModel is undefined");
     Record *ModelDef = RWDef->getValueAsDef("SchedModel");
     ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
     if (I == ProcModelMap.end()) {
       PrintFatalError(RWDef->getLoc(), "Undefined SchedMachineModel "
                     + ModelDef->getName());

utils/TableGen/CodeGenTarget.cpp

 CodeGenRegBank &CodeGenTarget::getRegBank() const {
   if (!RegBank)
     RegBank = llvm::make_unique<CodeGenRegBank>(Records, getHwModes());
   return *RegBank;
 }
 
 void CodeGenTarget::ReadRegAltNameIndices() const {
   RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
-  llvm::sort(RegAltNameIndices.begin(), RegAltNameIndices.end(), LessRecord());
+  llvm::sort(RegAltNameIndices, LessRecord());
 }
 
 /// getRegisterByName - If there is a register with the specific AsmName,
 /// return it.
 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
   const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
   StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
   if (I == Regs.end())
     return nullptr;
   return I->second;
 }
 
 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
       const {
   const CodeGenRegister *Reg = getRegBank().getReg(R);
   std::vector<ValueTypeByHwMode> Result;
   for (const auto &RC : getRegBank().getRegClasses()) {
     if (RC.contains(Reg)) {
       ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes();
       Result.insert(Result.end(), InVTs.begin(), InVTs.end());
     }
   }
 
   // Remove duplicates.
-  llvm::sort(Result.begin(), Result.end());
+  llvm::sort(Result);
   Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
   return Result;
 }
 
 
 void CodeGenTarget::ReadLegalValueTypes() const {
   for (const auto &RC : getRegBank().getRegClasses())
     LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end());
 
   // Remove duplicates.
-  llvm::sort(LegalValueTypes.begin(), LegalValueTypes.end());
+  llvm::sort(LegalValueTypes);
   LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
                                     LegalValueTypes.end()),
                         LegalValueTypes.end());
 }
 
 CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
   if (!SchedModels)
     SchedModels = llvm::make_unique<CodeGenSchedModels>(Records, *this);
CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC,
 
   Intrinsics.reserve(Defs.size());
 
   for (unsigned I = 0, e = Defs.size(); I != e; ++I) {
     bool isTarget = Defs[I]->getValueAsBit("isTarget");
     if (isTarget == TargetOnly)
       Intrinsics.push_back(CodeGenIntrinsic(Defs[I]));
   }
-  llvm::sort(Intrinsics.begin(), Intrinsics.end(),
+  llvm::sort(Intrinsics,
              [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) {
                return std::tie(LHS.TargetPrefix, LHS.Name) <
                       std::tie(RHS.TargetPrefix, RHS.Name);
              });
   Targets.push_back({"", 0, 0});
   for (size_t I = 0, E = Intrinsics.size(); I < E; ++I)
     if (Intrinsics[I].TargetPrefix != Targets.back().Name) {
       Targets.back().Count = I - Targets.back().Offset;
for (unsigned i = 0, e = PropList->size(); i != e; ++i) {
     } else
       llvm_unreachable("Unknown property!");
   }
 
   // Also record the SDPatternOperator Properties.
   Properties = parseSDPatternOperatorProperties(R);
 
   // Sort the argument attributes for later benefit.
-  llvm::sort(ArgumentAttributes.begin(), ArgumentAttributes.end());
+  llvm::sort(ArgumentAttributes);
 }
 

utils/TableGen/GlobalISelEmitter.cpp

if (I->mayLoad || I->mayStore) {
       //       some other means of having a memoperand. Also limit this to
       //       emitted instructions that expect to have a memoperand too. For
       //       example, (G_SEXT (G_LOAD x)) that results in separate load and
       //       sign-extend instructions shouldn't put the memoperand on the
       //       sign-extend since it has no effect there.
       std::vector<unsigned> MergeInsnIDs;
       for (const auto &IDMatcherPair : Rule.defined_insn_vars())
         MergeInsnIDs.push_back(IDMatcherPair.second);
-      llvm::sort(MergeInsnIDs.begin(), MergeInsnIDs.end());
+      llvm::sort(MergeInsnIDs);
       for (const auto &MergeInsnID : MergeInsnIDs)
         Table << MatchTable::IntValue(MergeInsnID);
       Table << MatchTable::NamedValue("GIU_MergeMemOperands_EndOfList")
             << MatchTable::LineBreak;
     }
 
     // FIXME: This is a hack but it's sufficient for ISel. We'll need to do
     //        better for combines. Particularly when there are multiple match
if (InsnVariableIDs.size() >= 2) {
     for (const auto &Pair : InsnVariableIDs) {
       // Skip the root node since it isn't moving anywhere. Everything else is
       // sinking to meet it.
       if (Pair.first == Matchers.front().get())
         continue;
 
       InsnIDs.push_back(Pair.second);
     }
-    llvm::sort(InsnIDs.begin(), InsnIDs.end());
+    llvm::sort(InsnIDs);
 
     for (const auto &InsnID : InsnIDs) {
       // Reject the difficult cases until we have a more accurate check.
       Table << MatchTable::Opcode("GIM_CheckIsSafeToFold")
             << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID)
             << MatchTable::LineBreak;
 
       // FIXME: Emit checks to determine it's _actually_ safe to fold and/or
void GlobalISelEmitter::run(raw_ostream &OS) {
 
   // Comparison function to order records by name.
   auto orderByName = [](const Record *A, const Record *B) {
     return A->getName() < B->getName();
   };
 
   std::vector<Record *> ComplexPredicates =
       RK.getAllDerivedDefinitions("GIComplexOperandMatcher");
-  llvm::sort(ComplexPredicates.begin(), ComplexPredicates.end(), orderByName);
+  llvm::sort(ComplexPredicates, orderByName);
 
   std::vector<Record *> CustomRendererFns =
       RK.getAllDerivedDefinitions("GICustomOperandRenderer");
-  llvm::sort(CustomRendererFns.begin(), CustomRendererFns.end(), orderByName);
+  llvm::sort(CustomRendererFns, orderByName);
 
   unsigned MaxTemporaries = 0;
   for (const auto &Rule : Rules)
     MaxTemporaries = std::max(MaxTemporaries, Rule.countRendererFns());
 
   OS << "#ifdef GET_GLOBALISEL_PREDICATE_BITSET\n"
      << "const unsigned MAX_SUBTARGET_PREDICATES = " << SubtargetFeatures.size()
      << ";\n"
SubtargetFeatureInfo::emitComputeAvailableFeatures(
       "computeAvailableFunctionFeatures", FunctionFeatures, OS,
       "const MachineFunction *MF");
 
   // Emit a table containing the LLT objects needed by the matcher and an enum
   // for the matcher to reference them with.
   std::vector<LLTCodeGen> TypeObjects;
   for (const auto &Ty : KnownTypes)
     TypeObjects.push_back(Ty);
-  llvm::sort(TypeObjects.begin(), TypeObjects.end());
+  llvm::sort(TypeObjects);
   OS << "// LLT Objects.\n"
      << "enum {\n";
   for (const auto &TypeObject : TypeObjects) {
     OS << "  ";
     TypeObject.emitCxxEnumValue(OS);
     OS << ",\n";
   }
   OS << "};\n";

utils/TableGen/InfoByHwMode.cpp

void ValueTypeByHwMode::writeToStream(raw_ostream &OS) const {
   if (isSimple()) {
     OS << getMVTName(getSimple());
     return;
   }
 
   std::vector<const PairType*> Pairs;
   for (const auto &P : Map)
     Pairs.push_back(&P);
-  llvm::sort(Pairs.begin(), Pairs.end(), deref<std::less<PairType>>());
+  llvm::sort(Pairs, deref<std::less<PairType>>());
 
   OS << '{';
   for (unsigned i = 0, e = Pairs.size(); i != e; ++i) {
     const PairType *P = Pairs[i];
     OS << '(' << getModeName(P->first)
        << ':' << getMVTName(P->second).str() << ')';
     if (i != e-1)
       OS << ',';
return std::tie(A0.SpillSize, A0.SpillAlignment) >
          std::tie(B0.SpillSize, B0.SpillAlignment);
 }
 
 void RegSizeInfoByHwMode::writeToStream(raw_ostream &OS) const {
   typedef typename decltype(Map)::value_type PairType;
   std::vector<const PairType*> Pairs;
   for (const auto &P : Map)
     Pairs.push_back(&P);
-  llvm::sort(Pairs.begin(), Pairs.end(), deref<std::less<PairType>>());
+  llvm::sort(Pairs, deref<std::less<PairType>>());
 
   OS << '{';
   for (unsigned i = 0, e = Pairs.size(); i != e; ++i) {
     const PairType *P = Pairs[i];
     OS << '(' << getModeName(P->first) << ':' << P->second << ')';
     if (i != e-1)
       OS << ',';
   }

utils/TableGen/SubtargetEmitter.cpp

 
 //
 // Enumeration - Emit the specified class as an enumeration.
 //
 void SubtargetEmitter::Enumeration(raw_ostream &OS) {
   // Get all records of class and sort
   std::vector<Record*> DefList =
     Records.getAllDerivedDefinitions("SubtargetFeature");
-  llvm::sort(DefList.begin(), DefList.end(), LessRecord());
+  llvm::sort(DefList, LessRecord());
 
   unsigned N = DefList.size();
   if (N == 0)
     return;
   if (N > MAX_SUBTARGET_FEATURES)
     PrintFatalError("Too many subtarget features! Bump MAX_SUBTARGET_FEATURES.");
 
   OS << "namespace " << Target << " {\n";

 unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
   // Gather and sort all the features
   std::vector<Record*> FeatureList =
                            Records.getAllDerivedDefinitions("SubtargetFeature");
 
   if (FeatureList.empty())
     return 0;
 
-  llvm::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName());
+  llvm::sort(FeatureList, LessRecordFieldName());
 
   // Begin feature table
   OS << "// Sorted (by key) array of values for CPU features.\n"
      << "extern const llvm::SubtargetFeatureKV " << Target
      << "FeatureKV[] = {\n";
 
   // For each feature
   unsigned NumFeatures = 0;

 //
 // CPUKeyValues - Emit data of all the subtarget processors.  Used by command
 // line.
 //
 unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) {
   // Gather and sort processor information
   std::vector<Record*> ProcessorList =
                           Records.getAllDerivedDefinitions("Processor");
-  llvm::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
+  llvm::sort(ProcessorList, LessRecordFieldName());
 
   // Begin processor table
   OS << "// Sorted (by key) array of values for CPU subtype.\n"
      << "extern const llvm::SubtargetFeatureKV " << Target
      << "SubTypeKV[] = {\n";
 
   // For each processor
   for (Record *Processor : ProcessorList) {
for (unsigned UseIdx = 0, EndIdx = Reads.size();
       IdxVec WriteIDs;
       if (ValidWrites.empty())
         WriteIDs.push_back(0);
       else {
         for (Record *VW : ValidWrites) {
           WriteIDs.push_back(SchedModels.getSchedRWIdx(VW, /*IsRead=*/false));
         }
       }
-      llvm::sort(WriteIDs.begin(), WriteIDs.end());
+      llvm::sort(WriteIDs);
       for(unsigned W : WriteIDs) {
         MCReadAdvanceEntry RAEntry;
         RAEntry.UseIdx = UseIdx;
         RAEntry.WriteResourceID = W;
         RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles");
         ReadAdvanceEntries.push_back(RAEntry);
       }
     }
     if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
       WriteProcResources.clear();
       WriteLatencies.clear();
       ReadAdvanceEntries.clear();
     }
     // Add the information for this SchedClass to the global tables using basic
     // compression.
     //
     // WritePrecRes entries are sorted by ProcResIdx.
-    llvm::sort(WriteProcResources.begin(), WriteProcResources.end(),
+    llvm::sort(WriteProcResources,
                LessWriteProcResources());
 
     SCDesc.NumWriteProcResEntries = WriteProcResources.size();
     std::vector<MCWriteProcResEntry>::iterator WPRPos =
       std::search(SchedTables.WriteProcResources.begin(),
                   SchedTables.WriteProcResources.end(),
                   WriteProcResources.begin(), WriteProcResources.end());
     if (WPRPos != SchedTables.WriteProcResources.end())

 
 //
 // EmitProcessorLookup - generate cpu name to itinerary lookup table.
 //
 void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
   // Gather and sort processor information
   std::vector<Record*> ProcessorList =
                           Records.getAllDerivedDefinitions("Processor");
-  llvm::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
+  llvm::sort(ProcessorList, LessRecordFieldName());
 
   // Begin processor table
   OS << "\n";
   OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
      << "extern const llvm::SubtargetInfoKV "
      << Target << "ProcSchedKV[] = {\n";
 
   // For each processor

 static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) {
   std::string Buffer;
   raw_string_ostream Stream(Buffer);
 
   // Collect all the PredicateProlog records and print them to the output
   // stream.
   std::vector<Record *> Prologs =
       Records.getAllDerivedDefinitions("PredicateProlog");
-  llvm::sort(Prologs.begin(), Prologs.end(), LessRecord());
+  llvm::sort(Prologs, LessRecord());
   for (Record *P : Prologs)
     Stream << P->getValueAsString("Code") << '\n';
 
   Stream.flush();
   OS << Buffer;
 }
 
 static void emitPredicates(const CodeGenSchedTransition &T,

 // ParseFeaturesFunction - Produces a subtarget specific function for parsing
 // the subtarget features string.
 //
 void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
                                              unsigned NumFeatures,
                                              unsigned NumProcs) {
   std::vector<Record*> Features =
                        Records.getAllDerivedDefinitions("SubtargetFeature");
-  llvm::sort(Features.begin(), Features.end(), LessRecord());
+  llvm::sort(Features, LessRecord());
 
   OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
      << "// subtarget options.\n"
      << "void llvm::";
   OS << Target;
   OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n"
      << "  LLVM_DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
      << "  LLVM_DEBUG(dbgs() << \"\\nCPU:\" << CPU << \"\\n\\n\");\n";