[AArch64] Add Tiny Code Model for AArch64

[dmgreen]

Summary

This adds the plumbing for the Tiny code model for the AArch64 backend. This, instead of loading addresses through the normal ADRP;ADD pair used in the Small model, uses a single ADR. The 21 bit range of an ADR means that the code and its statically defined symbols need to be within 1MB of each other.

This makes it mostly interesting for embedded applications where we want to fit as much as we can in as small a space as possible.

[efriedma]

This seems mostly straightforward.

Is tiny supported with PIC? Please add tests.

Do other in-tree targets correctly reject -code-model=tiny?

lib/Target/AArch64/AArch64Subtarget.h

315 ↗

(On Diff #156782)

Please don't use an default parameter like this; just use two separate helpers instead.

[peter.smith]

I think that it is important to support position independent code in the tiny code model, there was a thread on llvm-dev in May where someone couldn't 4k align his position independent code on a bare-metal AArch64 platform (http://lists.llvm.org/pipermail/llvm-dev/2018-May/123465.html) A tiny code model that avoids ADRP could be a solution there. A PR was raised to implement it https://bugs.llvm.org/show_bug.cgi?id=37543 . If we can get position independent support added then it will be worth closing that PR. I guess it could be added in a follow up patch though.

Some other observations:

• It will be worth adding assembler support for adr with respect to a relocated literal, I don't think it does right now. Certainly worth adding a test.
• I seem to remember in the thread that supporting tiny in machO might be difficult due to lack of available relocations. May be worth making sure that selecting tiny code model on MachO is an error and then you can avoid testing for non-MachO in multiple places.
• TLS could also be altered in the tiny code model. AFAIK GNU ld supports relaxation of at least some of the tiny code model TLS implementations. The GCC version I had only seemed to alter its initial-exec implementation though. Again I think TLS support could be added in a follow up patch.

lib/Target/AArch64/AArch64ISelLowering.cpp

3942 ↗

(On Diff #156782)

Typo: GOT relocations instead of git?

[dmgreen]

Thanks guys

In D49673#1172208, @efriedma wrote:

This seems mostly straightforward.

Is tiny supported with PIC? Please add tests.

Do other in-tree targets correctly reject -code-model=tiny?

Will do

In D49673#1173557, @peter.smith wrote:

Some other observations:

Cheers for the comments (and the code). I forgot to mention the things that this doesn't yet handle. TLS is the main one. This will currently assert for TLS for ELF, in the same way as for the Large codemodel, and if that is removed/ignored will create code as with the Small implementation. I plan to look into this, but as you say that might be better in a followup.

I have some code for fastisel but removed it as I wasn't sure it was worth-while. That will fall back to ISel at the moment.

I think I mentioned somewhere in the code that as weak references need to go through a GOT (so they can be 0), and from what I can tell there are no GOT relocations on ADR's, the code here currently produces an ADRP;ADD pair with the relocations. GCC produces a constant pool access or LDR's in PIC, so this may change.

I'll see about adding PIC, filling in the gaps and run some extra testing.

[dmgreen]

Now with more code. I will go through later and try to pull sensible parts of this out into separate patches. The llvm-test-suite all either pass or fail to link both with and without -fPIC (although more fail to link without PIC that I would have expected).

TLS still uses the same implementation as Small at the moment. This, as far as I can tell, is the same thing that gcc does.

Thanks to Peter for some pointers.

[peter.smith]

One example where gcc (7.1 in my case) will generate different code for tls is:

__thread int foo __attribute__((tls_model("initial-exec")));

int func(void) {
    return foo;
}

aarch64-linux-gnu-gcc -S tls.c -O1 -mcmodel=small -o -

func:
	adrp	x0, :gottprel:.LANCHOR0
	ldr	x0, [x0, #:gottprel_lo12:.LANCHOR0]
	mrs	x1, tpidr_el0
	ldr	w0, [x1, x0]
	ret
...
	.section	.tbss,"awT",@nobits
	.align	2
	.set	.LANCHOR0,. + 0
	.type	foo, %object
	.size	foo, 4
foo:
	.zero	4

whereas with -mcmodel=tiny

func:
	mrs	x1, tpidr_el0
	ldr	x0, :gottprel:.LANCHOR0
	add	x0, x0, x1
	ldr	w0, [x0]
	ret

I've not seen any differences in the other TLS models.

I think it is probably fine to keep TLS access using the small code model, at least initially. I wouldn't expect too many embedded systems to implement TLS and if they did they could probably use the local-exec model at compile time or have the linker relax to local-exec. Haven't had a chance to look at the rest of the patch yet, will hope to do so shortly.

[dmgreen]

Thanks Peter.

I've split out a couple of obvious parts into separate commits. Let me know if anything else looks like it deserves the same treatment.

[dmgreen]

Ping

[peter.smith]

Generally looking good to me. Apologies for the delay.

As a general nit, the patch has been a bit inconsistent about preserving/removing curly braces after if/else statements with only a single statement in the body. It may be better to either preserve all as they are or change all of them; not a critical comment by any means.

It would be good to add a test in MC for a relocated ADR instruction with the :got: modifier. It would also be good to add a test to check what happens when someone attempts to use TLS with the tiny code model.

lib/Target/AArch64/AArch64ISelLowering.cpp

4073 ↗

(On Diff #158529)

I think that this should be a user-visible error message as it is not obvious to a user why TLS might not be supported.

Another possibility is to just warn and use the small code model for TLS. This would cause problems for people that must avoid ADRP due to position independent requirements on 4k page alignment, but I think that could be a small minority of people.

4795 ↗

(On Diff #158529)

You may be able to simplify this as getTargetMachine().getCodeModel() == CodeModel::Tiny implies ELF as getEffectiveCodeModel so you shouldn't need to test if the Subtarget->isTargetMachO(). Probably not a lot in it though.

[dmgreen]

In D49673#1198678, @peter.smith wrote:

Generally looking good to me. Apologies for the delay.

Thanks for the review

As a general nit, the patch has been a bit inconsistent about preserving/removing curly braces after if/else statements with only a single statement in the body. It may be better to either preserve all as they are or change all of them; not a critical comment by any means.

If in doubt, follow what was already there. I'll try to keep things as they were.

It would be good to add a test in MC for a relocated ADR instruction with the :got: modifier.

Added some test for adr/adrp errors. There are others in MC to cover testing adr with a label. I changed the tryParseAdrLabel a little to make the error's better.

It would also be good to add a test to check what happens when someone attempts to use TLS with the tiny code model.

Hmm.. So I was expecting this would keep working the same as small model. I believe that would be less efficient but functionally correct (providing you are not un-aligning page boundaries). In adding some tests I can see that there are some code differences though (because it goes through LOADgot). I think the example in arm64-tls-execs is correct, and the other tests here produce the same code (as does your example from above). I've not tested this very well though, and I'm not sure what else would be required. As far as I can tell it should be OK, but producing an error for tiny+tls, same as large+tls, is an option.

lib/Target/AArch64/AArch64ISelLowering.cpp

4073 ↗

(On Diff #158529)

I agree the behaviour here for Large isn't so great. It will assert, or just use the small code here in release builds without asserts. I've changed that to a fatal error.

I'm not sure how to add a warning for tiny+tls.

[dmgreen]

In D49673#1199590, @dmgreen wrote:

Hmm.. So I was expecting this would keep working the same as small model. I believe that would be less efficient but functionally correct (providing you are not un-aligning page boundaries). In adding some tests I can see that there are some code differences though (because it goes through LOADgot). I think the example in arm64-tls-execs is correct, and the other tests here produce the same code (as does your example from above). I've not tested this very well though, and I'm not sure what else would be required. As far as I can tell it should be OK, but producing an error for tiny+tls, same as large+tls, is an option.

I've been testing out some examples with tls + tiny [+ pic]. As far as I can tell from the code I've ran, everything is working as expected.

[peter.smith]

From what I can see, it should just be the InitialExec model that does a LOADgot which should match the GCC behaviour with respect to TLS; so I'm happy with that for this patch. I think we can add better support for tiny code model TLS later if there is a need for it. I don't have any more comments myself, if there are no other comments from the other reviewers by the end of the week I'll LGTM.

lib/Target/AArch64/AArch64ISelLowering.cpp

4073 ↗

(On Diff #158529)

Ok. Probably worth just adding a comment/FIXME that the tiny code model uses the small code model TLS sequences and that some optimization is possible.

[peter.smith]

Looks good to me. I've not seen any other comments and I've no further comments.

[dmgreen]

Thanks Peter. This change just adds a FIXME for tiny+tls.

Mind taking a look at the hopefully trivial clang part of this in D49674? I can then commit the two parts together.

llvm/trunk/bindings/go/llvm/target.go

const (
   CodeGenLevelLess       CodeGenOptLevel = C.LLVMCodeGenLevelLess
   CodeGenLevelDefault    CodeGenOptLevel = C.LLVMCodeGenLevelDefault
   CodeGenLevelAggressive CodeGenOptLevel = C.LLVMCodeGenLevelAggressive
 )
 
 const (
   CodeModelDefault    CodeModel = C.LLVMCodeModelDefault
   CodeModelJITDefault CodeModel = C.LLVMCodeModelJITDefault
+  CodeModelTiny       CodeModel = C.LLVMCodeModelTiny
   CodeModelSmall      CodeModel = C.LLVMCodeModelSmall
   CodeModelKernel     CodeModel = C.LLVMCodeModelKernel
   CodeModelMedium     CodeModel = C.LLVMCodeModelMedium
   CodeModelLarge      CodeModel = C.LLVMCodeModelLarge
 )
 
 const (
   AssemblyFile CodeGenFileType = C.LLVMAssemblyFile

llvm/trunk/docs/CommandGuide/lli.rst

 
 .. option:: -code-model=model
 
  Choose the code model from:
 
  .. code-block:: text
 
       default: Target default code model
+      tiny: Tiny code model
       small: Small code model
       kernel: Kernel code model
       medium: Medium code model
       large: Large code model
 
 .. option:: -disable-post-RA-scheduler
 
  Disable scheduling after register allocation.

llvm/trunk/include/llvm-c/TargetMachine.h

typedef enum {
     LLVMRelocStatic,
     LLVMRelocPIC,
     LLVMRelocDynamicNoPic
 } LLVMRelocMode;
 
 typedef enum {
     LLVMCodeModelDefault,
     LLVMCodeModelJITDefault,
+    LLVMCodeModelTiny,
     LLVMCodeModelSmall,
     LLVMCodeModelKernel,
     LLVMCodeModelMedium,
     LLVMCodeModelLarge
 } LLVMCodeModel;
 
 typedef enum {
     LLVMAssemblyFile,

llvm/trunk/include/llvm/CodeGen/CommandFlags.inc

static cl::opt<ThreadModel::Model> TMModel(
     "thread-model", cl::desc("Choose threading model"),
     cl::init(ThreadModel::POSIX),
     cl::values(clEnumValN(ThreadModel::POSIX, "posix", "POSIX thread model"),
                clEnumValN(ThreadModel::Single, "single",
                           "Single thread model")));
 
 static cl::opt<llvm::CodeModel::Model> CMModel(
     "code-model", cl::desc("Choose code model"),
-    cl::values(clEnumValN(CodeModel::Small, "small", "Small code model"),
+    cl::values(clEnumValN(CodeModel::Tiny, "tiny", "Tiny code model"),
+               clEnumValN(CodeModel::Small, "small", "Small code model"),
                clEnumValN(CodeModel::Kernel, "kernel", "Kernel code model"),
                clEnumValN(CodeModel::Medium, "medium", "Medium code model"),
                clEnumValN(CodeModel::Large, "large", "Large code model")));
 
 LLVM_ATTRIBUTE_UNUSED static Optional<CodeModel::Model> getCodeModel() {
   if (CMModel.getNumOccurrences()) {
     CodeModel::Model M = CMModel;
     return M;

llvm/trunk/include/llvm/Support/CodeGen.h

namespace llvm {
   // Relocation model types.
   namespace Reloc {
   enum Model { Static, PIC_, DynamicNoPIC, ROPI, RWPI, ROPI_RWPI };
   }
 
   // Code model types.
   namespace CodeModel {
     // Sync changes with CodeGenCWrappers.h.
-  enum Model { Small, Kernel, Medium, Large };
+  enum Model { Tiny, Small, Kernel, Medium, Large };
   }
 
   namespace PICLevel {
     // This is used to map -fpic/-fPIC.
     enum Level { NotPIC=0, SmallPIC=1, BigPIC=2 };
   }
 
   namespace PIELevel {

llvm/trunk/include/llvm/Target/CodeGenCWrappers.h

 inline Optional<CodeModel::Model> unwrap(LLVMCodeModel Model, bool &JIT) {
   JIT = false;
   switch (Model) {
   case LLVMCodeModelJITDefault:
     JIT = true;
     LLVM_FALLTHROUGH;
   case LLVMCodeModelDefault:
     return None;
+  case LLVMCodeModelTiny:
+    return CodeModel::Tiny;
   case LLVMCodeModelSmall:
     return CodeModel::Small;
   case LLVMCodeModelKernel:
     return CodeModel::Kernel;
   case LLVMCodeModelMedium:
     return CodeModel::Medium;
   case LLVMCodeModelLarge:
     return CodeModel::Large;
   }
   return CodeModel::Small;
 }
 
 inline LLVMCodeModel wrap(CodeModel::Model Model) {
   switch (Model) {
+  case CodeModel::Tiny:
+    return LLVMCodeModelTiny;
   case CodeModel::Small:
     return LLVMCodeModelSmall;
   case CodeModel::Kernel:
     return LLVMCodeModelKernel;
   case CodeModel::Medium:
     return LLVMCodeModelMedium;
   case CodeModel::Large:
     return LLVMCodeModelLarge;
   }
   llvm_unreachable("Bad CodeModel!");
 }
 } // namespace llvm
 
 #endif

llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

MachineInstrBuilder MIB1 =
             .add(MI.getOperand(2))
             .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
     transferImpOps(MI, MIB1, MIB1);
     MI.eraseFromParent();
     return true;
   }
 
   case AArch64::LOADgot: {
-    // Expand into ADRP + LDR.
+    MachineFunction *MF = MBB.getParent();
     unsigned DstReg = MI.getOperand(0).getReg();
     const MachineOperand &MO1 = MI.getOperand(1);
     unsigned Flags = MO1.getTargetFlags();
+
+    if (MF->getTarget().getCodeModel() == CodeModel::Tiny) {
+      // Tiny codemodel expand to LDR
+      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
+                                        TII->get(AArch64::LDRXl), DstReg);
+
+      if (MO1.isGlobal()) {
+        MIB.addGlobalAddress(MO1.getGlobal(), 0, Flags);
+      } else if (MO1.isSymbol()) {
+        MIB.addExternalSymbol(MO1.getSymbolName(), Flags);
+      } else {
+        assert(MO1.isCPI() &&
+               "Only expect globals, externalsymbols, or constant pools");
+        MIB.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(), Flags);
+      }
+    } else {
+      // Small codemodel expand into ADRP + LDR.
       MachineInstrBuilder MIB1 =
           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg);
       MachineInstrBuilder MIB2 =
           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::LDRXui))
               .add(MI.getOperand(0))
               .addReg(DstReg);
 
       if (MO1.isGlobal()) {
         MIB1.addGlobalAddress(MO1.getGlobal(), 0, Flags | AArch64II::MO_PAGE);
         MIB2.addGlobalAddress(MO1.getGlobal(), 0,
                               Flags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
       } else if (MO1.isSymbol()) {
         MIB1.addExternalSymbol(MO1.getSymbolName(), Flags | AArch64II::MO_PAGE);
-      MIB2.addExternalSymbol(MO1.getSymbolName(),
-                             Flags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
+        MIB2.addExternalSymbol(MO1.getSymbolName(), Flags |
+                                                        AArch64II::MO_PAGEOFF |
+                                                        AArch64II::MO_NC);
       } else {
         assert(MO1.isCPI() &&
                "Only expect globals, externalsymbols, or constant pools");
         MIB1.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(),
                                   Flags | AArch64II::MO_PAGE);
         MIB2.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(),
                                   Flags | AArch64II::MO_PAGEOFF |
                                       AArch64II::MO_NC);
       }
 
       transferImpOps(MI, MIB1, MIB2);
+    }
     MI.eraseFromParent();
     return true;
   }
 
   case AArch64::MOVaddr:
   case AArch64::MOVaddrJT:
   case AArch64::MOVaddrCP:
   case AArch64::MOVaddrBA:

llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp

void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
   if (windowsRequiresStackProbe(MF, NumBytes)) {
     uint32_t NumWords = NumBytes >> 4;
 
     BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVi64imm), AArch64::X15)
         .addImm(NumWords)
         .setMIFlags(MachineInstr::FrameSetup);
 
     switch (MF.getTarget().getCodeModel()) {
+    case CodeModel::Tiny:
     case CodeModel::Small:
     case CodeModel::Medium:
     case CodeModel::Kernel:
       BuildMI(MBB, MBBI, DL, TII->get(AArch64::BL))
           .addExternalSymbol("__chkstk")
           .addReg(AArch64::X15, RegState::Implicit)
           .setMIFlags(MachineInstr::FrameSetup);
       break;

llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h

enum NodeType : unsigned {
   FIRST_NUMBER = ISD::BUILTIN_OP_END,
   WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
   CALL,         // Function call.
 
   // Produces the full sequence of instructions for getting the thread pointer
   // offset of a variable into X0, using the TLSDesc model.
   TLSDESC_CALLSEQ,
   ADRP,     // Page address of a TargetGlobalAddress operand.
+  ADR,      // ADR
   ADDlow,   // Add the low 12 bits of a TargetGlobalAddress operand.
   LOADgot,  // Load from automatically generated descriptor (e.g. Global
             // Offset Table, TLS record).
   RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
   BRCOND,   // Conditional branch instruction; "b.cond".
   CSEL,
   FCSEL, // Conditional move instruction.
   CSINV, // Conditional select invert.
private:
   SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
                         unsigned Flag) const;
   template <class NodeTy>
   SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
   template <class NodeTy>
   SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
   template <class NodeTy>
   SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
+  template <class NodeTy>
+  SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
   SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL,
                                  SelectionDAG &DAG) const;
   SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;

llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp

AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
   return AArch64::createFastISel(funcInfo, libInfo);
 }
 
 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((AArch64ISD::NodeType)Opcode) {
   case AArch64ISD::FIRST_NUMBER:      break;
   case AArch64ISD::CALL:              return "AArch64ISD::CALL";
   case AArch64ISD::ADRP:              return "AArch64ISD::ADRP";
+  case AArch64ISD::ADR:               return "AArch64ISD::ADR";
   case AArch64ISD::ADDlow:            return "AArch64ISD::ADDlow";
   case AArch64ISD::LOADgot:           return "AArch64ISD::LOADgot";
   case AArch64ISD::RET_FLAG:          return "AArch64ISD::RET_FLAG";
   case AArch64ISD::BRCOND:            return "AArch64ISD::BRCOND";
   case AArch64ISD::CSEL:              return "AArch64ISD::CSEL";
   case AArch64ISD::FCSEL:             return "AArch64ISD::FCSEL";
   case AArch64ISD::CSINV:             return "AArch64ISD::CSINV";
   case AArch64ISD::CSNEG:             return "AArch64ISD::CSNEG";
SDValue AArch64TargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
   EVT Ty = getPointerTy(DAG.getDataLayout());
   SDValue Hi = getTargetNode(N, Ty, DAG, AArch64II::MO_PAGE | Flags);
   SDValue Lo = getTargetNode(N, Ty, DAG,
                              AArch64II::MO_PAGEOFF | AArch64II::MO_NC | Flags);
   SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, Ty, Hi);
   return DAG.getNode(AArch64ISD::ADDlow, DL, Ty, ADRP, Lo);
 }
 
+// (adr sym)
+template <class NodeTy>
+SDValue AArch64TargetLowering::getAddrTiny(NodeTy *N, SelectionDAG &DAG,
+                                           unsigned Flags) const {
+  LLVM_DEBUG(dbgs() << "AArch64TargetLowering::getAddrTiny\n");
+  SDLoc DL(N);
+  EVT Ty = getPointerTy(DAG.getDataLayout());
+  SDValue Sym = getTargetNode(N, Ty, DAG, Flags);
+  return DAG.getNode(AArch64ISD::ADR, DL, Ty, Sym);
+}
+
 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
                                                   SelectionDAG &DAG) const {
   GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
   const GlobalValue *GV = GN->getGlobal();
   const AArch64II::TOF TargetFlags =
       (GV->hasDLLImportStorageClass() ? AArch64II::MO_DLLIMPORT
                                       : AArch64II::MO_NO_FLAG);
   unsigned char OpFlags =
       Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
 
   if (OpFlags != AArch64II::MO_NO_FLAG)
     assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
            "unexpected offset in global node");
 
-  // This also catches the large code model case for Darwin.
+  // This also catches the large code model case for Darwin, and tiny code
+  // model with got relocations.
   if ((OpFlags & AArch64II::MO_GOT) != 0) {
     return getGOT(GN, DAG, TargetFlags);
   }
 
   SDValue Result;
   if (getTargetMachine().getCodeModel() == CodeModel::Large) {
     Result = getAddrLarge(GN, DAG, TargetFlags);
+  } else if (getTargetMachine().getCodeModel() == CodeModel::Tiny) {
+    Result = getAddrTiny(GN, DAG, TargetFlags);
   } else {
     Result = getAddr(GN, DAG, TargetFlags);
   }
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
   SDLoc DL(GN);
   if (GV->hasDLLImportStorageClass())
     Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
                          MachinePointerInfo::getGOT(DAG.getMachineFunction()));
SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr,
 
   return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
 }
 
 SDValue
 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
                                                 SelectionDAG &DAG) const {
   assert(Subtarget->isTargetELF() && "This function expects an ELF target");
-  assert(Subtarget->useSmallAddressing() &&
-         "ELF TLS only supported in small memory model");
+  if (getTargetMachine().getCodeModel() == CodeModel::Large)
+    report_fatal_error("ELF TLS only supported in small memory model");
   // Different choices can be made for the maximum size of the TLS area for a
   // module. For the small address model, the default TLS size is 16MiB and the
   // maximum TLS size is 4GiB.
   // FIXME: add -mtls-size command line option and make it control the 16MiB
   // vs. 4GiB code sequence generation.
+  // FIXME: add tiny codemodel support. We currently generate the same code as
+  // small, which may be larger than needed.
   const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
 
   TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
 
   if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
     if (Model == TLSModel::LocalDynamic)
       Model = TLSModel::GeneralDynamic;
   }
SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
                                               SelectionDAG &DAG) const {
   // Jump table entries as PC relative offsets. No additional tweaking
   // is necessary here. Just get the address of the jump table.
   JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
 
   if (getTargetMachine().getCodeModel() == CodeModel::Large &&
       !Subtarget->isTargetMachO()) {
     return getAddrLarge(JT, DAG);
+  } else if (getTargetMachine().getCodeModel() == CodeModel::Tiny) {
+    return getAddrTiny(JT, DAG);
   }
   return getAddr(JT, DAG);
 }
 
 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
                                                  SelectionDAG &DAG) const {
   ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
 
   if (getTargetMachine().getCodeModel() == CodeModel::Large) {
     // Use the GOT for the large code model on iOS.
     if (Subtarget->isTargetMachO()) {
       return getGOT(CP, DAG);
     }
     return getAddrLarge(CP, DAG);
+  } else if (getTargetMachine().getCodeModel() == CodeModel::Tiny) {
+    return getAddrTiny(CP, DAG);
   } else {
     return getAddr(CP, DAG);
   }
 }
 
 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
                                                SelectionDAG &DAG) const {
   BlockAddressSDNode *BA = cast<BlockAddressSDNode>(Op);
   if (getTargetMachine().getCodeModel() == CodeModel::Large &&
       !Subtarget->isTargetMachO()) {
     return getAddrLarge(BA, DAG);
-  } else {
-    return getAddr(BA, DAG);
+  } else if (getTargetMachine().getCodeModel() == CodeModel::Tiny) {
+    return getAddrTiny(BA, DAG);
   }
+  return getAddr(BA, DAG);
 }
 
 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
                                                  SelectionDAG &DAG) const {
   AArch64FunctionInfo *FuncInfo =
       DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
 
   SDLoc DL(Op);

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

if ((OpFlags & AArch64II::MO_GOT) != 0) {
     BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
         .addReg(Reg, RegState::Kill)
         .addGlobalAddress(GV, 0, AArch64II::MO_G3)
         .addImm(48);
     BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
         .addReg(Reg, RegState::Kill)
         .addImm(0)
         .addMemOperand(*MI.memoperands_begin());
+  } else if (TM.getCodeModel() == CodeModel::Tiny) {
+    BuildMI(MBB, MI, DL, get(AArch64::ADR), Reg)
+        .addGlobalAddress(GV, 0, OpFlags);
   } else {
     BuildMI(MBB, MI, DL, get(AArch64::ADRP), Reg)
         .addGlobalAddress(GV, 0, OpFlags | AArch64II::MO_PAGE);
     unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | MO_NC;
     BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
         .addReg(Reg, RegState::Kill)
         .addGlobalAddress(GV, 0, LoFlags)
         .addMemOperand(*MI.memoperands_begin());

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td

 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
                                         [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
                                          SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
                                          SDTCisSameAs<1, 4>]>;
 
 
 // Node definitions.
 def AArch64adrp          : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
+def AArch64adr           : SDNode<"AArch64ISD::ADR", SDTIntUnaryOp, []>;
 def AArch64addlow        : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
 def AArch64LOADgot       : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
                                 SDCallSeqStart<[ SDTCisVT<0, i32>,
                                                  SDTCisVT<1, i32> ]>,
                                 [SDNPHasChain, SDNPOutGlue]>;
 def AArch64callseq_end   : SDNode<"ISD::CALLSEQ_END",
                                 SDCallSeqEnd<[ SDTCisVT<0, i32>,

 def : InstAlias<"cneg $dst, $src, $cc",
                 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
 
 //===----------------------------------------------------------------------===//
 // PC-relative instructions.
 //===----------------------------------------------------------------------===//
 let isReMaterializable = 1 in {
 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
-def ADR  : ADRI<0, "adr", adrlabel, []>;
+def ADR  : ADRI<0, "adr", adrlabel,
+                [(set GPR64:$Xd, (AArch64adr tglobaladdr:$label))]>;
 } // hasSideEffects = 0
 
 def ADRP : ADRI<1, "adrp", adrplabel,
                 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
 } // isReMaterializable = 1
 
 // page address of a constant pool entry, block address
+def : Pat<(AArch64adr tconstpool:$cp), (ADR tconstpool:$cp)>;
+def : Pat<(AArch64adr tblockaddress:$cp), (ADR tblockaddress:$cp)>;
+def : Pat<(AArch64adr texternalsym:$sym), (ADR texternalsym:$sym)>;
+def : Pat<(AArch64adr tjumptable:$sym), (ADR tjumptable:$sym)>;
 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
 def : Pat<(AArch64adrp texternalsym:$sym), (ADRP texternalsym:$sym)>;
 
 //===----------------------------------------------------------------------===//
 // Unconditional branch (register) instructions.
 //===----------------------------------------------------------------------===//
 

llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp

case TargetOpcode::G_GLOBAL_VALUE: {
     if (OpFlags & AArch64II::MO_GOT) {
       I.setDesc(TII.get(AArch64::LOADgot));
       I.getOperand(1).setTargetFlags(OpFlags);
     } else if (TM.getCodeModel() == CodeModel::Large) {
       // Materialize the global using movz/movk instructions.
       materializeLargeCMVal(I, GV, OpFlags);
       I.eraseFromParent();
       return true;
+    } else if (TM.getCodeModel() == CodeModel::Tiny) {
+      I.setDesc(TII.get(AArch64::ADR));
+      I.getOperand(1).setTargetFlags(OpFlags);
     } else {
       I.setDesc(TII.get(AArch64::MOVaddr));
       I.getOperand(1).setTargetFlags(OpFlags | AArch64II::MO_PAGE);
       MachineInstrBuilder MIB(MF, I);
       MIB.addGlobalAddress(GV, I.getOperand(1).getOffset(),
                            OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
     }
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp

AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
   unsigned Flags = GV->hasDLLImportStorageClass() ? AArch64II::MO_DLLIMPORT
                                                   : AArch64II::MO_NO_FLAG;
 
   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
     return AArch64II::MO_GOT | Flags;
 
   // The small code model's direct accesses use ADRP, which cannot
   // necessarily produce the value 0 (if the code is above 4GB).
-  if (useSmallAddressing() && GV->hasExternalWeakLinkage())
+  // Same for the tiny code model, where we have a pc relative LDR.
+  if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
+      GV->hasExternalWeakLinkage())
     return AArch64II::MO_GOT | Flags;
 
   return Flags;
 }
 
 unsigned char AArch64Subtarget::classifyGlobalFunctionReference(
     const GlobalValue *GV, const TargetMachine &TM) const {
   // MachO large model always goes via a GOT, because we don't have the

llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp

if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
     return Reloc::Static;
   return *RM;
 }
 
 static CodeModel::Model getEffectiveCodeModel(const Triple &TT,
                                               Optional<CodeModel::Model> CM,
                                               bool JIT) {
   if (CM) {
-    if (*CM != CodeModel::Small && *CM != CodeModel::Large) {
+    if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
+        *CM != CodeModel::Large) {
       if (!TT.isOSFuchsia())
         report_fatal_error(
-            "Only small and large code models are allowed on AArch64");
-      else if (CM != CodeModel::Kernel)
-        report_fatal_error(
-            "Only small, kernel, and large code models are allowed on AArch64");
-    }
+            "Only small, tiny and large code models are allowed on AArch64");
+      else if (*CM != CodeModel::Kernel)
+        report_fatal_error("Only small, tiny, kernel, and large code models "
+                           "are allowed on AArch64");
+    } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
+      report_fatal_error("tiny code model is only supported on ELF");
     return *CM;
   }
   // The default MCJIT memory managers make no guarantees about where they can
   // find an executable page; JITed code needs to be able to refer to globals
   // no matter how far away they are.
   if (JIT)
     return CodeModel::Large;
   return CodeModel::Small;

llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

 
 /// tryParseAdrLabel - Parse and validate a source label for the ADR
 /// instruction.
 OperandMatchResultTy
 AArch64AsmParser::tryParseAdrLabel(OperandVector &Operands) {
   SMLoc S = getLoc();
   const MCExpr *Expr;
 
-  const AsmToken &Tok = getParser().getTok();
-  if (parseOptionalToken(AsmToken::Hash) || Tok.is(AsmToken::Integer)) {
-    if (getParser().parseExpression(Expr))
-      return MatchOperand_ParseFail;
+  // Leave anything with a bracket to the default for SVE
+  if (getParser().getTok().is(AsmToken::LBrac))
+    return MatchOperand_NoMatch;
+
+  if (getParser().getTok().is(AsmToken::Hash))
+    getParser().Lex(); // Eat hash token.
+
+  if (parseSymbolicImmVal(Expr))
 
-    SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
-    Operands.push_back(AArch64Operand::CreateImm(Expr, S, E, getContext()));
-
-    return MatchOperand_Success;
-  }
-  return MatchOperand_NoMatch;
-}
+  AArch64MCExpr::VariantKind ELFRefKind;
+  MCSymbolRefExpr::VariantKind DarwinRefKind;
+  int64_t Addend;
+  if (classifySymbolRef(Expr, ELFRefKind, DarwinRefKind, Addend)) {
+    if (DarwinRefKind == MCSymbolRefExpr::VK_None &&
+        ELFRefKind == AArch64MCExpr::VK_INVALID) {
+      // No modifier was specified at all; this is the syntax for an ELF basic
+      // ADR relocation (unfortunately).
+      Expr = AArch64MCExpr::create(Expr, AArch64MCExpr::VK_ABS, getContext());
+    } else {
+      Error(S, "unexpected adr label");
+      return MatchOperand_ParseFail;
+    }
+  }
+
 
 /// tryParseFPImm - A floating point immediate expression operand.
 template<bool AddFPZeroAsLiteral>
 OperandMatchResultTy
 AArch64AsmParser::tryParseFPImm(OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
   SMLoc S = getLoc();
 

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

 //===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AArch64.h"
 #include "AArch64RegisterInfo.h"
 #include "MCTargetDesc/AArch64FixupKinds.h"
+#include "MCTargetDesc/AArch64MCExpr.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/BinaryFormat/MachO.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDirectives.h"
 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/MC/MCFixupKindInfo.h"
bool AArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm,
   //
   // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
   // we'll need that as an offset. At any other address "there" will be in the
   // same page as the ADRP and the instruction should encode 0x0. Assuming the
   // section isn't 0x1000-aligned, we therefore need to delegate this decision
   // to the linker -- a relocation!
   if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_pcrel_adrp_imm21)
     return true;
+
+  AArch64MCExpr::VariantKind RefKind =
+      static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
+  AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
+  // LDR GOT relocations need a relocation
+  if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_ldr_pcrel_imm19 &&
+      SymLoc == AArch64MCExpr::VK_GOT)
+    return true;
   return false;
 }
 
 namespace {
 
 namespace CU {
 
 /// Compact unwind encoding values.

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp

case FK_Data_8:
       if (IsILP32) {
         Ctx.reportError(Fixup.getLoc(),
                         "ILP32 8 byte PC relative data "
                         "relocation not supported (LP64 eqv: PREL64)");
         return ELF::R_AARCH64_NONE;
       } else
         return ELF::R_AARCH64_PREL64;
     case AArch64::fixup_aarch64_pcrel_adr_imm21:
-      assert(SymLoc == AArch64MCExpr::VK_NONE && "unexpected ADR relocation");
+      if (SymLoc != AArch64MCExpr::VK_ABS)
+        Ctx.reportError(Fixup.getLoc(),
+                        "invalid symbol kind for ADR relocation");
       return R_CLS(ADR_PREL_LO21);
     case AArch64::fixup_aarch64_pcrel_adrp_imm21:
       if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC)
         return R_CLS(ADR_PREL_PG_HI21);
       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) {
         if (IsILP32) {
           Ctx.reportError(Fixup.getLoc(),
                           "invalid fixup for 32-bit pcrel ADRP instruction "

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp

StringRef AArch64MCExpr::getVariantKindName() const {
   case VK_TPREL_G0:            return ":tprel_g0:";
   case VK_TPREL_G0_NC:         return ":tprel_g0_nc:";
   case VK_TPREL_HI12:          return ":tprel_hi12:";
   case VK_TPREL_LO12:          return ":tprel_lo12:";
   case VK_TPREL_LO12_NC:       return ":tprel_lo12_nc:";
   case VK_TLSDESC_LO12:        return ":tlsdesc_lo12:";
   case VK_ABS_PAGE:            return "";
   case VK_ABS_PAGE_NC:         return ":pg_hi21_nc:";
+  case VK_GOT:                 return ":got:";
   case VK_GOT_PAGE:            return ":got:";
   case VK_GOT_LO12:            return ":got_lo12:";
+  case VK_GOTTPREL:            return ":gottprel:";
   case VK_GOTTPREL_PAGE:       return ":gottprel:";
   case VK_GOTTPREL_LO12_NC:    return ":gottprel_lo12:";
   case VK_GOTTPREL_G1:         return ":gottprel_g1:";
   case VK_GOTTPREL_G0_NC:      return ":gottprel_g0_nc:";
   case VK_TLSDESC:             return "";
   case VK_TLSDESC_PAGE:        return ":tlsdesc:";
   case VK_SECREL_LO12:         return ":secrel_lo12:";
   case VK_SECREL_HI12:         return ":secrel_hi12:";

llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp

if (NumWords < 65536)
           .setMIFlags(MachineInstr::FrameSetup)
           .add(predOps(ARMCC::AL));
     else
       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
         .addImm(NumWords)
         .setMIFlags(MachineInstr::FrameSetup);
 
     switch (TM.getCodeModel()) {
+    case CodeModel::Tiny:
+      llvm_unreachable("Tiny code model not available on ARM.");
     case CodeModel::Small:
     case CodeModel::Medium:
     case CodeModel::Kernel:
       BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
           .add(predOps(ARMCC::AL))
           .addExternalSymbol("__chkstk")
           .addReg(ARM::R4, RegState::Implicit)
           .setMIFlags(MachineInstr::FrameSetup);

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI,
   //
   // Finally, although some linkers may theoretically provide a trampoline for
   // out of range calls (which is quite common due to a 32M range limitation of
   // branches for Thumb), we can generate the long-call version via
   // -mcmodel=large, alleviating the need for the trampoline which may clobber
   // IP.
 
   switch (TM.getCodeModel()) {
+  case CodeModel::Tiny:
+    llvm_unreachable("Tiny code model not available on ARM.");
   case CodeModel::Small:
   case CodeModel::Medium:
   case CodeModel::Kernel:
     BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
         .add(predOps(ARMCC::AL))
         .addExternalSymbol("__chkstk")
         .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
         .addReg(ARM::R4, RegState::Implicit | RegState::Define)

llvm/trunk/lib/Target/X86/X86Subtarget.cpp

X86Subtarget::classifyLocalReference(const GlobalValue *GV) const {
   if (!isPositionIndependent())
     return X86II::MO_NO_FLAG;
 
   if (is64Bit()) {
     // 64-bit ELF PIC local references may use GOTOFF relocations.
     if (isTargetELF()) {
       switch (TM.getCodeModel()) {
       // 64-bit small code model is simple: All rip-relative.
+      case CodeModel::Tiny:
+        llvm_unreachable("Tiny codesize model not supported on X86");
       case CodeModel::Small:
       case CodeModel::Kernel:
         return X86II::MO_NO_FLAG;
 
       // The large PIC code model uses GOTOFF.
       case CodeModel::Large:
         return X86II::MO_GOTOFF;
 

llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-none-eabi -code-model=tiny -run-pass=instruction-select -verify-machineinstrs -O0 %s -o - | FileCheck %s
+--- |
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+
+  @foo1 = common global [1073741824 x i32] zeroinitializer, align 4
+  @foo2 = common global [1073741824 x i32] zeroinitializer, align 4
+
+  define i32 @gv_tiny() {
+  entry:
+    %retval = alloca i32, align 4
+    store i32 0, i32* %retval, align 4
+    %0 = load i32, i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo1, i64 0, i64 0), align 4
+    %1 = load i32, i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo2, i64 0, i64 0), align 4
+    %add = add nsw i32 %0, %1
+    ret i32 %add
+  }
+
+...
+---
+name:            gv_tiny
+legalized:       true
+regBankSelected: true
+stack:
+  - { id: 0, name: retval, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
+constants:
+body:             |
+  bb.1:
+    ; CHECK-LABEL: name: gv_tiny
+    ; CHECK: [[ADR:%[0-9]+]]:gpr64 = ADR @foo1
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY [[ADR]]
+    ; CHECK: [[ADR1:%[0-9]+]]:gpr64 = ADR @foo2
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[ADR1]]
+    ; CHECK: STRWui $wzr, %stack.0.retval, 0 :: (store 4 into %ir.retval)
+    ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load 4 from `i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo1, i64 0, i64 0)`)
+    ; CHECK: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[COPY1]], 0 :: (load 4 from `i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo2, i64 0, i64 0)`)
+    ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRWui]], [[LDRWui1]]
+    ; CHECK: $w0 = COPY [[ADDWrr]]
+    ; CHECK: RET_ReallyLR implicit $w0
+    %1:gpr(s32) = G_CONSTANT i32 0
+    %4:gpr(p0) = G_GLOBAL_VALUE @foo1
+    %3:gpr(p0) = COPY %4(p0)
+    %7:gpr(p0) = G_GLOBAL_VALUE @foo2
+    %6:gpr(p0) = COPY %7(p0)
+    %0:gpr(p0) = G_FRAME_INDEX %stack.0.retval
+    G_STORE %1(s32), %0(p0) :: (store 4 into %ir.retval)
+    %2:gpr(s32) = G_LOAD %3(p0) :: (load 4 from `i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo1, i64 0, i64 0)`)
+    %5:gpr(s32) = G_LOAD %6(p0) :: (load 4 from `i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo2, i64 0, i64 0)`)
+    %8:gpr(s32) = G_ADD %2, %5
+    $w0 = COPY %8(s32)
+    RET_ReallyLR implicit $w0
+
+...

llvm/trunk/test/CodeGen/AArch64/arm64-tls-dynamics.ll

 ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
 ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOLD %s
 ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-NOLD-RELOC %s
+; FIXME: We currently produce "small" code for the tiny model
+; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -code-model=tiny -verify-machineinstrs < %s | FileCheck %s
+; FIXME: We currently error for the large code model
+; RUN: not llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -code-model=large -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LARGE
+
+; CHECK-LARGE: ELF TLS only supported in small memory model
 
 @general_dynamic_var = external thread_local global i32
 
 define i32 @test_generaldynamic() {
 ; CHECK-LABEL: test_generaldynamic:
 
   %val = load i32, i32* @general_dynamic_var
   ret i32 %val

llvm/trunk/test/CodeGen/AArch64/arm64-tls-execs.ll

 ; RUN: llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s
 ; RUN: llc -mtriple=arm64-none-linux-gnu -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
+; RUN: llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs -show-mc-encoding -code-model=tiny < %s | FileCheck %s --check-prefix=CHECK-TINY
+; RUN: llc -mtriple=arm64-none-linux-gnu -filetype=obj < %s -code-model=tiny | llvm-objdump -r - | FileCheck --check-prefix=CHECK-TINY-RELOC %s
+; FIXME: We currently error for the large code model
+; RUN: not llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs -show-mc-encoding -code-model=large < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LARGE
+
+; CHECK-LARGE: ELF TLS only supported in small memory model
 
 @initial_exec_var = external thread_local(initialexec) global i32
 
 define i32 @test_initial_exec() {
 ; CHECK-LABEL: test_initial_exec:
   %val = load i32, i32* @initial_exec_var
 
 ; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var
 ; CHECK: ldr x[[TP_OFFSET:[0-9]+]], [x[[GOTADDR]], :gottprel_lo12:initial_exec_var]
 ; CHECK: mrs x[[TP:[0-9]+]], TPIDR_EL0
 ; CHECK: ldr w0, [x[[TP]], x[[TP_OFFSET]]]
 
 ; CHECK-RELOC: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
 ; CHECK-RELOC: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
 
+; CHECK-TINY: ldr x[[TP_OFFSET:[0-9]+]], :gottprel:initial_exec_var
+; CHECK-TINY: mrs x[[TP:[0-9]+]], TPIDR_EL0
+; CHECK-TINY: ldr w0, [x[[TP]], x[[TP_OFFSET]]]
+
+; CHECK-TINY-RELOC: R_AARCH64_TLSIE_LD_GOTTPREL_PREL19
+
   ret i32 %val
 }
 
 define i32* @test_initial_exec_addr() {
 ; CHECK-LABEL: test_initial_exec_addr:
   ret i32* @initial_exec_var
 
 ; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var
 ; CHECK: ldr [[TP_OFFSET:x[0-9]+]], [x[[GOTADDR]], :gottprel_lo12:initial_exec_var]
 ; CHECK: mrs [[TP:x[0-9]+]], TPIDR_EL0
 ; CHECK: add x0, [[TP]], [[TP_OFFSET]]
 
 ; CHECK-RELOC: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
 ; CHECK-RELOC: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
 
+; CHECK-TINY: ldr x[[TP_OFFSET:[0-9]+]], :gottprel:initial_exec_var
+; CHECK-TINY: mrs [[TP:x[0-9]+]], TPIDR_EL0
+; CHECK-TINY: add x0, [[TP]], x[[TP_OFFSET]]
+
+; CHECK-TINY-RELOC: R_AARCH64_TLSIE_LD_GOTTPREL_PREL19
+
 }
 
 @local_exec_var = thread_local(localexec) global i32 0
 
 define i32 @test_local_exec() {
 ; CHECK-LABEL: test_local_exec:
   %val = load i32, i32* @local_exec_var
 
 ; CHECK: mrs x[[R1:[0-9]+]], TPIDR_EL0
 ; CHECK: add x[[R2:[0-9]+]], x[[R1]], :tprel_hi12:local_exec_var
 ; CHECK: add x[[R3:[0-9]+]], x[[R2]], :tprel_lo12_nc:local_exec_var
 ; CHECK: ldr w0, [x[[R3]]]
 
 ; CHECK-RELOC: R_AARCH64_TLSLE_ADD_TPREL_HI12
 ; CHECK-RELOC: R_AARCH64_TLSLE_ADD_TPREL_LO12_NC
+
+; CHECK-TINY: mrs x[[R1:[0-9]+]], TPIDR_EL0
+; CHECK-TINY: add x[[R2:[0-9]+]], x[[R1]], :tprel_hi12:local_exec_var
+; CHECK-TINY: add x[[R3:[0-9]+]], x[[R2]], :tprel_lo12_nc:local_exec_var
+; CHECK-TINY: ldr w0, [x[[R3]]]
+
+; CHECK-TINY-RELOC: R_AARCH64_TLSLE_ADD_TPREL_HI12
+; CHECK-TINY-RELOC: R_AARCH64_TLSLE_ADD_TPREL_LO12_NC
   ret i32 %val
 }
 
 define i32* @test_local_exec_addr() {
 ; CHECK-LABEL: test_local_exec_addr:
   ret i32* @local_exec_var
 
 ; CHECK: mrs x[[R1:[0-9]+]], TPIDR_EL0
 ; CHECK: add x[[R2:[0-9]+]], x[[R1]], :tprel_hi12:local_exec_var
 ; CHECK: add x0, x[[R2]], :tprel_lo12_nc:local_exec_var
 ; CHECK: ret
 
 ; CHECK-RELOC: R_AARCH64_TLSLE_ADD_TPREL_HI12
 ; CHECK-RELOC: R_AARCH64_TLSLE_ADD_TPREL_LO12_NC
+
+; CHECK-TINY: mrs x[[R1:[0-9]+]], TPIDR_EL0
+; CHECK-TINY: add x[[R2:[0-9]+]], x[[R1]], :tprel_hi12:local_exec_var
+; CHECK-TINY: add x0, x[[R2]], :tprel_lo12_nc:local_exec_var
+; CHECK-TINY: ret
+
+; CHECK-TINY-RELOC: R_AARCH64_TLSLE_ADD_TPREL_HI12
+; CHECK-TINY-RELOC: R_AARCH64_TLSLE_ADD_TPREL_LO12_NC
 }

llvm/trunk/test/CodeGen/AArch64/blockaddress.ll

 ; RUN: llc -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -code-model=large -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-LARGE %s
+; RUN: llc -code-model=tiny -mtriple=aarch64-none-none-eabi -aarch64-enable-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-TINY %s
 
 @addr = global i8* null
 
 define void @test_blockaddress() {
 ; CHECK-LABEL: test_blockaddress:
   store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr
   %val = load volatile i8*, i8** @addr
   indirectbr i8* %val, [label %block]
 ; CHECK: adrp [[DEST_HI:x[0-9]+]], [[DEST_LBL:.Ltmp[0-9]+]]
 ; CHECK: add [[DEST:x[0-9]+]], [[DEST_HI]], {{#?}}:lo12:[[DEST_LBL]]
 ; CHECK: str [[DEST]],
 ; CHECK: ldr [[NEWDEST:x[0-9]+]]
 ; CHECK: br [[NEWDEST]]
 
 ; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g0_nc:[[DEST_LBL:.Ltmp[0-9]+]]
 ; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g1_nc:[[DEST_LBL]]
 ; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
 ; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g3:[[DEST_LBL]]
 ; CHECK-LARGE: str [[ADDR_REG]],
 ; CHECK-LARGE: ldr [[NEWDEST:x[0-9]+]]
 ; CHECK-LARGE: br [[NEWDEST]]
 
+; CHECK-TINY: adr [[DEST:x[0-9]+]], {{.Ltmp[0-9]+}}
+; CHECK-TINY: str [[DEST]],
+; CHECK-TINY: ldr [[NEWDEST:x[0-9]+]]
+; CHECK-TINY: br [[NEWDEST]]
+
 block:
   ret void
 }

llvm/trunk/test/CodeGen/AArch64/code-model-tiny-abs.ll

+; RUN: llc -mtriple=aarch64-none-eabi -code-model=tiny < %s | FileCheck %s
+
+@var8 = global i8 0
+@var16 = global i16 0
+@var32 = global i32 0
+@var64 = global i64 0
+
+define i8* @global_addr() {
+; CHECK-LABEL: global_addr:
+  ret i8* @var8
+  ; The adr calculation should end up returned directly in x0.
+; CHECK: adr x0, var8
+; CHECK-NEXT: ret
+}
+
+define i8 @global_i8() {
+; CHECK-LABEL: global_i8:
+  %val = load i8, i8* @var8
+  ret i8 %val
+; CHECK: adr x[[ADDR_REG:[0-9]+]], var8
+; CHECK: ldrb w0, [x[[ADDR_REG]]]
+}
+
+define i16 @global_i16() {
+; CHECK-LABEL: global_i16:
+  %val = load i16, i16* @var16
+  ret i16 %val
+; CHECK: adr x[[ADDR_REG:[0-9]+]], var16
+; CHECK: ldrh w0, [x[[ADDR_REG]]]
+}
+
+define i32 @global_i32() {
+; CHECK-LABEL: global_i32:
+  %val = load i32, i32* @var32
+  ret i32 %val
+; CHECK: adr x[[ADDR_REG:[0-9]+]], var32
+; CHECK: ldr w0, [x[[ADDR_REG]]]
+}
+
+define i64 @global_i64() {
+; CHECK-LABEL: global_i64:
+  %val = load i64, i64* @var64
+  ret i64 %val
+; CHECK: adr x[[ADDR_REG:[0-9]+]], var64
+; CHECK: ldr x0, [x[[ADDR_REG]]]
+}
+
+define <2 x i64> @constpool() {
+; CHECK-LABEL: constpool:
+  ret <2 x i64> <i64 123456789, i64 987654321100>
+
+; CHECK: adr x[[ADDR_REG:[0-9]+]], {{.LCPI[0-9]+_[0-9]+}}
+; CHECK: ldr q0, [x[[ADDR_REG]]]
+}

llvm/trunk/test/CodeGen/AArch64/extern-weak.ll

 ; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=static -o - < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -code-model=large -o - %s | FileCheck --check-prefix=CHECK-LARGE %s
+; RUN: llc -mtriple=aarch64-none-none-eabi -code-model=tiny -o - %s | FileCheck --check-prefix=CHECK-TINY %s
 
 declare extern_weak i32 @var()
 
 define i32()* @foo() {
 ; The usual ADRP/ADD pair can't be used for a weak reference because it must
 ; evaluate to 0 if the symbol is undefined. We use a GOT entry for PIC
 ; otherwise a litpool entry.
   ret i32()* @var
 
 
 ; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:var
 ; CHECK: ldr x0, [x[[ADDRHI]], :got_lo12:var]
 
   ; In the large model, the usual relocations are absolute and can
   ; materialise 0.
 ; CHECK-LARGE: movz x0, #:abs_g0_nc:var
 ; CHECK-LARGE: movk x0, #:abs_g1_nc:var
 ; CHECK-LARGE: movk x0, #:abs_g2_nc:var
 ; CHECK-LARGE: movk x0, #:abs_g3:var
+
+  ; In the tiny codemodel we us a got relocated LDR.
+; CHECK-TINY: ldr x0, :got:var
 }
 
 
 @arr_var = extern_weak global [10 x i32]
 
 define i32* @bar() {
   %addr = getelementptr [10 x i32], [10 x i32]* @arr_var, i32 0, i32 5
 
 
 ; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:arr_var
 ; CHECK: ldr [[BASE:x[0-9]+]], [x[[ADDRHI]], :got_lo12:arr_var]
 ; CHECK: add x0, [[BASE]], #20
 
   ret i32* %addr
 
   ; In the large model, the usual relocations are absolute and can
   ; materialise 0.
 ; CHECK-LARGE: movz [[ADDR:x[0-9]+]], #:abs_g0_nc:arr_var
 ; CHECK-LARGE: movk [[ADDR]], #:abs_g1_nc:arr_var
 ; CHECK-LARGE: movk [[ADDR]], #:abs_g2_nc:arr_var
 ; CHECK-LARGE: movk [[ADDR]], #:abs_g3:arr_var
+
+; CHECK-TINY: ldr [[BASE:x[0-9]+]], :got:arr_var
+; CHECK-TINY: add x0, [[BASE]], #20
 }
 
 @defined_weak_var = internal unnamed_addr global i32 0
 
 define i32* @wibble() {
   ret i32* @defined_weak_var
 
 ; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var
 ; CHECK: add x0, [[BASE]], :lo12:defined_weak_var
 
 ; CHECK-LARGE: movz x0, #:abs_g0_nc:defined_weak_var
 ; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var
 ; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
 ; CHECK-LARGE: movk x0, #:abs_g3:defined_weak_var
+
+; CHECK-TINY: adr x0, defined_weak_var
 }

llvm/trunk/test/CodeGen/AArch64/fpimm.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu                                                  -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large                             -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE
 ; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE
+; RUN: llc -mtriple=aarch64-none-eabi    -code-model=tiny                              -verify-machineinstrs < %s | FileCheck %s --check-prefix=TINY
 
 @varf32 = global float 0.0
 @varf64 = global double 0.0
 
 define void @check_float() {
 ; CHECK-LABEL: check_float:
+; TINY-LABEL: check_float:
 
   %val = load float, float* @varf32
   %newval1 = fadd float %val, 8.5
   store volatile float %newval1, float* @varf32
-; CHECK-DAG: fmov [[EIGHT5:s[0-9]+]], #8.5
+; CHECK-DAG: fmov {{s[0-9]+}}, #8.5
+; TINY-DAG: fmov {{s[0-9]+}}, #8.5
 
   %newval2 = fadd float %val, 128.0
   store volatile float %newval2, float* @varf32
-; CHECK-DAG: ldr [[HARD:s[0-9]+]], [{{x[0-9]+}}, {{#?}}:lo12:.LCPI0_0
+; CHECK-DAG: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.LCPI0_0
+; TINY-DAG: ldr {{s[0-9]+}}, [{{x[0-9]+}}]
 
 ; CHECK: ret
+; TINY: ret
   ret void
 }
 
 define void @check_double() {
 ; CHECK-LABEL: check_double:
+; TINY-LABEL: check_double:
 
   %val = load double, double* @varf64
   %newval1 = fadd double %val, 8.5
   store volatile double %newval1, double* @varf64
 ; CHECK-DAG: fmov {{d[0-9]+}}, #8.5
+; TINY-DAG: fmov {{d[0-9]+}}, #8.5
 
   %newval2 = fadd double %val, 128.0
   store volatile double %newval2, double* @varf64
 ; CHECK-DAG: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.LCPI1_0
+; TINY-DAG: ldr {{d[0-9]+}}, [{{x[0-9]+}}]
 
 ; CHECK: ret
+; TINY: ret
   ret void
 }
 
 ; LARGE-LABEL: check_float2
 ; LARGE:       mov [[REG:w[0-9]+]], #4059
 ; LARGE-NEXT:  movk [[REG]], #16457, lsl #16
 ; LARGE-NEXT:  fmov s0, [[REG]]
+; TINY-LABEL: check_float2
+; TINY:       adr     x[[REG:[0-9]+]], .LCPI2_0
+; TINY-NEXT:  ldr     s0, [x[[REG]]]
 define float @check_float2() {
   ret float 3.14159274101257324218750
 }
 
 ; LARGE-LABEL: check_double2
 ; LARGE:       mov [[REG:x[0-9]+]], #11544
 ; LARGE-NEXT:  movk [[REG]], #21572, lsl #16
 ; LARGE-NEXT:  movk [[REG]], #8699, lsl #32
 ; LARGE-NEXT:  movk [[REG]], #16393, lsl #48
 ; LARGE-NEXT:  fmov d0, [[REG]]
+; TINY-LABEL: check_double2
+; TINY:       adr     x[[REG:[0-9]+]], .LCPI3_0
+; TINY-NEXT:  ldr     d0, [x[[REG]]]
 define double @check_double2() {
   ret double 3.1415926535897931159979634685441851615905761718750
 }

llvm/trunk/test/CodeGen/AArch64/jump-table.ll

 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
 ; RUN: llc -code-model=large -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-LARGE %s
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -relocation-model=pic -aarch64-enable-atomic-cfg-tidy=0 -o - %s | FileCheck --check-prefix=CHECK-PIC %s
+; RUN: llc -code-model=tiny -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-TINY %s
 
 define i32 @test_jumptable(i32 %in) {
 ; CHECK: test_jumptable
 
   switch i32 %in, label %def [
     i32 0, label %lbl1
     i32 1, label %lbl2
     i32 2, label %lbl3

 ; CHECK-LARGE: br [[DEST]]
 
 ; CHECK-PIC: adrp [[JTPAGE:x[0-9]+]], .LJTI0_0
 ; CHECK-PIC: add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI0_0
 ; CHECK-PIC: ldrsw [[DEST:x[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #2]
 ; CHECK-PIC: add [[TABLE:x[0-9]+]], [[DEST]], x[[JT]]
 ; CHECK-PIC: br [[TABLE]]
 
+; CHECK-TINY: adr x[[JT:[0-9]+]], .LJTI0_0
+; CHECK-TINY: ldr [[DEST:x[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #3]
+; CHECK-TINY: br [[DEST]]
+
 def:
   ret i32 0
 
 lbl1:
   ret i32 1
 
 lbl2:
   ret i32 2

llvm/trunk/test/CodeGen/AArch64/literal_pools_float.ll

 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -mcpu=cyclone | FileCheck %s
 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -code-model=large -mcpu=cyclone | FileCheck --check-prefix=CHECK-LARGE %s
+; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-none-eabi -code-model=tiny -mcpu=cyclone | FileCheck --check-prefix=CHECK-TINY %s
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -code-model=large -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP-LARGE %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-none-eabi -code-model=tiny -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP-TINY %s
 
 @varfloat = global float 0.0
 @vardouble = global double 0.0
 
 define void @floating_lits() {
 ; CHECK-LABEL: floating_lits:
 
   %floatval = load float, float* @varfloat
   %newfloat = fadd float %floatval, 128.0
 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]]
 ; CHECK: ldr [[LIT128:s[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
 ; CHECK-NOFP-NOT: ldr {{s[0-9]+}},
 
+; CHECK-TINY: adr x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]]
+; CHECK-TINY: ldr [[LIT128:s[0-9]+]], [x[[LITBASE]]]
+; CHECK-NOFP-TINY-NOT: ldr {{s[0-9]+}},
+
 ; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g0_nc:[[CURLIT:.LCPI[0-9]+_[0-9]+]]
 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]]
 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g3:[[CURLIT]]
 ; CHECK-LARGE: ldr {{s[0-9]+}}, [x[[LITADDR]]]
 ; CHECK-LARGE: fadd
 ; CHECK-NOFP-LARGE-NOT: ldr {{s[0-9]+}},
 ; CHECK-NOFP-LARGE-NOT: fadd
 
   store float %newfloat, float* @varfloat
 
   %doubleval = load double, double* @vardouble
   %newdouble = fadd double %doubleval, 129.0
 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]]
 ; CHECK: ldr [[LIT129:d[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
 ; CHECK-NOFP-NOT: ldr {{d[0-9]+}},
 ; CHECK-NOFP-NOT: fadd
 
+; CHECK-TINY: adr x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]]
+; CHECK-TINY: ldr [[LIT129:d[0-9]+]], [x[[LITBASE]]]
+; CHECK-NOFP-TINY-NOT: ldr {{d[0-9]+}},
+; CHECK-NOFP-TINY-NOT: fadd
+
 ; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g0_nc:[[CURLIT:.LCPI[0-9]+_[0-9]+]]
 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]]
 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g3:[[CURLIT]]
 ; CHECK-LARGE: ldr {{d[0-9]+}}, [x[[LITADDR]]]
 ; CHECK-NOFP-LARGE-NOT: ldr {{d[0-9]+}},
 
   store double %newdouble, double* @vardouble
 
   ret void
 }

llvm/trunk/test/CodeGen/AArch64/tiny_model.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny -fast-isel < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny -global-isel < %s | FileCheck %s --check-prefix=CHECK-GLOBISEL
+; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny -relocation-model=pic < %s | FileCheck %s --check-prefix=CHECK-PIC
+; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny -relocation-model=pic -fast-isel < %s | FileCheck %s --check-prefix=CHECK-PIC
+; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny -relocation-model=pic -global-isel < %s | FileCheck %s --check-prefix=CHECK-PIC-GLOBISEL
+
+; Note fast-isel tests here will fall back to isel
+
+@src = external local_unnamed_addr global [65536 x i8], align 1
+@dst = external global [65536 x i8], align 1
+@ptr = external local_unnamed_addr global i8*, align 8
+
+define void @foo1() {
+; CHECK-LABEL: foo1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adr x8, src
+; CHECK-NEXT:    ldrb w8, [x8]
+; CHECK-NEXT:    adr x9, dst
+; CHECK-NEXT:    strb w8, [x9]
+; CHECK-NEXT:    ret
+;
+; CHECK-GLOBISEL-LABEL: foo1:
+; CHECK-GLOBISEL:       // %bb.0: // %entry
+; CHECK-GLOBISEL-NEXT:    adr x8, src
+; CHECK-GLOBISEL-NEXT:    ldrb w8, [x8]
+; CHECK-GLOBISEL-NEXT:    adr x9, dst
+; CHECK-GLOBISEL-NEXT:    strb w8, [x9]
+; CHECK-GLOBISEL-NEXT:    ret
+;
+; CHECK-PIC-LABEL: foo1:
+; CHECK-PIC:       // %bb.0: // %entry
+; CHECK-PIC-NEXT:    ldr x8, :got:src
+; CHECK-PIC-NEXT:    ldrb w8, [x8]
+; CHECK-PIC-NEXT:    ldr x9, :got:dst
+; CHECK-PIC-NEXT:    strb w8, [x9]
+; CHECK-PIC-NEXT:    ret
+;
+; CHECK-PIC-GLOBISEL-LABEL: foo1:
+; CHECK-PIC-GLOBISEL:       // %bb.0: // %entry
+; CHECK-PIC-GLOBISEL-NEXT:    ldr x8, :got:src
+; CHECK-PIC-GLOBISEL-NEXT:    ldrb w8, [x8]
+; CHECK-PIC-GLOBISEL-NEXT:    ldr x9, :got:dst
+; CHECK-PIC-GLOBISEL-NEXT:    strb w8, [x9]
+; CHECK-PIC-GLOBISEL-NEXT:    ret
+entry:
+  %0 = load i8, i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @src, i64 0, i64 0), align 1
+  store i8 %0, i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @dst, i64 0, i64 0), align 1
+  ret void
+}
+
+define void @foo2() {
+; CHECK-LABEL: foo2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adr x8, ptr
+; CHECK-NEXT:    adr x9, dst
+; CHECK-NEXT:    str x9, [x8]
+; CHECK-NEXT:    ret
+;
+; CHECK-GLOBISEL-LABEL: foo2:
+; CHECK-GLOBISEL:       // %bb.0: // %entry
+; CHECK-GLOBISEL-NEXT:    adr x8, dst
+; CHECK-GLOBISEL-NEXT:    adr x9, ptr
+; CHECK-GLOBISEL-NEXT:    str x8, [x9]
+; CHECK-GLOBISEL-NEXT:    ret
+;
+; CHECK-PIC-LABEL: foo2:
+; CHECK-PIC:       // %bb.0: // %entry
+; CHECK-PIC-NEXT:    ldr x8, :got:ptr
+; CHECK-PIC-NEXT:    ldr x9, :got:dst
+; CHECK-PIC-NEXT:    str x9, [x8]
+; CHECK-PIC-NEXT:    ret
+;
+; CHECK-PIC-GLOBISEL-LABEL: foo2:
+; CHECK-PIC-GLOBISEL:       // %bb.0: // %entry
+; CHECK-PIC-GLOBISEL-NEXT:    ldr x8, :got:dst
+; CHECK-PIC-GLOBISEL-NEXT:    ldr x9, :got:ptr
+; CHECK-PIC-GLOBISEL-NEXT:    str x8, [x9]
+; CHECK-PIC-GLOBISEL-NEXT:    ret
+entry:
+  store i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @dst, i64 0, i64 0), i8** @ptr, align 8
+  ret void
+}
+
+define void @foo3() {
+; FIXME: Needn't adr ptr
+;
+; CHECK-LABEL: foo3:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adr x8, src
+; CHECK-NEXT:    adr x9, ptr
+; CHECK-NEXT:    ldrb w8, [x8]
+; CHECK-NEXT:    ldr x9, [x9]
+; CHECK-NEXT:    strb w8, [x9]
+; CHECK-NEXT:    ret
+;
+; CHECK-GLOBISEL-LABEL: foo3:
+; CHECK-GLOBISEL:       // %bb.0: // %entry
+; CHECK-GLOBISEL-NEXT:    adr x8, src
+; CHECK-GLOBISEL-NEXT:    adr x9, ptr
+; CHECK-GLOBISEL-NEXT:    ldrb w8, [x8]
+; CHECK-GLOBISEL-NEXT:    ldr x9, [x9]
+; CHECK-GLOBISEL-NEXT:    strb w8, [x9]
+; CHECK-GLOBISEL-NEXT:    ret
+;
+; CHECK-PIC-LABEL: foo3:
+; CHECK-PIC:       // %bb.0: // %entry
+; CHECK-PIC-NEXT:    ldr x8, :got:src
+; CHECK-PIC-NEXT:    ldr x9, :got:ptr
+; CHECK-PIC-NEXT:    ldrb w8, [x8]
+; CHECK-PIC-NEXT:    ldr x9, [x9]
+; CHECK-PIC-NEXT:    strb w8, [x9]
+; CHECK-PIC-NEXT:    ret
+;
+; CHECK-PIC-GLOBISEL-LABEL: foo3:
+; CHECK-PIC-GLOBISEL:       // %bb.0: // %entry
+; CHECK-PIC-GLOBISEL-NEXT:    ldr x8, :got:src
+; CHECK-PIC-GLOBISEL-NEXT:    ldr x9, :got:ptr
+; CHECK-PIC-GLOBISEL-NEXT:    ldrb w8, [x8]
+; CHECK-PIC-GLOBISEL-NEXT:    ldr x9, [x9]
+; CHECK-PIC-GLOBISEL-NEXT:    strb w8, [x9]
+; CHECK-PIC-GLOBISEL-NEXT:    ret
+entry:
+  %0 = load i8, i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @src, i64 0, i64 0), align 1
+  %1 = load i8*, i8** @ptr, align 8
+  store i8 %0, i8* %1, align 1
+  ret void
+}
+
+@lsrc = internal global i8 0, align 4
+@ldst = internal global i8 0, align 4
+@lptr = internal global i8* null, align 8
+
+define void @bar1() {
+; CHECK-LABEL: bar1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adr x8, lsrc
+; CHECK-NEXT:    ldrb w8, [x8]
+; CHECK-NEXT:    adr x9, ldst
+; CHECK-NEXT:    strb w8, [x9]
+; CHECK-NEXT:    ret
+;
+; CHECK-GLOBISEL-LABEL: bar1:
+; CHECK-GLOBISEL:       // %bb.0: // %entry
+; CHECK-GLOBISEL-NEXT:    adr x8, lsrc
+; CHECK-GLOBISEL-NEXT:    ldrb w8, [x8]
+; CHECK-GLOBISEL-NEXT:    adr x9, ldst
+; CHECK-GLOBISEL-NEXT:    strb w8, [x9]
+; CHECK-GLOBISEL-NEXT:    ret
+;
+; CHECK-PIC-LABEL: bar1:
+; CHECK-PIC:       // %bb.0: // %entry
+; CHECK-PIC-NEXT:    adr x8, lsrc
+; CHECK-PIC-NEXT:    ldrb w8, [x8]
+; CHECK-PIC-NEXT:    adr x9, ldst
+; CHECK-PIC-NEXT:    strb w8, [x9]
+; CHECK-PIC-NEXT:    ret
+;
+; CHECK-PIC-GLOBISEL-LABEL: bar1:
+; CHECK-PIC-GLOBISEL:       // %bb.0: // %entry
+; CHECK-PIC-GLOBISEL-NEXT:    adr x8, lsrc
+; CHECK-PIC-GLOBISEL-NEXT:    ldrb w8, [x8]
+; CHECK-PIC-GLOBISEL-NEXT:    adr x9, ldst
+; CHECK-PIC-GLOBISEL-NEXT:    strb w8, [x9]
+; CHECK-PIC-GLOBISEL-NEXT:    ret
+entry:
+  %0 = load i8, i8* @lsrc, align 4
+  store i8 %0, i8* @ldst, align 4
+  ret void
+}
+
+define void @bar2() {
+; CHECK-LABEL: bar2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adr x8, lptr
+; CHECK-NEXT:    adr x9, ldst
+; CHECK-NEXT:    str x9, [x8]
+; CHECK-NEXT:    ret
+;
+; CHECK-GLOBISEL-LABEL: bar2:
+; CHECK-GLOBISEL:       // %bb.0: // %entry
+; CHECK-GLOBISEL-NEXT:    adr x8, ldst
+; CHECK-GLOBISEL-NEXT:    adr x9, lptr
+; CHECK-GLOBISEL-NEXT:    str x8, [x9]
+; CHECK-GLOBISEL-NEXT:    ret
+;
+; CHECK-PIC-LABEL: bar2:
+; CHECK-PIC:       // %bb.0: // %entry
+; CHECK-PIC-NEXT:    adr x8, lptr
+; CHECK-PIC-NEXT:    adr x9, ldst
+; CHECK-PIC-NEXT:    str x9, [x8]
+; CHECK-PIC-NEXT:    ret
+;
+; CHECK-PIC-GLOBISEL-LABEL: bar2:
+; CHECK-PIC-GLOBISEL:       // %bb.0: // %entry
+; CHECK-PIC-GLOBISEL-NEXT:    adr x8, ldst
+; CHECK-PIC-GLOBISEL-NEXT:    adr x9, lptr
+; CHECK-PIC-GLOBISEL-NEXT:    str x8, [x9]
+; CHECK-PIC-GLOBISEL-NEXT:    ret
+entry:
+  store i8* @ldst, i8** @lptr, align 8
+  ret void
+}
+
+define void @bar3() {
+; FIXME: Needn't adr lptr
+;
+; CHECK-LABEL: bar3:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adr x8, lsrc
+; CHECK-NEXT:    adr x9, lptr
+; CHECK-NEXT:    ldrb w8, [x8]
+; CHECK-NEXT:    ldr x9, [x9]
+; CHECK-NEXT:    strb w8, [x9]
+; CHECK-NEXT:    ret
+;
+; CHECK-GLOBISEL-LABEL: bar3:
+; CHECK-GLOBISEL:       // %bb.0: // %entry
+; CHECK-GLOBISEL-NEXT:    adr x8, lsrc
+; CHECK-GLOBISEL-NEXT:    adr x9, lptr
+; CHECK-GLOBISEL-NEXT:    ldrb w8, [x8]
+; CHECK-GLOBISEL-NEXT:    ldr x9, [x9]
+; CHECK-GLOBISEL-NEXT:    strb w8, [x9]
+; CHECK-GLOBISEL-NEXT:    ret
+;
+; CHECK-PIC-LABEL: bar3:
+; CHECK-PIC:       // %bb.0: // %entry
+; CHECK-PIC-NEXT:    adr x8, lsrc
+; CHECK-PIC-NEXT:    adr x9, lptr
+; CHECK-PIC-NEXT:    ldrb w8, [x8]
+; CHECK-PIC-NEXT:    ldr x9, [x9]
+; CHECK-PIC-NEXT:    strb w8, [x9]
+; CHECK-PIC-NEXT:    ret
+;
+; CHECK-PIC-GLOBISEL-LABEL: bar3:
+; CHECK-PIC-GLOBISEL:       // %bb.0: // %entry
+; CHECK-PIC-GLOBISEL-NEXT:    adr x8, lsrc
+; CHECK-PIC-GLOBISEL-NEXT:    adr x9, lptr
+; CHECK-PIC-GLOBISEL-NEXT:    ldrb w8, [x8]
+; CHECK-PIC-GLOBISEL-NEXT:    ldr x9, [x9]
+; CHECK-PIC-GLOBISEL-NEXT:    strb w8, [x9]
+; CHECK-PIC-GLOBISEL-NEXT:    ret
+entry:
+  %0 = load i8, i8* @lsrc, align 4
+  %1 = load i8*, i8** @lptr, align 8
+  store i8 %0, i8* %1, align 1
+  ret void
+}
+
+
+@lbsrc = internal global [65536 x i8] zeroinitializer, align 4
+@lbdst = internal global [65536 x i8] zeroinitializer, align 4
+
+define void @baz1() {
+; CHECK-LABEL: baz1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adr x8, lbsrc
+; CHECK-NEXT:    ldrb w8, [x8]
+; CHECK-NEXT:    adr x9, lbdst
+; CHECK-NEXT:    strb w8, [x9]
+; CHECK-NEXT:    ret
+;
+; CHECK-GLOBISEL-LABEL: baz1:
+; CHECK-GLOBISEL:       // %bb.0: // %entry
+; CHECK-GLOBISEL-NEXT:    adr x8, lbsrc
+; CHECK-GLOBISEL-NEXT:    ldrb w8, [x8]
+; CHECK-GLOBISEL-NEXT:    adr x9, lbdst
+; CHECK-GLOBISEL-NEXT:    strb w8, [x9]
+; CHECK-GLOBISEL-NEXT:    ret
+;
+; CHECK-PIC-LABEL: baz1:
+; CHECK-PIC:       // %bb.0: // %entry
+; CHECK-PIC-NEXT:    adr x8, lbsrc
+; CHECK-PIC-NEXT:    ldrb w8, [x8]
+; CHECK-PIC-NEXT:    adr x9, lbdst
+; CHECK-PIC-NEXT:    strb w8, [x9]
+; CHECK-PIC-NEXT:    ret
+;
+; CHECK-PIC-GLOBISEL-LABEL: baz1:
+; CHECK-PIC-GLOBISEL:       // %bb.0: // %entry
+; CHECK-PIC-GLOBISEL-NEXT:    adr x8, lbsrc
+; CHECK-PIC-GLOBISEL-NEXT:    ldrb w8, [x8]
+; CHECK-PIC-GLOBISEL-NEXT:    adr x9, lbdst
+; CHECK-PIC-GLOBISEL-NEXT:    strb w8, [x9]
+; CHECK-PIC-GLOBISEL-NEXT:    ret
+entry:
+  %0 = load i8, i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @lbsrc, i64 0, i64 0), align 4
+  store i8 %0, i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @lbdst, i64 0, i64 0), align 4
+  ret void
+}
+
+define void @baz2() {
+; CHECK-LABEL: baz2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adr x8, lptr
+; CHECK-NEXT:    adr x9, lbdst
+; CHECK-NEXT:    str x9, [x8]
+; CHECK-NEXT:    ret
+;
+; CHECK-GLOBISEL-LABEL: baz2:
+; CHECK-GLOBISEL:       // %bb.0: // %entry
+; CHECK-GLOBISEL-NEXT:    adr x8, lbdst
+; CHECK-GLOBISEL-NEXT:    adr x9, lptr
+; CHECK-GLOBISEL-NEXT:    str x8, [x9]
+; CHECK-GLOBISEL-NEXT:    ret
+;
+; CHECK-PIC-LABEL: baz2:
+; CHECK-PIC:       // %bb.0: // %entry
+; CHECK-PIC-NEXT:    adr x8, lptr
+; CHECK-PIC-NEXT:    adr x9, lbdst
+; CHECK-PIC-NEXT:    str x9, [x8]
+; CHECK-PIC-NEXT:    ret
+;
+; CHECK-PIC-GLOBISEL-LABEL: baz2:
+; CHECK-PIC-GLOBISEL:       // %bb.0: // %entry
+; CHECK-PIC-GLOBISEL-NEXT:    adr x8, lbdst
+; CHECK-PIC-GLOBISEL-NEXT:    adr x9, lptr
+; CHECK-PIC-GLOBISEL-NEXT:    str x8, [x9]
+; CHECK-PIC-GLOBISEL-NEXT:    ret
+entry:
+  store i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @lbdst, i64 0, i64 0), i8** @lptr, align 8
+  ret void
+}
+
+define void @baz3() {
+; FIXME: Needn't adr lptr
+;
+; CHECK-LABEL: baz3:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adr x8, lbsrc
+; CHECK-NEXT:    adr x9, lptr
+; CHECK-NEXT:    ldrb w8, [x8]
+; CHECK-NEXT:    ldr x9, [x9]
+; CHECK-NEXT:    strb w8, [x9]
+; CHECK-NEXT:    ret
+;
+; CHECK-GLOBISEL-LABEL: baz3:
+; CHECK-GLOBISEL:       // %bb.0: // %entry
+; CHECK-GLOBISEL-NEXT:    adr x8, lbsrc
+; CHECK-GLOBISEL-NEXT:    adr x9, lptr
+; CHECK-GLOBISEL-NEXT:    ldrb w8, [x8]
+; CHECK-GLOBISEL-NEXT:    ldr x9, [x9]
+; CHECK-GLOBISEL-NEXT:    strb w8, [x9]
+; CHECK-GLOBISEL-NEXT:    ret
+;
+; CHECK-PIC-LABEL: baz3:
+; CHECK-PIC:       // %bb.0: // %entry
+; CHECK-PIC-NEXT:    adr x8, lbsrc
+; CHECK-PIC-NEXT:    adr x9, lptr
+; CHECK-PIC-NEXT:    ldrb w8, [x8]
+; CHECK-PIC-NEXT:    ldr x9, [x9]
+; CHECK-PIC-NEXT:    strb w8, [x9]
+; CHECK-PIC-NEXT:    ret
+;
+; CHECK-PIC-GLOBISEL-LABEL: baz3:
+; CHECK-PIC-GLOBISEL:       // %bb.0: // %entry
+; CHECK-PIC-GLOBISEL-NEXT:    adr x8, lbsrc
+; CHECK-PIC-GLOBISEL-NEXT:    adr x9, lptr
+; CHECK-PIC-GLOBISEL-NEXT:    ldrb w8, [x8]
+; CHECK-PIC-GLOBISEL-NEXT:    ldr x9, [x9]
+; CHECK-PIC-GLOBISEL-NEXT:    strb w8, [x9]
+; CHECK-PIC-GLOBISEL-NEXT:    ret
+entry:
+  %0 = load i8, i8* getelementptr inbounds ([65536 x i8], [65536 x i8]* @lbsrc, i64 0, i64 0), align 4
+  %1 = load i8*, i8** @lptr, align 8
+  store i8 %0, i8* %1, align 1
+  ret void
+}
+
+
+declare void @func(...)
+
+define i8* @externfuncaddr() {
+; CHECK-LABEL: externfuncaddr:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adr x0, func
+; CHECK-NEXT:    ret
+;
+; CHECK-GLOBISEL-LABEL: externfuncaddr:
+; CHECK-GLOBISEL:       // %bb.0: // %entry
+; CHECK-GLOBISEL-NEXT:    adr x0, func
+; CHECK-GLOBISEL-NEXT:    ret
+;
+; CHECK-PIC-LABEL: externfuncaddr:
+; CHECK-PIC:       // %bb.0: // %entry
+; CHECK-PIC-NEXT:    ldr x0, :got:func
+; CHECK-PIC-NEXT:    ret
+;
+; CHECK-PIC-GLOBISEL-LABEL: externfuncaddr:
+; CHECK-PIC-GLOBISEL:       // %bb.0: // %entry
+; CHECK-PIC-GLOBISEL-NEXT:    ldr x0, :got:func
+; CHECK-PIC-GLOBISEL-NEXT:    ret
+entry:
+      ret i8* bitcast (void (...)* @func to i8*)
+}
+
+define i8* @localfuncaddr() {
+; CHECK-LABEL: localfuncaddr:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adr x0, externfuncaddr
+; CHECK-NEXT:    ret
+;
+; CHECK-GLOBISEL-LABEL: localfuncaddr:
+; CHECK-GLOBISEL:       // %bb.0: // %entry
+; CHECK-GLOBISEL-NEXT:    adr x0, externfuncaddr
+; CHECK-GLOBISEL-NEXT:    ret
+;
+; CHECK-PIC-LABEL: localfuncaddr:
+; CHECK-PIC:       // %bb.0: // %entry
+; CHECK-PIC-NEXT:    ldr x0, :got:externfuncaddr
+; CHECK-PIC-NEXT:    ret
+;
+; CHECK-PIC-GLOBISEL-LABEL: localfuncaddr:
+; CHECK-PIC-GLOBISEL:       // %bb.0: // %entry
+; CHECK-PIC-GLOBISEL-NEXT:    ldr x0, :got:externfuncaddr
+; CHECK-PIC-GLOBISEL-NEXT:    ret
+entry:
+      ret i8* bitcast (i8* ()* @externfuncaddr to i8*)
+}
+

llvm/trunk/test/CodeGen/AArch64/tiny_supported.ll

+; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny < %s 2>&1 | FileCheck %s
+; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-eabi -code-model=tiny < %s 2>&1 | FileCheck %s
+; RUN: not llc -verify-machineinstrs -o - -mtriple=arm64-apple-darwin -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY
+; RUN: not llc -verify-machineinstrs -o - -mtriple=arm64-apple-ios -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY
+; RUN: not llc -verify-machineinstrs -o - -mtriple=aarch64-unknown-windows-msvc -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY
+
+; CHECK-NOT:   tiny code model is only supported on ELF
+; CHECK-LABEL:   foo
+; NOTINY:   tiny code model is only supported on ELF
+
+define void @foo() {
+  ret void
+}

llvm/trunk/test/MC/AArch64/basic-a64-diagnostics.s

 // CHECK-ERROR-NEXT:         movk w23, #:abs_g2_s:sym
 // CHECK-ERROR-NEXT:                   ^
 
 //------------------------------------------------------------------------------
 // PC-relative addressing
 //------------------------------------------------------------------------------
 
         adr sp, loc             // expects xzr
+        adr x0, :got:loc        // bad relocation type
         adrp x3, #20            // Immediate unaligned
         adrp w2, loc            // 64-bit register needed
+        adrp x5, :got_lo12:loc  // bad relocation type
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR-NEXT:         adr sp, loc
 // CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: error: unexpected adr label
+// CHECK-ERROR-NEXT:         adr x0, :got:loc
+// CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected label or encodable integer pc offset
 // CHECK-ERROR-NEXT:         adrp x3, #20
 // CHECK-ERROR-NEXT:                  ^
 // CHECK-ERROR-NEXT: error: invalid operand for instruction
 // CHECK-ERROR-NEXT:         adrp w2, loc
 // CHECK-ERROR-NEXT:              ^
+// CHECK-ERROR-NEXT: error: page or gotpage label reference expected
+// CHECK-ERROR-NEXT:         adrp x5, :got_lo12:loc
+// CHECK-ERROR-NEXT:             ^
 
         adr x9, #1048576
         adr x2, #-1048577
         adrp x9, #4294967296
         adrp x20, #-4294971392
 // CHECK-ERROR: error: expected label or encodable integer pc offset
 // CHECK-ERROR-NEXT:         adr x9, #1048576
 // CHECK-ERROR-NEXT:                 ^