[WebAssembly] Move/clone DBG_VALUE during WebAssemblyRegStackify pass

[yurydelendik]

Summary

The MoveForSingleUse or MoveAndTeeForMultiUse functions move wasm instructions,
however DBG_VALUE stay unchanged -- moving or cloning these.

[mattd]

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

472

I'm wondering if we should check that MI is nullptr here, or maybe assert? I know parent MI's can be initialized to nullptr and can be cleared, but I'm not sure if that would ever be the case at this point.

539

Minor nit: I'd suggest running clang-format here, usually formals split between two lines end up following the opening parenthesis, lining up with each other.

595

I would reword this to be imperative: "Move or clone corresponding DBG_VALUEs to the 'Insert' location.

[yurydelendik]

Changes:

• add asserts for MI
• run clang-format
• comment rewording

[yurydelendik]

Fix DBG_VALUE instruction cloning.

[mattd]

Thanks Yury, it looks like you addressed my immediate concerns. I didn't see anything glaringly wrong, when I looked at the original patch. You should add a few reviewers and tag this as "debug-info" by editing the revision and updating the "Tags" field. That should get your patch a bit more exposure. Do you happen to have a smaller/reduced reproducer? I'm wondering how much of the test can be trimmed down, for instance, you declared a variable 't' but it's unused.

[yurydelendik]

• Reducing the test case further: remove attributes, lifetime markers and non-"a" variable metadata.
• Add test for MoveAndTeeForMultiUse changes

[yurydelendik]

Do you happen to have a smaller/reduced reproducer?

It is really hard for me to create reduced test case. I modified the test cases to remove some metadata per https://reviews.llvm.org/D48994#1164085 recommendation.

[yurydelendik]

Rebased on top of D48994

[dschuff]

Otherwise LGTM, although I'm not an expert in DebugInfo either.

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

470

I think this can just be something like for (const auto &Op : MRI.reg_operands(Reg)) (and below)

[yurydelendik]

Use for (const auto &Op :

[yurydelendik]

Rebase (adjust test/DebugInfo/WebAssembly/dbg-value-move.ll)

[dschuff]

otherwise LGTM

test/DebugInfo/WebAssembly/dbg-value-move.ll

11

Was this generated with any optimization flags in clang? (maybe just also add the clang command line as well as the sources in these files?)

[yurydelendik]

Add instructions how to regenerate dbg-value-move*.ll files

[jgravelle-google]

This seems to have broken some of the emscripten tests (binaryen2.test_poppler and binaryen2.test_the_bullet) that we run on the wasm waterfall:
https://logs.chromium.org/v/?s=chromium%2Fbb%2Fclient.wasm.llvm%2Flinux%2F35933%2F%2B%2Frecipes%2Fsteps%2FExecute_emscripten_testsuite__emwasm_%2F0%2Fstdout

[yurydelendik]

In D49034#1245913, @jgravelle-google wrote:

This seems to have broken some of the emscripten tests (binaryen2.test_poppler and binaryen2.test_the_bullet) that we run on the wasm waterfall:
https://logs.chromium.org/v/?s=chromium%2Fbb%2Fclient.wasm.llvm%2Flinux%2F35933%2F%2B%2Frecipes%2Fsteps%2FExecute_emscripten_testsuite__emwasm_%2F0%2Fstdout

Looks like MRI.hasOneUse checks also DBG_VALUE register usages (that causes assert to fail). I need to check if use_nodbg_begin() will fix the issue. (FWIW OneUseDominatesOtherUses uses xx_nodbg_yyy operations in some places)

[sbc100]

We we revert this or get it fixed? Its currently breaking the wasm waterfall: https://wasm-stat.us/console

[yurydelendik]

In D49034#1246966, @sbc100 wrote:

We we revert this or get it fixed? Its currently breaking the wasm waterfall: https://wasm-stat.us/console

The fix just to pass tests is

diff --git a/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
index 5b6a91dbc9d..6583057e7fb 100644
--- a/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
+++ b/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
@@ -428,8 +428,10 @@ static bool OneUseDominatesOtherUses(unsigned Reg, const MachineOperand &OneUse,
         if (!TargetRegisterInfo::isVirtualRegister(DefReg) ||
             !MFI.isVRegStackified(DefReg))
           return false;
-        assert(MRI.hasOneUse(DefReg));
-        const MachineOperand &NewUse = *MRI.use_begin(DefReg);
+        auto It = MRI.use_nodbg_begin(DefReg);
+        assert(It != MRI.use_nodbg_end());
+        const MachineOperand &NewUse = *It;
+        assert(++It == MRI.use_nodbg_end());
         const MachineInstr *NewUseInst = NewUse.getParent();
         if (NewUseInst == OneUseInst) {
           if (&OneUse > &NewUse)

It will take care of WebAssemblyRegStackify, but it will be nice to see it at MRI::hasOneUse.

Let me know if I need to backup entire patch and attempt to fix hasOneUse first.

[dschuff]

Not exactly sure what you mean; do you mean that hasOneUse should return true if there is only one non-debug use? That makes sense, maybe it should be hasOneNonDbgUse or something. But please either commit this fix and then follow up, or revert this patch and re-apply with hasOneUse fixed.

[jgravelle-google]

This still breaks two emscripten tests, test_the_bullet and test_poppler
In particular, it creates a wasm module that fails to typecheck, seemingly because of a reordering of instructions. Commenting out MoveDebugValues and CloneDebugValues is needed to avoid this.
The simplest reproduction I can find is:

wasm32-clang++ $EMSCRIPTEN/tests/bullet/src/BulletCollision/NarrowPhaseCollision/btPersistentManifold.cpp \
  -D__EMSCRIPTEN__=1 \
  -I$EMSCRIPTEN/tests/bullet/src/ \
  -nostdlib \
  -Xclang -nostdsysteminc \
  -Xclang -isystem$EMSCRIPTEN/system/include/libc \
  -Xlinker --no-entry \
  -Xlinker --allow-undefined \
  -O2 -g -o test.wasm

where EMSCRIPTEN is the path to emscripten's main directory (containing emcc.py et al). This creates a test.wasm that is invalid, quickly verifiable with wabt's wasm2wat

[alexcrichton]

I think this has unfortunately caused a regression :( -- https://bugs.llvm.org/show_bug.cgi?id=39158

[alexcrichton]

er sorry, looks like some problems may already be known!

[jgravelle-google]

Forgot to add, need to add __attribute__((used, visibility("default"))) to btPersistentManifold::clearUserCache in that cpp file

[aheejin]

It looks DBG_VALUE instruction handling in RegStackify has several problems.

1. MoveDebugValues and UpdateDebugValuesReg do not seem to consider the case where there are multiple defs to a single register within a BB. Currently they treat all DBG_VALUE instruction to a register as a group and move / update them together whenever any one of the definitions of the register in a BB is stackified. A sample test case with multiple defs within a BB that fails is attached in PR40209.

2-3 are written inline.

I also filed PR40209 with the same contents for easy tracking.

llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

486 ↗

(On Diff #166969)

Here Op.setReg(NewReg) modifies the iterator MRI.reg_operands(Reg) while traversing it. So this ends up hitting only the first element and bailing out. This function has problems even without this bug because of the 1 above though.

542 ↗

(On Diff #166969)

This function does not consider a case that an instruction to be rematerialized is in another BB. Even though RegStackify mostly work within a BB, when a def is trivially rematerializable, i.e., const_i32 instruction, that instruction can be another BB and can be copied to this BB. But CloneDebugValues limit the search within this BB by MI->getParent() == &MBB clause, so in that case the debug value for the rematerialized instruction will not be cloned. A test case can be made trivially, so I'm not gonna attach an mir file for that, but it should look like this:

bb1:
  %3 = const_i32 3 ; This is trivially rematerializable
  ...

bb2:
  ...
  use %3

lib/CodeGen/LiveInterval.cpp

void ConnectedVNInfoEqClasses::Distribute(LiveInterval &LI, LiveInterval *LIV[],
                                           MachineRegisterInfo &MRI) {
   // Rewrite instructions.
   for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LI.reg),
        RE = MRI.reg_end(); RI != RE;) {
     MachineOperand &MO = *RI;
     MachineInstr *MI = RI->getParent();
     ++RI;
     // DBG_VALUE instructions don't have slot indexes, so get the index of the
-    // instruction before them.
+    // instruction before them. The value is defined there too.
     // Normally, DBG_VALUE instructions are removed before this function is
     // called, but it is not a requirement.
     SlotIndex Idx;
-    if (MI->isDebugValue())
+    bool ValueIn; // TODO(yd) land in D48994
+    if (MI->isDebugValue()) {
       Idx = LIS.getSlotIndexes()->getIndexBefore(*MI);
-    else
+      ValueIn = false;
+    } else {
       Idx = LIS.getInstructionIndex(*MI);
+      ValueIn = MO.readsReg();
+    }
     LiveQueryResult LRQ = LI.Query(Idx);
-    const VNInfo *VNI = MO.readsReg() ? LRQ.valueIn() : LRQ.valueDefined();
+    const VNInfo *VNI = ValueIn ? LRQ.valueIn() : LRQ.valueDefined();
     // In the case of an <undef> use that isn't tied to any def, VNI will be
     // NULL. If the use is tied to a def, VNI will be the defined value.
     if (!VNI)
       continue;
     if (unsigned EqClass = getEqClass(VNI))
       MO.setReg(LIV[EqClass-1]->reg);
   }
 

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

 ///
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" // for WebAssembly::ARGUMENT_*
 #include "WebAssembly.h"
 #include "WebAssemblyMachineFunctionInfo.h"
 #include "WebAssemblySubtarget.h"
 #include "WebAssemblyUtilities.h"
+#include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/CodeGen/LiveIntervals.h"
 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/Passes.h"

 // Shrink LI to its uses, cleaning up LI.
 static void ShrinkToUses(LiveInterval &LI, LiveIntervals &LIS) {
   if (LIS.shrinkToUses(&LI)) {
     SmallVector<LiveInterval*, 4> SplitLIs;
     LIS.splitSeparateComponents(LI, SplitLIs);
   }
 }
 
+static void MoveDebugValues(unsigned Reg, MachineInstr *Insert,
+                            MachineBasicBlock &MBB, MachineRegisterInfo &MRI) {
+  for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg),
+                                         RE = MRI.reg_end();
+       RI != RE; ++RI) {
+    MachineInstr *MI = RI->getParent();
+    assert(MI != nullptr);
+    if (MI->isDebugValue() && MI->getParent() == &MBB)
+      MBB.splice(Insert, &MBB, MI);
+  }
+}
+
+static void UpdateDebugValuesReg(unsigned Reg, unsigned NewReg,
+                                 MachineBasicBlock &MBB,
+                                 MachineRegisterInfo &MRI) {
+  for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg),
+                                         RE = MRI.reg_end();
+       RI != RE; ++RI) {
+    MachineOperand &MO = *RI;
+    MachineInstr *MI = RI->getParent();
+    assert(MI != nullptr);
+    if (MI->isDebugValue() && MI->getParent() == &MBB)
+      MO.setReg(NewReg);
+  }
+}
+
 /// A single-use def in the same block with no intervening memory or register
 /// dependencies; move the def down and nest it with the current instruction.
 static MachineInstr *MoveForSingleUse(unsigned Reg, MachineOperand& Op,
                                       MachineInstr *Def,
                                       MachineBasicBlock &MBB,
                                       MachineInstr *Insert, LiveIntervals &LIS,
                                       WebAssemblyFunctionInfo &MFI,
                                       MachineRegisterInfo &MRI) {
   LLVM_DEBUG(dbgs() << "Move for single use: "; Def->dump());
 
   MBB.splice(Insert, &MBB, Def);
+  MoveDebugValues(Reg, Insert, MBB, MRI);
   LIS.handleMove(*Def);
 
   if (MRI.hasOneDef(Reg) && MRI.hasOneUse(Reg)) {
     // No one else is using this register for anything so we can just stackify
     // it in place.
     MFI.stackifyVReg(Reg);
   } else {
     // The register may have unrelated uses or defs; create a new register for
     // just our one def and use so that we can stackify it.
     unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg));
     Def->getOperand(0).setReg(NewReg);
     Op.setReg(NewReg);
+    UpdateDebugValuesReg(Reg, NewReg, MBB, MRI);
 
     // Tell LiveIntervals about the new register.
     LIS.createAndComputeVirtRegInterval(NewReg);
 
     // Tell LiveIntervals about the changes to the old register.
     LiveInterval &LI = LIS.getInterval(Reg);
     LI.removeSegment(LIS.getInstructionIndex(*Def).getRegSlot(),
                      LIS.getInstructionIndex(*Op.getParent()).getRegSlot(),
                      /*RemoveDeadValNo=*/true);
 
     MFI.stackifyVReg(NewReg);
 
     LLVM_DEBUG(dbgs() << " - Replaced register: "; Def->dump());
   }
 
   ImposeStackOrdering(Def);
   return Def;
 }
 
+static void CloneDebugValues(unsigned Reg, MachineInstr *Insert,
+                             unsigned TargetReg, MachineBasicBlock &MBB,
+                             MachineRegisterInfo &MRI) {
+  SmallPtrSet<MachineInstr *, 4> Instrs;
+  for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg),
+                                         RE = MRI.reg_end();
+       RI != RE; ++RI) {
+    MachineInstr *MI = RI->getParent();
+    assert(MI != nullptr);
+    if (MI->isDebugValue() && MI->getParent() == &MBB &&
+        Instrs.find(MI) == Instrs.end())
+      Instrs.insert(MI);
+  }
+  MachineFunction &MF = *MBB.getParent();
+  for (const auto &MI : Instrs) {
+    MachineInstr *Clone =
+        BuildMI(MBB, Insert, MI->getDebugLoc(), MI->getDesc());
+    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+      MachineOperand MO(MI->getOperand(i));
+      if (MO.isReg() && MO.getReg() == Reg)
+        MO.setReg(TargetReg);
+      Clone->addOperand(MF, MO);
+    }
+    LLVM_DEBUG(dbgs() << " - - Cloned DBG_VALUE: "; Clone->dump());
+  }
+}
+
 /// A trivially cloneable instruction; clone it and nest the new copy with the
 /// current instruction.
 static MachineInstr *RematerializeCheapDef(
     unsigned Reg, MachineOperand &Op, MachineInstr &Def, MachineBasicBlock &MBB,
     MachineBasicBlock::instr_iterator Insert, LiveIntervals &LIS,
     WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI,
     const WebAssemblyInstrInfo *TII, const WebAssemblyRegisterInfo *TRI) {
   LLVM_DEBUG(dbgs() << "Rematerializing cheap def: "; Def.dump());
static MachineInstr *RematerializeCheapDef(
   bool IsDead = MRI.use_empty(Reg);
   if (!IsDead) {
     LiveInterval &LI = LIS.getInterval(Reg);
     ShrinkToUses(LI, LIS);
     IsDead = !LI.liveAt(LIS.getInstructionIndex(Def).getDeadSlot());
   }
 
   // If that was the last use of the original, delete the original.
+  // Move or clone corresponding DBG_VALUEs to the 'Insert' location.
   if (IsDead) {
     LLVM_DEBUG(dbgs() << " - Deleting original\n");
     SlotIndex Idx = LIS.getInstructionIndex(Def).getRegSlot();
     LIS.removePhysRegDefAt(WebAssembly::ARGUMENTS, Idx);
     LIS.removeInterval(Reg);
     LIS.RemoveMachineInstrFromMaps(Def);
     Def.eraseFromParent();
+
+    MoveDebugValues(Reg, &*Insert, MBB, MRI);
+    UpdateDebugValuesReg(Reg, NewReg, MBB, MRI);
+  } else {
+    CloneDebugValues(Reg, &*Insert, NewReg, MBB, MRI);
   }
 
   return Clone;
 }
 
 /// A multiple-use def in the same block with no intervening memory or register
 /// dependencies; move the def down, nest it with the current instruction, and
 /// insert a tee to satisfy the rest of the uses. As an illustration, rewrite

 static MachineInstr *MoveAndTeeForMultiUse(
     unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB,
     MachineInstr *Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI,
     MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII) {
   LLVM_DEBUG(dbgs() << "Move and tee for multi-use:"; Def->dump());
 
   // Move Def into place.
   MBB.splice(Insert, &MBB, Def);
+  MoveDebugValues(Reg, Insert, MBB, MRI);
   LIS.handleMove(*Def);
 
   // Create the Tee and attach the registers.
   const auto *RegClass = MRI.getRegClass(Reg);
   unsigned TeeReg = MRI.createVirtualRegister(RegClass);
   unsigned DefReg = MRI.createVirtualRegister(RegClass);
   MachineOperand &DefMO = Def->getOperand(0);
   MachineInstr *Tee = BuildMI(MBB, Insert, Insert->getDebugLoc(),
                               TII->get(GetTeeOpcode(RegClass)), TeeReg)
                           .addReg(Reg, RegState::Define)
                           .addReg(DefReg, getUndefRegState(DefMO.isDead()));
   Op.setReg(TeeReg);
   DefMO.setReg(DefReg);
   SlotIndex TeeIdx = LIS.InsertMachineInstrInMaps(*Tee).getRegSlot();
   SlotIndex DefIdx = LIS.getInstructionIndex(*Def).getRegSlot();
+  CloneDebugValues(Reg, Tee, DefReg, MBB, MRI);
+  CloneDebugValues(Reg, Insert, TeeReg, MBB, MRI);
 
   // Tell LiveIntervals we moved the original vreg def from Def to Tee.
   LiveInterval &LI = LIS.getInterval(Reg);
   LiveInterval::iterator I = LI.FindSegmentContaining(DefIdx);
   VNInfo *ValNo = LI.getVNInfoAt(DefIdx);
   I->start = TeeIdx;
   ValNo->def = TeeIdx;
   ShrinkToUses(LI, LIS);

test/DebugInfo/WebAssembly/dbg-value-move.ll

+; RUN: llc < %s -print-machineinstrs 2>&1 | FileCheck %s
+
+; CHECK: After WebAssembly Register Stackify:
+; CHECK: bb.3.for.body.for.body_crit_edge:
+; CHECK: [[REG:%[0-9]+]]:i32 = ADD_I32 {{.*}} fib.c:7:7
+; CHECK-NEXT: DBG_VALUE debug-use [[REG]]:i32, debug-use $noreg, !"a", {{.*}} fib.c:5:13
+; CHECK: After WebAssembly Store Results:
+
+; ModuleID = 'fib.bc'
+source_filename = "fib.c"
+; void swap(int* a, int* b);
+; 
+; __attribute__ ((visibility ("default")))
+; int fib(int n) {
+;   int i, t, a = 0, b = 1;
+;   for (i = 0; i < n; i++) {
+;     a += b;
+;     swap(&a, &b);
+;   }
+;   return b;
+; }
+; void _start() {}
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown-wasm"
+
+; Function Attrs: nounwind
+define i32 @fib(i32 %n) local_unnamed_addr #0 !dbg !7 {
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  call void @llvm.dbg.value(metadata i32 %n, metadata !12, metadata !DIExpression()), !dbg !17
+  %0 = bitcast i32* %a to i8*, !dbg !18
+  call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0) #5, !dbg !18
+  call void @llvm.dbg.value(metadata i32 0, metadata !15, metadata !DIExpression()), !dbg !19
+  store i32 0, i32* %a, align 4, !dbg !19, !tbaa !20
+  %1 = bitcast i32* %b to i8*, !dbg !18
+  call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %1) #5, !dbg !18
+  call void @llvm.dbg.value(metadata i32 1, metadata !16, metadata !DIExpression()), !dbg !24
+  store i32 1, i32* %b, align 4, !dbg !24, !tbaa !20
+  call void @llvm.dbg.value(metadata i32 0, metadata !13, metadata !DIExpression()), !dbg !25
+  %cmp4 = icmp sgt i32 %n, 0, !dbg !26
+  call void @llvm.dbg.value(metadata i32 1, metadata !16, metadata !DIExpression()), !dbg !24
+  br i1 %cmp4, label %for.body.preheader, label %for.end, !dbg !29
+
+for.body.preheader:                               ; preds = %entry
+  call void @llvm.dbg.value(metadata i32 0, metadata !13, metadata !DIExpression()), !dbg !25
+  call void @llvm.dbg.value(metadata i32 0, metadata !15, metadata !DIExpression()), !dbg !19
+  call void @llvm.dbg.value(metadata i32 1, metadata !15, metadata !DIExpression()), !dbg !19
+  store i32 1, i32* %a, align 4, !dbg !30, !tbaa !20
+  call void @llvm.dbg.value(metadata i32* %a, metadata !15, metadata !DIExpression()), !dbg !19
+  call void @llvm.dbg.value(metadata i32* %b, metadata !16, metadata !DIExpression()), !dbg !24
+  call void @swap(i32* nonnull %a, i32* nonnull %b) #5, !dbg !32
+  call void @llvm.dbg.value(metadata i32 1, metadata !13, metadata !DIExpression()), !dbg !25
+  %2 = load i32, i32* %b, align 4, !dbg !33, !tbaa !20
+  call void @llvm.dbg.value(metadata i32 %2, metadata !16, metadata !DIExpression()), !dbg !24
+  %exitcond9 = icmp eq i32 %n, 1, !dbg !26
+  br i1 %exitcond9, label %for.end, label %for.body.for.body_crit_edge, !dbg !29, !llvm.loop !34
+
+for.body.for.body_crit_edge:                      ; preds = %for.body.preheader, %for.body.for.body_crit_edge
+  %3 = phi i32 [ %4, %for.body.for.body_crit_edge ], [ %2, %for.body.preheader ]
+  %inc10 = phi i32 [ %inc, %for.body.for.body_crit_edge ], [ 1, %for.body.preheader ]
+  %.pre = load i32, i32* %a, align 4, !dbg !30, !tbaa !20
+  call void @llvm.dbg.value(metadata i32 %inc10, metadata !13, metadata !DIExpression()), !dbg !25
+  call void @llvm.dbg.value(metadata i32 %.pre, metadata !15, metadata !DIExpression()), !dbg !19
+  %add = add nsw i32 %.pre, %3, !dbg !30
+  call void @llvm.dbg.value(metadata i32 %add, metadata !15, metadata !DIExpression()), !dbg !19
+  store i32 %add, i32* %a, align 4, !dbg !30, !tbaa !20
+  call void @llvm.dbg.value(metadata i32* %a, metadata !15, metadata !DIExpression()), !dbg !19
+  call void @llvm.dbg.value(metadata i32* %b, metadata !16, metadata !DIExpression()), !dbg !24
+  call void @swap(i32* nonnull %a, i32* nonnull %b) #5, !dbg !32
+  %inc = add nuw nsw i32 %inc10, 1, !dbg !36
+  call void @llvm.dbg.value(metadata i32 %inc, metadata !13, metadata !DIExpression()), !dbg !25
+  %4 = load i32, i32* %b, align 4, !dbg !33, !tbaa !20
+  call void @llvm.dbg.value(metadata i32 %4, metadata !16, metadata !DIExpression()), !dbg !24
+  %exitcond = icmp eq i32 %inc, %n, !dbg !26
+  br i1 %exitcond, label %for.end, label %for.body.for.body_crit_edge, !dbg !29, !llvm.loop !34
+
+for.end:                                          ; preds = %for.body.for.body_crit_edge, %for.body.preheader, %entry
+  %.lcssa = phi i32 [ 1, %entry ], [ %2, %for.body.preheader ], [ %4, %for.body.for.body_crit_edge ]
+  call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %1) #5, !dbg !37
+  call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0) #5, !dbg !37
+  ret i32 %.lcssa, !dbg !38
+}
+
+; Function Attrs: argmemonly nounwind
+declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
+
+declare void @swap(i32*, i32*) local_unnamed_addr #2
+
+; Function Attrs: argmemonly nounwind
+declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
+
+; Function Attrs: norecurse nounwind readnone
+define hidden void @_start() local_unnamed_addr #3 !dbg !39 {
+entry:
+  ret void, !dbg !42
+}
+
+; Function Attrs: nounwind readnone speculatable
+declare void @llvm.dbg.value(metadata, metadata, metadata) #4
+
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { argmemonly nounwind }
+attributes #2 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #4 = { nounwind readnone speculatable }
+attributes #5 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4, !5}
+!llvm.ident = !{!6}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 7.0.0 (trunk 334610)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
+!1 = !DIFile(filename: "fib.c", directory: "/d/y/llvmwasm")
+!2 = !{}
+!3 = !{i32 2, !"Dwarf Version", i32 4}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
+!5 = !{i32 1, !"wchar_size", i32 4}
+!6 = !{!"clang version 7.0.0 (trunk 334610)"}
+!7 = distinct !DISubprogram(name: "fib", scope: !1, file: !1, line: 4, type: !8, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: true, unit: !0, retainedNodes: !11)
+!8 = !DISubroutineType(types: !9)
+!9 = !{!10, !10}
+!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+!11 = !{!12, !13, !14, !15, !16}
+!12 = !DILocalVariable(name: "n", arg: 1, scope: !7, file: !1, line: 4, type: !10)
+!13 = !DILocalVariable(name: "i", scope: !7, file: !1, line: 5, type: !10)
+!14 = !DILocalVariable(name: "t", scope: !7, file: !1, line: 5, type: !10)
+!15 = !DILocalVariable(name: "a", scope: !7, file: !1, line: 5, type: !10)
+!16 = !DILocalVariable(name: "b", scope: !7, file: !1, line: 5, type: !10)
+!17 = !DILocation(line: 4, column: 13, scope: !7)
+!18 = !DILocation(line: 5, column: 3, scope: !7)
+!19 = !DILocation(line: 5, column: 13, scope: !7)
+!20 = !{!21, !21, i64 0}
+!21 = !{!"int", !22, i64 0}
+!22 = !{!"omnipotent char", !23, i64 0}
+!23 = !{!"Simple C/C++ TBAA"}
+!24 = !DILocation(line: 5, column: 20, scope: !7)
+!25 = !DILocation(line: 5, column: 7, scope: !7)
+!26 = !DILocation(line: 6, column: 17, scope: !27)
+!27 = distinct !DILexicalBlock(scope: !28, file: !1, line: 6, column: 3)
+!28 = distinct !DILexicalBlock(scope: !7, file: !1, line: 6, column: 3)
+!29 = !DILocation(line: 6, column: 3, scope: !28)
+!30 = !DILocation(line: 7, column: 7, scope: !31)
+!31 = distinct !DILexicalBlock(scope: !27, file: !1, line: 6, column: 27)
+!32 = !DILocation(line: 8, column: 5, scope: !31)
+!33 = !DILocation(line: 0, scope: !7)
+!34 = distinct !{!34, !29, !35}
+!35 = !DILocation(line: 9, column: 3, scope: !28)
+!36 = !DILocation(line: 6, column: 23, scope: !27)
+!37 = !DILocation(line: 11, column: 1, scope: !7)
+!38 = !DILocation(line: 10, column: 3, scope: !7)
+!39 = distinct !DISubprogram(name: "_start", scope: !1, file: !1, line: 13, type: !40, isLocal: false, isDefinition: true, scopeLine: 13, isOptimized: true, unit: !0, retainedNodes: !2)
+!40 = !DISubroutineType(types: !41)
+!41 = !{null}
+!42 = !DILocation(line: 13, column: 16, scope: !39)