[Power9] Code Cleanup - Remove needsAggressiveScheduling()

[stefanp]

Summary

As we already return true from needsAggressiveScheduling() for the most recent hardware it would be cleaner to just return true for all PowerPC hardware.

Three tests were deleted because they were looking for correct spill behavior however with the use of the machine scheduler the spill is not longer required and therefore cannot be checked for correctness

2011-12-05-NoSpillDupCR.ll
save-cr-ppc32svr4.ll
save-crbp-ppc32svr4.ll

Also, the following test ppc64-gep-opt.ll was cut down significantly because the removal of needsAggressiveScheduling() also means that PPCSubtarget::useAA() always returns true. That test checked with and without AA. I have removed the without AA portion of the test.

[echristo]

lib/Target/PowerPC/PPCSubtarget.cpp

167–168

Might want to fix up the comment? :)

186–187

These appear to be the defaults?

193–194

Comment update?

[stefanp]

Updated the comments.
Sorry.. I should have caught them initially.

For the defaults:

Policy.OnlyTopDown = false; 
Policy.OnlyBottomUp = false;

The flag Policy.OnlyTopDown does default to false.
However, GenericScheduler::initPolicy changes the default of Policy.OnlyBottomUp to true. I've fixed this so that I only use Policy.OnlyBottomUp = false; and not the other flag which is already a default.

[echristo]

lib/Target/PowerPC/PPCSubtarget.cpp

167–168

I'd probably just delete the comment.

186–187

We should probably comment on why we do this?

193–194

Same.

[stefanp]

Fixed comments according to previous review.

Also, the three tests that I wanted to delete I've actually kept. I added asm to each of those three tests to force the code to spill the condition register. If the condition register is spilled the tests can once again check to see if the spill is correct.

[echristo]

Looking pretty good at this point. I am still curious why we've got the scheduling change here...

lib/Target/PowerPC/PPCSubtarget.cpp

186–187

I do wonder "why" we want to do this rather than just that we're doing it.

[stefanp]

Hi Eric,

We set the generic scheduler to bi-directional scheduling back in 2013. It was at the time when the generic machine scheduler was added to PowerPC. I can only assume that when we did this we ran a set of benchmarks and determined that this is the best option based on that.
However, what I can do now is run a round of SPEC with Top-Of-Trunk and confirm that we still do better in the bi-directional case. (Or at least not worse.)

Does that sound reasonable?

[hfinkel]

In D48663#1147881, @stefanp wrote:

Hi Eric,

We set the generic scheduler to bi-directional scheduling back in 2013. It was at the time when the generic machine scheduler was added to PowerPC. I can only assume that when we did this we ran a set of benchmarks and determined that this is the best option based on that.
However, what I can do now is run a round of SPEC with Top-Of-Trunk and confirm that we still do better in the bi-directional case. (Or at least not worse.)

Yep. Those benchmarks were likely run on a P7, so rechecking is probably a good idea.

Does that sound reasonable?

[stefanp]

Hi Hal, Eric,

I ran SPEC2017 on a P9 machine and difference between bi-directional and bottom up scheduling was very small overall. The bi-directional scheduling continues to be a bit better with
xalancbmk - 0.5% better on bi-directional
leela - 2.0% better on bi-directional

Changes for all of the other benchmarks were too small.

[hfinkel]

In D48663#1152519, @stefanp wrote:

Hi Hal, Eric,

I ran SPEC2017 on a P9 machine and difference between bi-directional and bottom up scheduling was very small overall. The bi-directional scheduling continues to be a bit better with
xalancbmk - 0.5% better on bi-directional
leela - 2.0% better on bi-directional

Changes for all of the other benchmarks were too small.

Sounds good. Thanks for checking. I recommend keeping it bi-directional.

[nemanjai]

LGTM.

lib/Target/PowerPC/PPCSubtarget.cpp

188

I agree with Eric, please add the reason. Perhaps We want to do bi-directional scheduling since it provides a more balanced schedule leading to better performance.

[echristo]

lib/Target/PowerPC/PPCSubtarget.cpp

188

Yeah... though that's not even really a reason, just describing the effect. :\

lib/Target/PowerPC/PPCSubtarget.cpp

bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
   // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
   // the section that is being relocated. This means we have to use o load even
   // for GVs that are known to be local to the dso.
   if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
     return true;
   return false;
 }
 
-// Embedded cores need aggressive scheduling (and some others also benefit).
-static bool needsAggressiveScheduling(unsigned Directive) {
-  switch (Directive) {
-  default: return false;
-  case PPC::DIR_440:
-  case PPC::DIR_A2:
-  case PPC::DIR_E500mc:
-  case PPC::DIR_E5500:
-  case PPC::DIR_PWR7:
-  case PPC::DIR_PWR8:
-  // FIXME: Same as P8 until POWER9 scheduling info is available
-  case PPC::DIR_PWR9:
-    return true;
-  }
-}
-
 bool PPCSubtarget::enableMachineScheduler() const {
-  // Enable MI scheduling for the embedded cores.
-  // FIXME: Enable this for all cores (some additional modeling
-  // may be necessary).
-  return needsAggressiveScheduling(DarwinDirective);
+  // Enable MI scheduling
+  return true;
 }
 
 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
 
 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
   return TargetSubtargetInfo::ANTIDEP_ALL;
 }
 
 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
   CriticalPathRCs.clear();
   CriticalPathRCs.push_back(isPPC64() ?
                             &PPC::G8RCRegClass : &PPC::GPRCRegClass);
 }
 
 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
                                        unsigned NumRegionInstrs) const {
-  if (needsAggressiveScheduling(DarwinDirective)) {
-    Policy.OnlyTopDown = false;
-    Policy.OnlyBottomUp = false;
-  }
-
   // Spilling is generally expensive on all PPC cores, so always enable
   // register-pressure tracking.
   Policy.ShouldTrackPressure = true;
 }
 
 bool PPCSubtarget::useAA() const {
-  // Use AA during code generation for the embedded cores.
-  return needsAggressiveScheduling(DarwinDirective);
+  // Always use AA for PowerPC.
+  return true;
 }
 
 bool PPCSubtarget::enableSubRegLiveness() const {
   return UseSubRegLiveness;
 }
 
 unsigned char
 PPCSubtarget::classifyGlobalReference(const GlobalValue *GV) const {

test/CodeGen/PowerPC/2008-10-28-f128-i32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o - | FileCheck %s
 
 define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
 ; CHECK-LABEL: __fixunstfdi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stw 0, 4(1)
 ; CHECK-NEXT:    stwu 1, -464(1)
-; CHECK-NEXT:    lis 3, .LCPI0_0@ha
-; CHECK-NEXT:    stfd 27, 424(1) # 8-byte Folded Spill
+; CHECK-NEXT:    mfcr 12
 ; CHECK-NEXT:    stw 29, 412(1) # 4-byte Folded Spill
 ; CHECK-NEXT:    stw 30, 416(1) # 4-byte Folded Spill
-; CHECK-NEXT:    lfs 27, .LCPI0_0@l(3)
-; CHECK-NEXT:    mfcr 12
+; CHECK-NEXT:    stfd 27, 424(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd 28, 432(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd 29, 440(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd 30, 448(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd 31, 456(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stw 12, 408(1)
 ; CHECK-NEXT:    stfd 2, 376(1)
 ; CHECK-NEXT:    stfd 1, 384(1)
-; CHECK-NEXT:    nop
+; CHECK-NEXT:    lis 3, .LCPI0_0@ha
+; CHECK-NEXT:    lwz 4, 380(1)
+; CHECK-NEXT:    lfs 27, .LCPI0_0@l(3)
+; CHECK-NEXT:    stw 4, 396(1)
 ; CHECK-NEXT:    fcmpu 0, 2, 27
-; CHECK-NEXT:    lwz 3, 380(1)
-; CHECK-NEXT:    lwz 4, 376(1)
-; CHECK-NEXT:    lwz 5, 388(1)
-; CHECK-NEXT:    lwz 6, 384(1)
 ; CHECK-NEXT:    fcmpu 1, 1, 27
+; CHECK-NEXT:    lwz 4, 376(1)
 ; CHECK-NEXT:    crand 20, 6, 0
 ; CHECK-NEXT:    cror 20, 4, 20
-; CHECK-NEXT:    stw 3, 396(1)
 ; CHECK-NEXT:    stw 4, 392(1)
-; CHECK-NEXT:    stw 5, 404(1)
-; CHECK-NEXT:    stw 6, 400(1)
+; CHECK-NEXT:    lwz 4, 388(1)
+; CHECK-NEXT:    stw 4, 404(1)
+; CHECK-NEXT:    lwz 29, 384(1)
+; CHECK-NEXT:    stw 29, 400(1)
 ; CHECK-NEXT:    bc 4, 20, .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %bb5
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, 0
 ; CHECK-NEXT:    b .LBB0_16
 ; CHECK-NEXT:  .LBB0_2: # %bb1
-; CHECK-NEXT:    lfd 0, 392(1)
-; CHECK-NEXT:    lfd 1, 400(1)
+; CHECK-NEXT:    lfd 0, 400(1)
+; CHECK-NEXT:    lfd 1, 392(1)
 ; CHECK-NEXT:    li 29, 0
 ; CHECK-NEXT:    lis 3, 15856
-; CHECK-NEXT:    stfd 1, 304(1)
-; CHECK-NEXT:    stfd 0, 296(1)
-; CHECK-NEXT:    nop
-; CHECK-NEXT:    nop
-; CHECK-NEXT:    lwz 4, 308(1)
-; CHECK-NEXT:    lwz 5, 304(1)
-; CHECK-NEXT:    lwz 6, 300(1)
-; CHECK-NEXT:    lwz 7, 296(1)
+; CHECK-NEXT:    stfd 0, 304(1)
+; CHECK-NEXT:    stfd 1, 296(1)
 ; CHECK-NEXT:    stw 29, 340(1)
 ; CHECK-NEXT:    stw 3, 336(1)
 ; CHECK-NEXT:    stw 29, 332(1)
 ; CHECK-NEXT:    stw 29, 328(1)
-; CHECK-NEXT:    stw 4, 324(1)
-; CHECK-NEXT:    stw 5, 320(1)
-; CHECK-NEXT:    stw 6, 316(1)
-; CHECK-NEXT:    stw 7, 312(1)
+; CHECK-NEXT:    lwz 3, 308(1)
+; CHECK-NEXT:    stw 3, 324(1)
+; CHECK-NEXT:    lwz 3, 304(1)
+; CHECK-NEXT:    stw 3, 320(1)
+; CHECK-NEXT:    lwz 3, 300(1)
+; CHECK-NEXT:    stw 3, 316(1)
+; CHECK-NEXT:    lwz 3, 296(1)
+; CHECK-NEXT:    stw 3, 312(1)
+; CHECK-NEXT:    nop
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    lfd 31, 320(1)
 ; CHECK-NEXT:    lfd 30, 312(1)
 ; CHECK-NEXT:    lfd 3, 336(1)
 ; CHECK-NEXT:    lfd 4, 328(1)
 ; CHECK-NEXT:    fmr 1, 31
 ; CHECK-NEXT:    fmr 2, 30
 ; CHECK-NEXT:    bl __gcc_qmul@PLT
+; CHECK-NEXT:    lis 3, 16864
 ; CHECK-NEXT:    stfd 1, 280(1)
 ; CHECK-NEXT:    stfd 2, 288(1)
-; CHECK-NEXT:    lis 3, .LCPI0_1@ha
+; CHECK-NEXT:    stw 29, 372(1)
 ; CHECK-NEXT:    fmr 29, 1
 ; CHECK-NEXT:    fmr 28, 2
-; CHECK-NEXT:    fcmpu 0, 2, 27
-; CHECK-NEXT:    lwz 4, 284(1)
-; CHECK-NEXT:    lwz 5, 280(1)
-; CHECK-NEXT:    lwz 6, 292(1)
-; CHECK-NEXT:    lwz 7, 288(1)
-; CHECK-NEXT:    lfs 0, .LCPI0_1@l(3)
-; CHECK-NEXT:    lis 3, 16864
-; CHECK-NEXT:    stw 29, 372(1)
 ; CHECK-NEXT:    stw 3, 368(1)
 ; CHECK-NEXT:    stw 29, 364(1)
 ; CHECK-NEXT:    stw 29, 360(1)
-; CHECK-NEXT:    stw 4, 356(1)
-; CHECK-NEXT:    stw 5, 352(1)
-; CHECK-NEXT:    stw 6, 348(1)
-; CHECK-NEXT:    stw 7, 344(1)
-; CHECK-NEXT:    fcmpu 1, 1, 0
+; CHECK-NEXT:    lwz 3, 284(1)
+; CHECK-NEXT:    stw 3, 356(1)
+; CHECK-NEXT:    lwz 3, 280(1)
+; CHECK-NEXT:    stw 3, 352(1)
+; CHECK-NEXT:    lwz 3, 292(1)
+; CHECK-NEXT:    stw 3, 348(1)
+; CHECK-NEXT:    lwz 3, 288(1)
+; CHECK-NEXT:    stw 3, 344(1)
 ; CHECK-NEXT:    lfd 3, 368(1)
 ; CHECK-NEXT:    lfd 4, 360(1)
 ; CHECK-NEXT:    lfd 1, 352(1)
 ; CHECK-NEXT:    lfd 2, 344(1)
-; CHECK-NEXT:    crandc 20, 6, 0
-; CHECK-NEXT:    cror 8, 5, 20
 ; CHECK-NEXT:    bl __gcc_qsub@PLT
 ; CHECK-NEXT:    mffs 0
 ; CHECK-NEXT:    mtfsb1 31
+; CHECK-NEXT:    lis 3, .LCPI0_1@ha
+; CHECK-NEXT:    fcmpu 0, 28, 27
 ; CHECK-NEXT:    mtfsb0 30
 ; CHECK-NEXT:    fadd 1, 2, 1
 ; CHECK-NEXT:    mtfsf 1, 0
-; CHECK-NEXT:    mffs 0
-; CHECK-NEXT:    mtfsb1 31
-; CHECK-NEXT:    mtfsb0 30
-; CHECK-NEXT:    fadd 2, 28, 29
-; CHECK-NEXT:    mtfsf 1, 0
 ; CHECK-NEXT:    fctiwz 0, 1
-; CHECK-NEXT:    fctiwz 1, 2
 ; CHECK-NEXT:    stfd 0, 160(1)
-; CHECK-NEXT:    stfd 1, 152(1)
-; CHECK-NEXT:    nop
-; CHECK-NEXT:    lwz 3, 164(1)
+; CHECK-NEXT:    mffs 1
+; CHECK-NEXT:    mtfsb1 31
+; CHECK-NEXT:    mtfsb0 30
+; CHECK-NEXT:    fadd 13, 28, 29
+; CHECK-NEXT:    mtfsf 1, 1
+; CHECK-NEXT:    lfs 1, .LCPI0_1@l(3)
+; CHECK-NEXT:    fctiwz 0, 13
+; CHECK-NEXT:    stfd 0, 152(1)
+; CHECK-NEXT:    fcmpu 1, 29, 1
+; CHECK-NEXT:    crandc 20, 6, 0
+; CHECK-NEXT:    lwz 12, 164(1)
 ; CHECK-NEXT:    lwz 4, 156(1)
-; CHECK-NEXT:    addis 3, 3, -32768
-; CHECK-NEXT:    bc 12, 8, .LBB0_4
+; CHECK-NEXT:    cror 20, 5, 20
+; CHECK-NEXT:    addis 3, 12, -32768
+; CHECK-NEXT:    bc 12, 20, .LBB0_4
 ; CHECK-NEXT:  # %bb.3: # %bb1
 ; CHECK-NEXT:    ori 30, 4, 0
 ; CHECK-NEXT:    b .LBB0_5
 ; CHECK-NEXT:  .LBB0_4: # %bb1
 ; CHECK-NEXT:    addi 30, 3, 0
 ; CHECK-NEXT:  .LBB0_5: # %bb1
-; CHECK-NEXT:    mr 3, 30
 ; CHECK-NEXT:    li 4, 0
+; CHECK-NEXT:    mr 3, 30
 ; CHECK-NEXT:    bl __floatditf@PLT
+; CHECK-NEXT:    lis 3, 17392
 ; CHECK-NEXT:    stfd 1, 208(1)
 ; CHECK-NEXT:    stfd 2, 200(1)
-; CHECK-NEXT:    lis 3, 17392
-; CHECK-NEXT:    fmr 28, 1
-; CHECK-NEXT:    fmr 29, 2
-; CHECK-NEXT:    cmpwi 2, 30, 0
-; CHECK-NEXT:    lwz 4, 212(1)
-; CHECK-NEXT:    lwz 5, 208(1)
-; CHECK-NEXT:    lwz 6, 204(1)
-; CHECK-NEXT:    lwz 7, 200(1)
 ; CHECK-NEXT:    stw 29, 244(1)
+; CHECK-NEXT:    fmr 29, 1
+; CHECK-NEXT:    fmr 28, 2
 ; CHECK-NEXT:    stw 3, 240(1)
 ; CHECK-NEXT:    stw 29, 236(1)
 ; CHECK-NEXT:    stw 29, 232(1)
-; CHECK-NEXT:    stw 4, 228(1)
-; CHECK-NEXT:    stw 5, 224(1)
-; CHECK-NEXT:    stw 6, 220(1)
-; CHECK-NEXT:    stw 7, 216(1)
-; CHECK-NEXT:    nop
+; CHECK-NEXT:    cmpwi 2, 30, 0
+; CHECK-NEXT:    lwz 3, 212(1)
+; CHECK-NEXT:    stw 3, 228(1)
+; CHECK-NEXT:    lwz 3, 208(1)
+; CHECK-NEXT:    stw 3, 224(1)
+; CHECK-NEXT:    lwz 3, 204(1)
+; CHECK-NEXT:    stw 3, 220(1)
+; CHECK-NEXT:    lwz 3, 200(1)
+; CHECK-NEXT:    stw 3, 216(1)
 ; CHECK-NEXT:    lfd 3, 240(1)
 ; CHECK-NEXT:    lfd 4, 232(1)
 ; CHECK-NEXT:    lfd 1, 224(1)
 ; CHECK-NEXT:    lfd 2, 216(1)
 ; CHECK-NEXT:    bl __gcc_qadd@PLT
 ; CHECK-NEXT:    blt 2, .LBB0_7
 ; CHECK-NEXT:  # %bb.6: # %bb1
-; CHECK-NEXT:    fmr 1, 28
+; CHECK-NEXT:    fmr 2, 28
 ; CHECK-NEXT:  .LBB0_7: # %bb1
-; CHECK-NEXT:    stfd 1, 184(1)
 ; CHECK-NEXT:    blt 2, .LBB0_9
 ; CHECK-NEXT:  # %bb.8: # %bb1
-; CHECK-NEXT:    fmr 2, 29
+; CHECK-NEXT:    fmr 1, 29
 ; CHECK-NEXT:  .LBB0_9: # %bb1
+; CHECK-NEXT:    stfd 1, 184(1)
 ; CHECK-NEXT:    stfd 2, 192(1)
 ; CHECK-NEXT:    fmr 1, 31
 ; CHECK-NEXT:    fmr 2, 30
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    nop
 ; CHECK-NEXT:    lwz 3, 188(1)
-; CHECK-NEXT:    lwz 4, 184(1)
-; CHECK-NEXT:    lwz 5, 196(1)
-; CHECK-NEXT:    lwz 6, 192(1)
 ; CHECK-NEXT:    stw 3, 260(1)
-; CHECK-NEXT:    stw 4, 256(1)
-; CHECK-NEXT:    stw 5, 252(1)
-; CHECK-NEXT:    stw 6, 248(1)
+; CHECK-NEXT:    lwz 3, 184(1)
+; CHECK-NEXT:    stw 3, 256(1)
+; CHECK-NEXT:    lwz 3, 196(1)
+; CHECK-NEXT:    stw 3, 252(1)
+; CHECK-NEXT:    lwz 3, 192(1)
+; CHECK-NEXT:    stw 3, 248(1)
 ; CHECK-NEXT:    lfd 3, 256(1)
 ; CHECK-NEXT:    lfd 4, 248(1)
 ; CHECK-NEXT:    bl __gcc_qsub@PLT
 ; CHECK-NEXT:    stfd 2, 176(1)
 ; CHECK-NEXT:    stfd 1, 168(1)
 ; CHECK-NEXT:    fcmpu 1, 1, 27
 ; CHECK-NEXT:    fcmpu 0, 2, 27
 ; CHECK-NEXT:    lwz 3, 180(1)
-; CHECK-NEXT:    lwz 4, 176(1)
-; CHECK-NEXT:    lwz 5, 172(1)
-; CHECK-NEXT:    lwz 6, 168(1)
 ; CHECK-NEXT:    crandc 20, 6, 0
 ; CHECK-NEXT:    cror 21, 5, 7
 ; CHECK-NEXT:    cror 20, 21, 20
 ; CHECK-NEXT:    stw 3, 268(1)
-; CHECK-NEXT:    stw 4, 264(1)
-; CHECK-NEXT:    stw 5, 276(1)
-; CHECK-NEXT:    stw 6, 272(1)
+; CHECK-NEXT:    lwz 3, 176(1)
+; CHECK-NEXT:    stw 3, 264(1)
+; CHECK-NEXT:    lwz 3, 172(1)
+; CHECK-NEXT:    stw 3, 276(1)
+; CHECK-NEXT:    lwz 3, 168(1)
+; CHECK-NEXT:    stw 3, 272(1)
 ; CHECK-NEXT:    lfd 30, 264(1)
 ; CHECK-NEXT:    lfd 31, 272(1)
 ; CHECK-NEXT:    bc 12, 20, .LBB0_13
 ; CHECK-NEXT:  # %bb.10: # %bb2
-; CHECK-NEXT:    fneg 29, 31
-; CHECK-NEXT:    fneg 28, 30
+; CHECK-NEXT:    fneg 28, 31
+; CHECK-NEXT:    fneg 29, 30
 ; CHECK-NEXT:    li 29, 0
 ; CHECK-NEXT:    lis 3, 16864
-; CHECK-NEXT:    stfd 29, 48(1)
-; CHECK-NEXT:    stfd 28, 40(1)
-; CHECK-NEXT:    nop
-; CHECK-NEXT:    lwz 4, 52(1)
-; CHECK-NEXT:    lwz 5, 48(1)
-; CHECK-NEXT:    lwz 6, 44(1)
-; CHECK-NEXT:    lwz 7, 40(1)
+; CHECK-NEXT:    stfd 28, 48(1)
+; CHECK-NEXT:    stfd 29, 40(1)
 ; CHECK-NEXT:    stw 29, 84(1)
 ; CHECK-NEXT:    stw 3, 80(1)
 ; CHECK-NEXT:    stw 29, 76(1)
 ; CHECK-NEXT:    stw 29, 72(1)
-; CHECK-NEXT:    stw 4, 68(1)
-; CHECK-NEXT:    stw 5, 64(1)
-; CHECK-NEXT:    stw 6, 60(1)
-; CHECK-NEXT:    stw 7, 56(1)
 ; CHECK-NEXT:    nop
+; CHECK-NEXT:    lwz 3, 52(1)
+; CHECK-NEXT:    stw 3, 68(1)
+; CHECK-NEXT:    lwz 3, 48(1)
+; CHECK-NEXT:    stw 3, 64(1)
+; CHECK-NEXT:    lwz 3, 44(1)
+; CHECK-NEXT:    stw 3, 60(1)
+; CHECK-NEXT:    lwz 3, 40(1)
+; CHECK-NEXT:    stw 3, 56(1)
 ; CHECK-NEXT:    lfd 3, 80(1)
 ; CHECK-NEXT:    lfd 4, 72(1)
 ; CHECK-NEXT:    lfd 1, 64(1)
 ; CHECK-NEXT:    lfd 2, 56(1)
 ; CHECK-NEXT:    bl __gcc_qsub@PLT
-; CHECK-NEXT:    lis 3, .LCPI0_2@ha
-; CHECK-NEXT:    lis 4, .LCPI0_3@ha
-; CHECK-NEXT:    lfs 0, .LCPI0_2@l(3)
-; CHECK-NEXT:    mffs 11
+; CHECK-NEXT:    mffs 0
 ; CHECK-NEXT:    mtfsb1 31
-; CHECK-NEXT:    lfs 3, .LCPI0_3@l(4)
+; CHECK-NEXT:    lis 3, .LCPI0_2@ha
+; CHECK-NEXT:    lfs 11, .LCPI0_2@l(3)
+; CHECK-NEXT:    lis 3, .LCPI0_3@ha
 ; CHECK-NEXT:    mtfsb0 30
-; CHECK-NEXT:    fcmpu 0, 30, 0
-; CHECK-NEXT:    fcmpu 1, 31, 3
+; CHECK-NEXT:    lfs 13, .LCPI0_3@l(3)
 ; CHECK-NEXT:    fadd 1, 2, 1
+; CHECK-NEXT:    mtfsf 1, 0
+; CHECK-NEXT:    fcmpu 0, 30, 11
+; CHECK-NEXT:    fctiwz 0, 1
+; CHECK-NEXT:    fcmpu 1, 31, 13
+; CHECK-NEXT:    mffs 10
+; CHECK-NEXT:    stfd 0, 32(1)
 ; CHECK-NEXT:    crandc 20, 6, 1
-; CHECK-NEXT:    mtfsf 1, 11
 ; CHECK-NEXT:    cror 20, 4, 20
-; CHECK-NEXT:    mffs 0
 ; CHECK-NEXT:    mtfsb1 31
 ; CHECK-NEXT:    mtfsb0 30
-; CHECK-NEXT:    fadd 12, 28, 29
-; CHECK-NEXT:    mtfsf 1, 0
-; CHECK-NEXT:    fctiwz 0, 1
-; CHECK-NEXT:    fctiwz 13, 12
-; CHECK-NEXT:    stfd 0, 32(1)
-; CHECK-NEXT:    stfd 13, 24(1)
-; CHECK-NEXT:    nop
+; CHECK-NEXT:    fadd 12, 29, 28
+; CHECK-NEXT:    mtfsf 1, 10
+; CHECK-NEXT:    fctiwz 2, 12
+; CHECK-NEXT:    stfd 2, 24(1)
 ; CHECK-NEXT:    lwz 3, 36(1)
 ; CHECK-NEXT:    lwz 4, 28(1)
 ; CHECK-NEXT:    addis 3, 3, -32768
 ; CHECK-NEXT:    bc 12, 20, .LBB0_12
 ; CHECK-NEXT:  # %bb.11: # %bb2
 ; CHECK-NEXT:    ori 3, 4, 0
 ; CHECK-NEXT:    b .LBB0_12
 ; CHECK-NEXT:  .LBB0_12: # %bb2
 ; CHECK-NEXT:    subfic 4, 3, 0
 ; CHECK-NEXT:    subfe 3, 29, 30
 ; CHECK-NEXT:    b .LBB0_16
 ; CHECK-NEXT:  .LBB0_13: # %bb3
-; CHECK-NEXT:    stfd 31, 112(1)
-; CHECK-NEXT:    stfd 30, 104(1)
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    lis 4, 16864
-; CHECK-NEXT:    lwz 5, 116(1)
-; CHECK-NEXT:    lwz 6, 112(1)
-; CHECK-NEXT:    lwz 7, 108(1)
-; CHECK-NEXT:    lwz 8, 104(1)
+; CHECK-NEXT:    stfd 31, 112(1)
+; CHECK-NEXT:    stfd 30, 104(1)
 ; CHECK-NEXT:    stw 3, 148(1)
 ; CHECK-NEXT:    stw 4, 144(1)
 ; CHECK-NEXT:    stw 3, 140(1)
 ; CHECK-NEXT:    stw 3, 136(1)
-; CHECK-NEXT:    stw 5, 132(1)
-; CHECK-NEXT:    stw 6, 128(1)
-; CHECK-NEXT:    stw 7, 124(1)
-; CHECK-NEXT:    stw 8, 120(1)
-; CHECK-NEXT:    nop
+; CHECK-NEXT:    lwz 3, 116(1)
+; CHECK-NEXT:    stw 3, 132(1)
+; CHECK-NEXT:    lwz 3, 112(1)
+; CHECK-NEXT:    stw 3, 128(1)
+; CHECK-NEXT:    lwz 3, 108(1)
+; CHECK-NEXT:    stw 3, 124(1)
+; CHECK-NEXT:    lwz 3, 104(1)
+; CHECK-NEXT:    stw 3, 120(1)
 ; CHECK-NEXT:    lfd 3, 144(1)
 ; CHECK-NEXT:    lfd 4, 136(1)
 ; CHECK-NEXT:    lfd 1, 128(1)
 ; CHECK-NEXT:    lfd 2, 120(1)
 ; CHECK-NEXT:    bl __gcc_qsub@PLT
-; CHECK-NEXT:    lis 3, .LCPI0_0@ha
-; CHECK-NEXT:    lis 4, .LCPI0_1@ha
-; CHECK-NEXT:    lfs 0, .LCPI0_0@l(3)
-; CHECK-NEXT:    mffs 11
+; CHECK-NEXT:    mffs 0
 ; CHECK-NEXT:    mtfsb1 31
-; CHECK-NEXT:    lfs 3, .LCPI0_1@l(4)
+; CHECK-NEXT:    lis 3, .LCPI0_0@ha
+; CHECK-NEXT:    lfs 11, .LCPI0_0@l(3)
+; CHECK-NEXT:    lis 3, .LCPI0_1@ha
 ; CHECK-NEXT:    mtfsb0 30
-; CHECK-NEXT:    fcmpu 0, 30, 0
-; CHECK-NEXT:    fcmpu 1, 31, 3
+; CHECK-NEXT:    lfs 13, .LCPI0_1@l(3)
 ; CHECK-NEXT:    fadd 1, 2, 1
+; CHECK-NEXT:    mtfsf 1, 0
+; CHECK-NEXT:    fcmpu 0, 30, 11
+; CHECK-NEXT:    fctiwz 0, 1
+; CHECK-NEXT:    fcmpu 1, 31, 13
+; CHECK-NEXT:    mffs 10
+; CHECK-NEXT:    stfd 0, 96(1)
 ; CHECK-NEXT:    crandc 20, 6, 0
-; CHECK-NEXT:    mtfsf 1, 11
 ; CHECK-NEXT:    cror 20, 5, 20
-; CHECK-NEXT:    mffs 0
 ; CHECK-NEXT:    mtfsb1 31
 ; CHECK-NEXT:    mtfsb0 30
 ; CHECK-NEXT:    fadd 12, 30, 31
-; CHECK-NEXT:    mtfsf 1, 0
-; CHECK-NEXT:    fctiwz 0, 1
-; CHECK-NEXT:    fctiwz 13, 12
-; CHECK-NEXT:    stfd 0, 96(1)
-; CHECK-NEXT:    stfd 13, 88(1)
-; CHECK-NEXT:    nop
+; CHECK-NEXT:    mtfsf 1, 10
+; CHECK-NEXT:    fctiwz 2, 12
+; CHECK-NEXT:    stfd 2, 88(1)
 ; CHECK-NEXT:    lwz 3, 100(1)
 ; CHECK-NEXT:    lwz 4, 92(1)
 ; CHECK-NEXT:    addis 3, 3, -32768
 ; CHECK-NEXT:    bc 12, 20, .LBB0_14
 ; CHECK-NEXT:    b .LBB0_15
 ; CHECK-NEXT:  .LBB0_14: # %bb3
 ; CHECK-NEXT:    addi 4, 3, 0
 ; CHECK-NEXT:  .LBB0_15: # %bb3

test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll

-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin -mcpu=g4 -disable-ppc-ilp-pref | FileCheck %s
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g4 -disable-ppc-ilp-pref | FileCheck %s
-
-; ModuleID = 'tsc.c'
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
-@a = common global [32000 x float] zeroinitializer, align 16
-@b = common global [32000 x float] zeroinitializer, align 16
-@c = common global [32000 x float] zeroinitializer, align 16
-@d = common global [32000 x float] zeroinitializer, align 16
-@e = common global [32000 x float] zeroinitializer, align 16
-@aa = common global [256 x [256 x float]] zeroinitializer, align 16
-@bb = common global [256 x [256 x float]] zeroinitializer, align 16
-@cc = common global [256 x [256 x float]] zeroinitializer, align 16
-
-@.str11 = private unnamed_addr constant [6 x i8] c"s122 \00", align 1
-@.str152 = private unnamed_addr constant [14 x i8] c"S122\09 %.2f \09\09\00", align 1
-
-declare i32 @printf(i8* nocapture, ...) nounwind
-declare i32 @init(i8* %name) nounwind
-declare i64 @clock() nounwind
-declare i32 @dummy(float*, float*, float*, float*, float*, [256 x float]*, [256 x float]*, [256 x float]*, float)
-declare void @check(i32 %name) nounwind
-
-; CHECK: mfcr
-; CHECK: mtcr
-
-define i32 @s122(i32 %n1, i32 %n3) nounwind {
-entry:
-  %call = tail call i32 @init(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str11, i64 0, i64 0))
-  %call1 = tail call i64 @clock() nounwind
-  %sub = add nsw i32 %n1, -1
-  %cmp316 = icmp slt i32 %sub, 32000
-  br i1 %cmp316, label %entry.split.us, label %for.end.7
-
-entry.split.us:                                   ; preds = %entry
-  %0 = sext i32 %sub to i64
-  %1 = sext i32 %n3 to i64
-  br label %for.body4.lr.ph.us
-
-for.body4.us:                                     ; preds = %for.body4.lr.ph.us, %for.body4.us
-  %indvars.iv20 = phi i64 [ 0, %for.body4.lr.ph.us ], [ %indvars.iv.next21, %for.body4.us ]
-  %indvars.iv = phi i64 [ %0, %for.body4.lr.ph.us ], [ %indvars.iv.next, %for.body4.us ]
-  %indvars.iv.next21 = add i64 %indvars.iv20, 1
-  %sub5.us = sub i64 31999, %indvars.iv20
-  %sext = shl i64 %sub5.us, 32
-  %idxprom.us = ashr exact i64 %sext, 32
-  %arrayidx.us = getelementptr inbounds [32000 x float], [32000 x float]* @b, i64 0, i64 %idxprom.us
-  %2 = load float, float* %arrayidx.us, align 4
-  %arrayidx7.us = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %indvars.iv
-  %3 = load float, float* %arrayidx7.us, align 4
-  %add8.us = fadd float %3, %2
-  store float %add8.us, float* %arrayidx7.us, align 4
-  %indvars.iv.next = add i64 %indvars.iv, %1
-  %4 = trunc i64 %indvars.iv.next to i32
-  %cmp3.us = icmp slt i32 %4, 32000
-  br i1 %cmp3.us, label %for.body4.us, label %for.body4.lr.ph.us.1
-
-for.body4.lr.ph.us:                               ; preds = %entry.split.us, %for.end.us.4
-  %nl.019.us = phi i32 [ 0, %entry.split.us ], [ %inc.us.4, %for.end.us.4 ]
-  br label %for.body4.us
-
-for.end12:                                        ; preds = %for.end.7, %for.end.us.4
-  %call13 = tail call i64 @clock() nounwind
-  %sub14 = sub nsw i64 %call13, %call1
-  %conv = sitofp i64 %sub14 to double
-  %div = fdiv double %conv, 1.000000e+06
-  %call15 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str152, i64 0, i64 0), double %div) nounwind
-  tail call void @check(i32 1)
-  ret i32 0
-
-for.body4.lr.ph.us.1:                             ; preds = %for.body4.us
-  %call10.us = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  br label %for.body4.us.1
-
-for.body4.us.1:                                   ; preds = %for.body4.us.1, %for.body4.lr.ph.us.1
-  %indvars.iv20.1 = phi i64 [ 0, %for.body4.lr.ph.us.1 ], [ %indvars.iv.next21.1, %for.body4.us.1 ]
-  %indvars.iv.1 = phi i64 [ %0, %for.body4.lr.ph.us.1 ], [ %indvars.iv.next.1, %for.body4.us.1 ]
-  %indvars.iv.next21.1 = add i64 %indvars.iv20.1, 1
-  %sub5.us.1 = sub i64 31999, %indvars.iv20.1
-  %sext23 = shl i64 %sub5.us.1, 32
-  %idxprom.us.1 = ashr exact i64 %sext23, 32
-  %arrayidx.us.1 = getelementptr inbounds [32000 x float], [32000 x float]* @b, i64 0, i64 %idxprom.us.1
-  %5 = load float, float* %arrayidx.us.1, align 4
-  %arrayidx7.us.1 = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %indvars.iv.1
-  %6 = load float, float* %arrayidx7.us.1, align 4
-  %add8.us.1 = fadd float %6, %5
-  store float %add8.us.1, float* %arrayidx7.us.1, align 4
-  %indvars.iv.next.1 = add i64 %indvars.iv.1, %1
-  %7 = trunc i64 %indvars.iv.next.1 to i32
-  %cmp3.us.1 = icmp slt i32 %7, 32000
-  br i1 %cmp3.us.1, label %for.body4.us.1, label %for.body4.lr.ph.us.2
-
-for.body4.lr.ph.us.2:                             ; preds = %for.body4.us.1
-  %call10.us.1 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  br label %for.body4.us.2
-
-for.body4.us.2:                                   ; preds = %for.body4.us.2, %for.body4.lr.ph.us.2
-  %indvars.iv20.2 = phi i64 [ 0, %for.body4.lr.ph.us.2 ], [ %indvars.iv.next21.2, %for.body4.us.2 ]
-  %indvars.iv.2 = phi i64 [ %0, %for.body4.lr.ph.us.2 ], [ %indvars.iv.next.2, %for.body4.us.2 ]
-  %indvars.iv.next21.2 = add i64 %indvars.iv20.2, 1
-  %sub5.us.2 = sub i64 31999, %indvars.iv20.2
-  %sext24 = shl i64 %sub5.us.2, 32
-  %idxprom.us.2 = ashr exact i64 %sext24, 32
-  %arrayidx.us.2 = getelementptr inbounds [32000 x float], [32000 x float]* @b, i64 0, i64 %idxprom.us.2
-  %8 = load float, float* %arrayidx.us.2, align 4
-  %arrayidx7.us.2 = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %indvars.iv.2
-  %9 = load float, float* %arrayidx7.us.2, align 4
-  %add8.us.2 = fadd float %9, %8
-  store float %add8.us.2, float* %arrayidx7.us.2, align 4
-  %indvars.iv.next.2 = add i64 %indvars.iv.2, %1
-  %10 = trunc i64 %indvars.iv.next.2 to i32
-  %cmp3.us.2 = icmp slt i32 %10, 32000
-  br i1 %cmp3.us.2, label %for.body4.us.2, label %for.body4.lr.ph.us.3
-
-for.body4.lr.ph.us.3:                             ; preds = %for.body4.us.2
-  %call10.us.2 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  br label %for.body4.us.3
-
-for.body4.us.3:                                   ; preds = %for.body4.us.3, %for.body4.lr.ph.us.3
-  %indvars.iv20.3 = phi i64 [ 0, %for.body4.lr.ph.us.3 ], [ %indvars.iv.next21.3, %for.body4.us.3 ]
-  %indvars.iv.3 = phi i64 [ %0, %for.body4.lr.ph.us.3 ], [ %indvars.iv.next.3, %for.body4.us.3 ]
-  %indvars.iv.next21.3 = add i64 %indvars.iv20.3, 1
-  %sub5.us.3 = sub i64 31999, %indvars.iv20.3
-  %sext25 = shl i64 %sub5.us.3, 32
-  %idxprom.us.3 = ashr exact i64 %sext25, 32
-  %arrayidx.us.3 = getelementptr inbounds [32000 x float], [32000 x float]* @b, i64 0, i64 %idxprom.us.3
-  %11 = load float, float* %arrayidx.us.3, align 4
-  %arrayidx7.us.3 = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %indvars.iv.3
-  %12 = load float, float* %arrayidx7.us.3, align 4
-  %add8.us.3 = fadd float %12, %11
-  store float %add8.us.3, float* %arrayidx7.us.3, align 4
-  %indvars.iv.next.3 = add i64 %indvars.iv.3, %1
-  %13 = trunc i64 %indvars.iv.next.3 to i32
-  %cmp3.us.3 = icmp slt i32 %13, 32000
-  br i1 %cmp3.us.3, label %for.body4.us.3, label %for.body4.lr.ph.us.4
-
-for.body4.lr.ph.us.4:                             ; preds = %for.body4.us.3
-  %call10.us.3 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  br label %for.body4.us.4
-
-for.body4.us.4:                                   ; preds = %for.body4.us.4, %for.body4.lr.ph.us.4
-  %indvars.iv20.4 = phi i64 [ 0, %for.body4.lr.ph.us.4 ], [ %indvars.iv.next21.4, %for.body4.us.4 ]
-  %indvars.iv.4 = phi i64 [ %0, %for.body4.lr.ph.us.4 ], [ %indvars.iv.next.4, %for.body4.us.4 ]
-  %indvars.iv.next21.4 = add i64 %indvars.iv20.4, 1
-  %sub5.us.4 = sub i64 31999, %indvars.iv20.4
-  %sext26 = shl i64 %sub5.us.4, 32
-  %idxprom.us.4 = ashr exact i64 %sext26, 32
-  %arrayidx.us.4 = getelementptr inbounds [32000 x float], [32000 x float]* @b, i64 0, i64 %idxprom.us.4
-  %14 = load float, float* %arrayidx.us.4, align 4
-  %arrayidx7.us.4 = getelementptr inbounds [32000 x float], [32000 x float]* @a, i64 0, i64 %indvars.iv.4
-  %15 = load float, float* %arrayidx7.us.4, align 4
-  %add8.us.4 = fadd float %15, %14
-  store float %add8.us.4, float* %arrayidx7.us.4, align 4
-  %indvars.iv.next.4 = add i64 %indvars.iv.4, %1
-  %16 = trunc i64 %indvars.iv.next.4 to i32
-  %cmp3.us.4 = icmp slt i32 %16, 32000
-  br i1 %cmp3.us.4, label %for.body4.us.4, label %for.end.us.4
-
-for.end.us.4:                                     ; preds = %for.body4.us.4
-  %call10.us.4 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %inc.us.4 = add nsw i32 %nl.019.us, 5
-  %exitcond.4 = icmp eq i32 %inc.us.4, 200000
-  br i1 %exitcond.4, label %for.end12, label %for.body4.lr.ph.us
-
-for.end.7:                                        ; preds = %entry, %for.end.7
-  %nl.019 = phi i32 [ %inc.7, %for.end.7 ], [ 0, %entry ]
-  %call10 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %call10.1 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %call10.2 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %call10.3 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %call10.4 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %call10.5 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %call10.6 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %call10.7 = tail call i32 @dummy(float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @b, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @c, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @d, i64 0, i64 0), float* getelementptr inbounds ([32000 x float], [32000 x float]* @e, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @aa, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @bb, i64 0, i64 0), [256 x float]* getelementptr inbounds ([256 x [256 x float]], [256 x [256 x float]]* @cc, i64 0, i64 0), float 0.000000e+00) nounwind
-  %inc.7 = add nsw i32 %nl.019, 8
-  %exitcond.7 = icmp eq i32 %inc.7, 200000
-  br i1 %exitcond.7, label %for.end12, label %for.end.7
-}
-
-declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind
-
-declare i32 @puts(i8* nocapture) nounwind
-
-!3 = !{!"branch_weights", i32 64, i32 4}

test/CodeGen/PowerPC/coalesce-ext.ll

 ; RUN: llc -verify-machineinstrs -mcpu=g5 -mtriple=powerpc64-apple-darwin < %s | FileCheck %s
 ; Check that the peephole optimizer knows about sext and zext instructions.
 ; CHECK: test1sext
 define i32 @test1sext(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
   %C = add i64 %A, %B
   ; CHECK: add [[SUM:r[0-9]+]], r3, r4
   %D = trunc i64 %C to i32
   %E = shl i64 %C, 32
   %F = ashr i64 %E, 32
   ; CHECK: extsw [[EXT:r[0-9]+]], [[SUM]]
   store volatile i64 %F, i64 *%P2
-  ; CHECK: std [[EXT]]
+  ; CHECK-DAG: std [[EXT]]
   store volatile i32 %D, i32* %P
   ; Reuse low bits of extended register, don't extend live range of SUM.
-  ; CHECK: stw [[EXT]]
+  ; CHECK-DAG: stw [[SUM]]
   %R = add i32 %D, %D
   ret i32 %R
 }

test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll

 ; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
 ; PPC64-P8-NOT: BARRIER
 ; PPC64-P8-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
 ; PPC64-P8-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
 ; PPC64-P8-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]]
 ; PPC64-P8: blr
 
 ; PPC32: stfd 1, [[STACK:[0-9]+]](1)
-; PPC32: nop
 ; PPC32: lwz [[HI:[0-9]+]], [[STACK]](1)
 ; PPC32: rlwinm [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0, 0
 ; PPC32-NOT: BARRIER
 ; PPC32-DAG: oris {{[0-9]+}}, [[FLIP_BIT]], 16399
 ; PPC32-DAG: xoris {{[0-9]+}}, [[FLIP_BIT]], 48304
 ; PPC32: blr
   %0 = tail call ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128 0xM400F000000000000BCB0000000000000, ppc_fp128 %x)
   %1 = bitcast ppc_fp128 %0 to i128
   ret i128 %1
 }
 
 declare ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128)
 declare ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128, ppc_fp128)

test/CodeGen/PowerPC/i1-to-double.ll

 ; RUN: llc -verify-machineinstrs -mcpu=ppc32 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
 define double @test(i1 %X) {
         %Y = uitofp i1 %X to double
         ret double %Y
 }
 
 ; CHECK-LABEL: @test
 
 ; CHECK: andi. {{[0-9]+}}, 3, 1
-; CHECK-NEXT: addis 4, 4, .LCPI
-; CHECK-NEXT: addis 5, 5, .LCPI
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
-; CHECK: ori 3, 4, 0
+; CHECK: addis {{[0-9]+}}, {{[0-9]+}}, .LCPI
+; CHECK: addis {{[0-9]+}}, {{[0-9]+}}, .LCPI
+; CHECK: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT: [[TRUE]]
-; CHECK-NEXT: addi 3, 5, 0
+; CHECK-NEXT: addi 3, 4, 0
 ; CHECK-NEXT: [[SUCCESSOR]]
 ; CHECK-NEXT: lfs 1, 0(3)
 ; CHECK-NEXT: blr

test/CodeGen/PowerPC/lsa.ll

entry:
   %arraydecay2 = getelementptr inbounds [8200 x i32], [8200 x i32]* %w, i64 0, i64 0
   call void @bar(i32* %arraydecay, i32* %arraydecay1, i32* %arraydecay2) #0
   %3 = load i32, i32* %arraydecay2, align 4
   %arrayidx3 = getelementptr inbounds [8200 x i32], [8200 x i32]* %w, i64 0, i64 1
   %4 = load i32, i32* %arrayidx3, align 4
 
 ; CHECK: @foo
 ; CHECK-NOT: lwzx
-; CHECK: lwz {{[0-9]+}}, 4([[REG:[0-9]+]])
-; CHECK: lwz {{[0-9]+}}, 0([[REG]])
+; CHECK: lwz {{[0-9]+}}, 0([[REG:[0-9]+]])
+; CHECK: lwz {{[0-9]+}}, 4([[REG]])
 ; CHECK: blr
 
   %add = add nsw i32 %4, %3
   call void @llvm.lifetime.end.p0i8(i64 32800, i8* %2) #0
   call void @llvm.lifetime.end.p0i8(i64 32800, i8* %1) #0
   call void @llvm.lifetime.end.p0i8(i64 32800, i8* %0) #0
   ret i32 %add
 }
 
 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #0
 
 declare void @bar(i32*, i32*, i32*)
 
 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #0
 
 attributes #0 = { nounwind }

test/CodeGen/PowerPC/ppc32-vacopy.ll

entry:
   call void @llvm.va_copy(i8* %3, i8* %2)
 
   ret void
 }
 ; CHECK: test_vacopy:
 ; CHECK: lwz [[REG1:[0-9]+]], {{.*}}
 ; CHECK: lwz [[REG2:[0-9]+]], {{.*}}
 ; CHECK: lwz [[REG3:[0-9]+]], {{.*}}
-; CHECK: stw [[REG1]], {{.*}}
-; CHECK: stw [[REG2]], {{.*}}
-; CHECK: stw [[REG3]], {{.*}}
+; CHECK-DAG: stw [[REG1]], {{.*}}
+; CHECK-DAG: stw [[REG2]], {{.*}}
+; CHECK-DAG: stw [[REG3]], {{.*}}

test/CodeGen/PowerPC/ppc64-gep-opt.ll

 ; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr7 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -O3 -print-after=codegenprepare -mcpu=ppc64 < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-NoAA <%t %s
 ; RUN: llc -verify-machineinstrs -O3 -print-after=codegenprepare -mcpu=pwr7  < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA <%t %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 ; Following test cases test enabling SeparateConstOffsetFromGEP pass in the PPC
 ; backend. If useAA() returns true, it will lower a GEP with multiple indices
 ; into GEPs with a single index, otherwise it will lower it into a
 ; "ptrtoint+arithmetics+inttoptr" form.
if.then:                                          ; preds = %entry
   %2 = load i32, i32* %origin, align 4
   store i32 %2, i32* %adj, align 4
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
   ret void
 }
 
-; CHECK-NoAA-LABEL: @test_GEP_CSE(
-; CHECK-NoAA: [[PTR0:%[a-zA-Z0-9]+]] = ptrtoint [240 x %struct]* %string to i64
-; CHECK-NoAA: [[PTR1:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96
-; CHECK-NoAA: [[PTR2:%[a-zA-Z0-9]+]] = add i64 [[PTR0]], [[PTR1]]
-; CHECK-NoAA: add i64 [[PTR2]], 23052
-; CHECK-NoAA: inttoptr
-; CHECK-NoAA: if.then:
-; CHECK-NoAA-NOT: ptrtoint
-; CHECK-NoAA-NOT: mul
-; CHECK-NoAA: add i64 [[PTR2]], 23048
-; CHECK-NoAA: inttoptr
-
 ; CHECK-UseAA-LABEL: @test_GEP_CSE(
 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = bitcast [240 x %struct]* %string to i8*
 ; CHECK-UseAA: [[IDX:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96
 ; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8, i8* [[PTR0]], i64 [[IDX]]
 ; CHECK-UseAA: getelementptr i8, i8* [[PTR1]], i64 23052
 ; CHECK-UseAA: bitcast
 ; CHECK-UseAA: if.then:
 ; CHECK-UseAA: getelementptr i8, i8* [[PTR1]], i64 23048
exit:
   %7 = add nsw i32 %4, 1
   store i32 %7, i32* %1, align 4
   ret void
 }
 ; CHECK-LABEL: test_GEP_across_BB:
 ; CHECK-NOT: lwzu
 ; CHECK: blr
 
-; CHECK-NoAA-LABEL: test_GEP_across_BB(
-; CHECK-NoAA: add i64 [[TMP:%[a-zA-Z0-9]+]], 528
-; CHECK-NoAA: add i64 [[TMP]], 532
-; CHECK-NoAA: if.true:
-; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, i8* {{.*}}, i64 532
-; CHECK-NoAA: exit:
-; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, i8* {{.*}}, i64 528
-
 ; CHECK-UseAA-LABEL: test_GEP_across_BB(
 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = getelementptr
 ; CHECK-UseAA: getelementptr i8, i8* [[PTR0]], i64 528
 ; CHECK-UseAA: getelementptr i8, i8* [[PTR0]], i64 532
 ; CHECK-UseAA: if.true:
 ; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, i8* [[PTR0]], i64 532
 ; CHECK-UseAA: exit:
 ; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, i8* [[PTR0]], i64 528
 
 %struct.S = type { float, double }
 @struct_array = global [1024 x %struct.S] zeroinitializer, align 16
 
 ; The following two test cases check we can extract constant from indices of
 ; struct type.
 ; The constant offsets are from indices "i64 %idxprom" and "i32 1". As the
 ; alloca size of %struct.S is 16, and "i32 1" is the 2rd element whose field
 ; offset is 8, the total constant offset is (5 * 16 + 8) = 88.
 define double* @test-struct_1(i32 %i) {
 entry:
   %add = add nsw i32 %i, 5
   %idxprom = sext i32 %add to i64
   %p = getelementptr [1024 x %struct.S], [1024 x %struct.S]* @struct_array, i64 0, i64 %idxprom, i32 1
   ret double* %p
 }
-; CHECK-NoAA-LABEL: @test-struct_1(
-; CHECK-NoAA-NOT: getelementptr
-; CHECK-NoAA: add i64 %{{[a-zA-Z0-9]+}}, 88
-
 ; CHECK-UseAA-LABEL: @test-struct_1(
 ; CHECK-UseAA: getelementptr i8, i8* %{{[a-zA-Z0-9]+}}, i64 88
 
 %struct3 = type { i64, i32 }
 %struct2 = type { %struct3, i32 }
 %struct1 = type { i64, %struct2 }
 %struct0 = type { i32, i32, i64*, [100 x %struct1] }
 
 ; The constant offsets are from indices "i32 3", "i64 %arrayidx" and "i32 1".
 ; "i32 3" is the 4th element whose field offset is 16. The alloca size of
 ; %struct1 is 32. "i32 1" is the 2rd element whose field offset is 8. So the
 ; total constant offset is 16 + (-2 * 32) + 8 = -40
 define %struct2* @test-struct_2(%struct0* %ptr, i64 %idx) {
 entry:
   %arrayidx = add nsw i64 %idx, -2
   %ptr2 = getelementptr %struct0, %struct0* %ptr, i64 0, i32 3, i64 %arrayidx, i32 1
   ret %struct2* %ptr2
 }
-; CHECK-NoAA-LABEL: @test-struct_2(
-; CHECK-NoAA-NOT: = getelementptr
-; CHECK-NoAA: add i64 %{{[a-zA-Z0-9]+}}, -40
-
 ; CHECK-UseAA-LABEL: @test-struct_2(
 ; CHECK-UseAA: getelementptr i8, i8* %{{[a-zA-Z0-9]+}}, i64 -40
 
 ; Test that when a index is added from two constant, SeparateConstOffsetFromGEP
 ; pass does not generate incorrect result.
 define void @test_const_add([3 x i32]* %in) {
   %inc = add nsw i32 2, 1
   %idxprom = sext i32 %inc to i64

test/CodeGen/PowerPC/save-cr-ppc32svr4.ll

-; RUN: llc -relocation-model pic < %s | FileCheck %s
-;
-; Make sure that the CR register is saved correctly on PPC32/SVR4.
-
-; CHECK-LABEL: fred:
-; CHECK: stwu 1, -32(1)
-; CHECK: stw 31, 28(1)
-; CHECK: mr 31, 1
-; CHECK: stw 30, 24(1)
-; CHECK: mfcr [[CR:[0-9]+]]
-; CHECK: stw [[CR]], 20(31)
-
-target datalayout = "E-m:e-p:32:32-i64:64-n32"
-target triple = "powerpc-unknown-freebsd"
-
-; Function Attrs: norecurse nounwind readnone sspstrong
-define i64 @fred(double %a0) local_unnamed_addr #0 {
-b1:
-  %v2 = fcmp olt double %a0, 0x43E0000000000000
-  br i1 %v2, label %b3, label %b7
-
-b3:                                               ; preds = %b1
-  %v4 = fcmp olt double %a0, 0xC3E0000000000000
-  %v5 = fptosi double %a0 to i64
-  %v6 = select i1 %v4, i64 -9223372036854775808, i64 %v5
-  br label %b14
-
-b7:                                               ; preds = %b1
-  %v8 = fcmp olt double %a0, 0x43F0000000000000
-  br i1 %v8, label %b9, label %b11
-
-b9:                                               ; preds = %b7
-  %v10 = fptoui double %a0 to i64
-  br label %b14
-
-b11:                                              ; preds = %b7
-  %v12 = fcmp ogt double %a0, 0.000000e+00
-  %v13 = sext i1 %v12 to i64
-  br label %b14
-
-b14:                                              ; preds = %b11, %b9, %b3
-  %v15 = phi i64 [ %v6, %b3 ], [ %v10, %b9 ], [ %v13, %b11 ]
-  ret i64 %v15
-}
-
-attributes #0 = { norecurse nounwind readnone sspstrong "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="ppc" }

test/CodeGen/PowerPC/save-crbp-ppc32svr4.ll

-; RUN: llc -relocation-model pic < %s | FileCheck %s
-
-; CHECK-LABEL: fred
-; CHECK: stwux 1, 1, 0
-; Save R31..R29 via R0:
-; CHECK: addic 0, 0, -4
-; CHECK: stwx 31, 0, 0
-; CHECK: addic 0, 0, -4
-; CHECK: stwx 30, 0, 0
-; CHECK: addic 0, 0, -4
-; CHECK: stwx 29, 0, 0
-; Set R29 back to the value of R0 from before the updates:
-; CHECK: addic 29, 0, 12
-; Save CR through R12 using R29 as the stack pointer (aligned base pointer).
-; CHECK: mfcr 12
-; CHECK: stw 28, -16(29)
-; CHECK: stw 12, -20(29)
-
-target datalayout = "E-m:e-p:32:32-i64:64-n32"
-target triple = "powerpc-unknown-freebsd"
-
-; Function Attrs: norecurse readnone sspstrong
-define i64 @fred(double %a0) local_unnamed_addr #0 {
-b1:
-  %v2 = alloca i64, align 128
-  store i64 0, i64* %v2
-  %v3 = fcmp olt double %a0, 0x43E0000000000000
-  br i1 %v3, label %b4, label %b8
-
-b4:                                               ; preds = %b1
-  %v5 = fcmp olt double %a0, 0xC3E0000000000000
-  %v6 = fptosi double %a0 to i64
-  store i64 %v6, i64* %v2
-  %v7 = select i1 %v5, i64 -9223372036854775808, i64 %v6
-  br label %b15
-
-b8:                                               ; preds = %b1
-  %v9 = fcmp olt double %a0, 0x43F0000000000000
-  br i1 %v9, label %b10, label %b12
-
-b10:                                              ; preds = %b8
-  %v11 = fptoui double %a0 to i64
-  br label %b15
-
-b12:                                              ; preds = %b8
-  %v13 = fcmp ogt double %a0, 0.000000e+00
-  %v14 = sext i1 %v13 to i64
-  br label %b15
-
-b15:                                              ; preds = %b12, %b10, %b4
-  %v16 = phi i64 [ %v7, %b4 ], [ %v11, %b10 ], [ %v14, %b12 ]
-  %v17 = load i64, i64* %v2
-  %v18 = add i64 %v17, %v16
-  ret i64 %v18
-}
-
-attributes #0 = { norecurse readnone sspstrong "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="ppc" }

test/CodeGen/PowerPC/tls.ll

 define i32 @localexec() nounwind {
 entry:
 ;OPT0:          addis [[REG1:[0-9]+]], 13, a@tprel@ha
 ;OPT0-NEXT:     addi [[REG1]], [[REG1]], a@tprel@l
 ;OPT0-NEXT:     li [[REG2:[0-9]+]], 42
 ;OPT0:          stw [[REG2]], 0([[REG1]])
 ;OPT1:          addis [[REG1:[0-9]+]], 13, a@tprel@ha
 ;OPT1-NEXT:     li [[REG2:[0-9]+]], 42
-;OPT1-NEXT:     stw [[REG2]], a@tprel@l([[REG1]])
+;OPT1:     stw [[REG2]], a@tprel@l([[REG1]])
   store i32 42, i32* @a, align 4
   ret i32 0
 }
 
 ; Test correct assembly code generation for thread-local storage
 ; using the initial-exec model.
 
 @a2 = external thread_local global i32

test/CodeGen/PowerPC/unal-altivec.ll

vector.body:                                      ; preds = %vector.body, %vector.ph
   %9 = bitcast float* %8 to <4 x float>*
   store <4 x float> %5, <4 x float>* %9, align 4
   %index.next = add i64 %index, 8
   %10 = icmp eq i64 %index.next, 16000
   br i1 %10, label %for.end, label %vector.body
 
 ; CHECK: @foo
 ; CHECK-DAG: li [[C0:[0-9]+]], 0
-; CHECK-DAG: li [[C15:[0-9]+]], 15
 ; CHECK-DAG: lvx [[CNST:[0-9]+]],
 ; CHECK: .LBB0_1:
 ; CHECK-DAG: lvsl [[MASK1:[0-9]+]], [[B1:[0-9]+]], [[C0]]
 ; CHECK-DAG: lvsl [[MASK2:[0-9]+]], [[B2:[0-9]+]], [[C0]]
 ; CHECK-DAG: add [[B3:[0-9]+]], [[B1]], [[C0]]
 ; CHECK-DAG: add [[B4:[0-9]+]], [[B2]], [[C0]]
 ; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
-; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]], [[C15]]
+; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]],
 ; CHECK-DAG: lvx [[LD3:[0-9]+]], [[B2]], [[C0]]
-; CHECK-DAG: lvx [[LD4:[0-9]+]], [[B4]], [[C15]]
+; CHECK-DAG: lvx [[LD4:[0-9]+]], [[B4]],
 ; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
 ; CHECK-DAG: vperm [[R2:[0-9]+]], [[LD3]], [[LD4]], [[MASK2]]
 ; CHECK-DAG: vaddfp {{[0-9]+}}, [[R1]], [[CNST]]
 ; CHECK-DAG: vaddfp {{[0-9]+}}, [[R2]], [[CNST]]
 ; CHECK: blr
 
 for.end:                                          ; preds = %vector.body
   ret void
 }
 
 attributes #0 = { nounwind }