This patch adds lowering for atomic fences to the native RV32I fence instructions and relies on AtomicExpandPass to lower atomic loads/stores, atomic rmw, and cmpxchg to __atomic_* libcalls. Future patches add support for RV32A, providing atomics support without libcalls.
test/CodeGen/RISCV/atomic-* are modelled on the exhaustive test/CodeGen/PPC/atomics-regression.ll, and will prove more useful once RV32A codegen support is introduced. I'd welcome feedback on if I'm missing anything obvious. I believe that lowering fences but emitting __atomic libcalls otherwise seems to match the behaviour of other backends (e.g. Sparc) and seems correct, but I'd appreciate further opinions.
Fence mappings are taken from table A.6 in the current draft of version 2.3 of the RISC-V Instruction Set Manual, which incorporates the memory model changes and definitions contributed by the RISC-V Memroy Consistency Model task group.