[AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (shift by immediate) instructions.

llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE] in {
   def RDVLI_XI  : sve_int_read_vl_a<0b0, 0b11111, "rdvl">;
   def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">;
   def ADDPL_XXI : sve_int_arith_vl<0b1, "addpl">;
 
   defm INDEX_RR : sve_int_index_rr<"index">;
   defm INDEX_IR : sve_int_index_ir<"index">;
   defm INDEX_RI : sve_int_index_ri<"index">;
   defm INDEX_II : sve_int_index_ii<"index">;
+
+  defm LSR_ZZI : sve_int_bin_cons_shift_b_right<0b01, "lsr">;
+  defm LSL_ZZI : sve_int_bin_cons_shift_b_left< 0b11, "lsl">;
 }

llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td

 multiclass sve_int_index_rr<string asm> {
   def _B : sve_int_index_rr<0b00, asm, ZPR8, GPR32>;
   def _H : sve_int_index_rr<0b01, asm, ZPR16, GPR32>;
   def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>;
   def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>;
 }
 
 //===----------------------------------------------------------------------===//
+// SVE Shift by Immediate - Unpredicated Group
+//===----------------------------------------------------------------------===//
+
+class sve_int_bin_cons_shift_b<bits<4> tsz8_64, bits<2> opc, string asm,
+                               ZPRRegOp zprty, Operand immtype>
+: I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$imm),
+  asm, "\t$Zd, $Zn, $imm",
+  "", []>, Sched<[]> {
+  bits<5> Zd;
+  bits<5> Zn;
+  bits<6> imm;
+  let Inst{31-24} = 0b00000100;
+  let Inst{23-22} = tsz8_64{3-2};
+  let Inst{21}    = 0b1;
+  let Inst{20-19} = tsz8_64{1-0};
+  let Inst{18-16} = imm{2-0}; // imm3
+  let Inst{15-12} = 0b1001;
+  let Inst{11-10} = opc;
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Zd;
+}
+
+multiclass sve_int_bin_cons_shift_b_left<bits<2> opc, string asm> {
+  def _B : sve_int_bin_cons_shift_b<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>;
+  def _H : sve_int_bin_cons_shift_b<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> {
+    let Inst{19} = imm{3};
+  }
+  def _S : sve_int_bin_cons_shift_b<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> {
+    let Inst{20-19} = imm{4-3};
+  }
+  def _D : sve_int_bin_cons_shift_b<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> {
+    let Inst{22}    = imm{5};
+    let Inst{20-19} = imm{4-3};
+  }
+}
+
+multiclass sve_int_bin_cons_shift_b_right<bits<2> opc, string asm> {
+  def _B : sve_int_bin_cons_shift_b<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
+  def _H : sve_int_bin_cons_shift_b<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
+    let Inst{19} = imm{3};
+  }
+  def _S : sve_int_bin_cons_shift_b<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
+    let Inst{20-19} = imm{4-3};
+  }
+  def _D : sve_int_bin_cons_shift_b<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
+    let Inst{22}    = imm{5};
+    let Inst{20-19} = imm{4-3};
+  }
+}
+//===----------------------------------------------------------------------===//
 // SVE Permute - Predicates Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_perm_bin_perm_pp<bits<3> opc, bits<2> sz8_64, string asm,
                                PPRRegOp pprty>
 : I<(outs pprty:$Pd), (ins pprty:$Pn, pprty:$Pm),
   asm, "\t$Pd, $Pn, $Pm",
   "",

llvm/trunk/test/MC/AArch64/SVE/lsl-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+lsl z18.b, z28.b, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
+// CHECK-NEXT: lsl z18.b, z28.b, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lsl z1.b, z9.b, #8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
+// CHECK-NEXT: lsl z1.b, z9.b, #8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lsl z21.h, z2.h, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
+// CHECK-NEXT: lsl z21.h, z2.h, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lsl z14.h, z30.h, #16
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
+// CHECK-NEXT: lsl z14.h, z30.h, #16
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lsl z6.s, z12.s, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
+// CHECK-NEXT: lsl z6.s, z12.s, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lsl z23.s, z19.s, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
+// CHECK-NEXT: lsl z23.s, z19.s, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lsl z3.d, z24.d, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
+// CHECK-NEXT: lsl z3.d, z24.d, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lsl z25.d, z16.d, #64
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
+// CHECK-NEXT: lsl z25.d, z16.d, #64
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/lsl.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+lsl     z0.b, z0.b, #0
+// CHECK-INST: lsl     z0.b, z0.b, #0
+// CHECK-ENCODING: [0x00,0x9c,0x28,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 9c 28 04 <unknown>
+
+lsl     z31.b, z31.b, #7
+// CHECK-INST: lsl     z31.b, z31.b, #7
+// CHECK-ENCODING: [0xff,0x9f,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f 2f 04 <unknown>
+
+lsl     z0.h, z0.h, #0
+// CHECK-INST: lsl     z0.h, z0.h, #0
+// CHECK-ENCODING: [0x00,0x9c,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 9c 30 04 <unknown>
+
+lsl     z31.h, z31.h, #15
+// CHECK-INST: lsl     z31.h, z31.h, #15
+// CHECK-ENCODING: [0xff,0x9f,0x3f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f 3f 04 <unknown>
+
+lsl     z0.s, z0.s, #0
+// CHECK-INST: lsl     z0.s, z0.s, #0
+// CHECK-ENCODING: [0x00,0x9c,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 9c 60 04 <unknown>
+
+lsl     z31.s, z31.s, #31
+// CHECK-INST: lsl     z31.s, z31.s, #31
+// CHECK-ENCODING: [0xff,0x9f,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f 7f 04 <unknown>
+
+lsl     z0.d, z0.d, #0
+// CHECK-INST: lsl     z0.d, z0.d, #0
+// CHECK-ENCODING: [0x00,0x9c,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 9c a0 04 <unknown>
+
+lsl     z31.d, z31.d, #63
+// CHECK-INST: lsl     z31.d, z31.d, #63
+// CHECK-ENCODING: [0xff,0x9f,0xff,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f ff 04 <unknown>

llvm/trunk/test/MC/AArch64/SVE/lsr-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+lsr z30.b, z10.b, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
+// CHECK-NEXT: lsr z30.b, z10.b, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lsr z18.b, z27.b, #9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
+// CHECK-NEXT: lsr z18.b, z27.b, #9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lsr z26.h, z4.h, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: lsr z26.h, z4.h, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lsr z25.h, z10.h, #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: lsr z25.h, z10.h, #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lsr z17.s, z0.s, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
+// CHECK-NEXT: lsr z17.s, z0.s, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lsr z0.s, z15.s, #33
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
+// CHECK-NEXT: lsr z0.s, z15.s, #33
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lsr z4.d, z13.d, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
+// CHECK-NEXT: lsr z4.d, z13.d, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lsr z26.d, z26.d, #65
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
+// CHECK-NEXT: lsr z26.d, z26.d, #65
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/lsr.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+lsr     z0.b, z0.b, #8
+// CHECK-INST: lsr     z0.b, z0.b, #8
+// CHECK-ENCODING: [0x00,0x94,0x28,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 94 28 04 <unknown>
+
+lsr     z31.b, z31.b, #1
+// CHECK-INST: lsr     z31.b, z31.b, #1
+// CHECK-ENCODING: [0xff,0x97,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 97 2f 04 <unknown>
+
+lsr     z0.h, z0.h, #16
+// CHECK-INST: lsr     z0.h, z0.h, #16
+// CHECK-ENCODING: [0x00,0x94,0x30,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 94 30 04 <unknown>
+
+lsr     z31.h, z31.h, #1
+// CHECK-INST: lsr     z31.h, z31.h, #1
+// CHECK-ENCODING: [0xff,0x97,0x3f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 97 3f 04 <unknown>
+
+lsr     z0.s, z0.s, #32
+// CHECK-INST: lsr     z0.s, z0.s, #32
+// CHECK-ENCODING: [0x00,0x94,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 94 60 04 <unknown>
+
+lsr     z31.s, z31.s, #1
+// CHECK-INST: lsr     z31.s, z31.s, #1
+// CHECK-ENCODING: [0xff,0x97,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 97 7f 04 <unknown>
+
+lsr     z0.d, z0.d, #64
+// CHECK-INST: lsr     z0.d, z0.d, #64
+// CHECK-ENCODING: [0x00,0x94,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 94 a0 04 <unknown>
+
+lsr     z31.d, z31.d, #1
+// CHECK-INST: lsr     z31.d, z31.d, #1
+// CHECK-ENCODING: [0xff,0x97,0xff,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 97 ff 04 <unknown>