[RISCV] Override EmitToStreamer in RISCVAsmPrinter to handle missed compression opportunities

[sabuasal]

Summary

[RISCV] Update EmitToStreamer in RISCVAsmPrinter to handle missed compression
opportunities

Updating Compression hooks in D41932 to move compression from
ElfStream to AsmPrinter caused missing  opportunities for
compression. This is due to emitPseudoExpansionLowering lowering
Machine instructions to MC Instructions and emitting them directly
to the stream without calling compression.

This patch fixes the problem by shadowing EmitToStreamer in
RISCVAsmPrinter to call compressInst before emitting.

[efriedma]

Oh, I didn't realize there was another codepath when I suggested RISCVAsmPrinter::EmitInstruction.

It's generally a good idea to avoid virtual functions where possible... in this context, I think it would work correctly if you just shadow the function?

[asb]

This seems like a good improvement. As Eli says, avoiding the virtual function if possible would be ideal.

[sabuasal]

Shadow instead of override.

Thanks @efriedma !

[asb]

Looks good to me. Thanks.

[sabuasal]

Committed with: https://reviews.llvm.org/D45385

lib/Target/RISCV/RISCVAsmPrinter.cpp

public:
 
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                        unsigned AsmVariant, const char *ExtraCode,
                        raw_ostream &OS) override;
   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
                              unsigned AsmVariant, const char *ExtraCode,
                              raw_ostream &OS) override;
 
+  void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
   bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
                                    const MachineInstr *MI);
 
   // Wrapper needed for tblgenned pseudo lowering.
   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
     return LowerRISCVMachineOperandToMCOperand(MO, MCOp, *this);
   }
 };
 }
 
+#define GEN_COMPRESS_INSTR
+#include "RISCVGenCompressInstEmitter.inc"
+void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
+  MCInst CInst;
+  bool Res = compressInst(CInst, Inst, *TM.getMCSubtargetInfo(),
+                          OutStreamer->getContext());
+  AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst);
+}
+
 // Simple pseudo-instructions have their lowering (with expansion to real
 // instructions) auto-generated.
 #include "RISCVGenMCPseudoLowering.inc"
 
-#define GEN_COMPRESS_INSTR
-#include "RISCVGenCompressInstEmitter.inc"
 void RISCVAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   // Do any auto-generated pseudo lowerings.
   if (emitPseudoExpansionLowering(*OutStreamer, MI))
     return;
 
-  MCInst TmpInst, CInst;
+  MCInst TmpInst;
   LowerRISCVMachineInstrToMCInst(MI, TmpInst, *this);
-  bool Res = compressInst(CInst, TmpInst, *TM.getMCSubtargetInfo(),
-                          OutStreamer->getContext());
-  EmitToStreamer(*OutStreamer, Res ? CInst : TmpInst);
+  EmitToStreamer(*OutStreamer, TmpInst);
 }
 
 bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                       unsigned AsmVariant,
                                       const char *ExtraCode, raw_ostream &OS) {
   if (AsmVariant != 0)
     report_fatal_error("There are no defined alternate asm variants");
 

test/CodeGen/RISCV/compress-Pseudo.ll

+; RUN: llc -mtriple=riscv32 -mattr=+c  -riscv-no-aliases -o %t1 < %s
+; RUN: FileCheck %s < %t1
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK:   c.jr
+
+end:
+  ret void
+}