[RISCV] Hooks for enabling instruction compression

[sabuasal]

Summary

This patch inserts calls in RISCV backend to call instruction
compression\uncompression logic.

Calls were inserted in three locations:
1) RISCVAsmParser::MatchAndEmitInstruction:
    Inserted a call to compressInst() to compresses instructions
    parsed by llvm-mc coming from an ASM input.
 2) RISCVAsmPrinter::EmitInstruction:
     Inserted a call to compressInst() to compress instructions coming
     that were lowered from Machine Instructions (MachineInstr).
  3) RVInstPrinter::printInst:
      Inserted a call to uncompressInst() to print the expanded
      version of the instruction instead of the compressed one (e.g,
      add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
      is not passed.

[asb]

Thanks Ana for outlining your current thinking. Without reviewing the fine details, this seems in the direction we were all discussing.

Although in the current GNU tools control of compression/decompression is intrinsically linked to the -M no-aliases flag, we might want to add some more fine-grained control here (after all, it seems reasonable that I'd want to disable automatic compression but still use pseudoinstructions like mv). Something we can think about later though.

lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp

47

I think the logic should actually be the other way - we uncompress if !NoAliases (i.e. by default if we decode a c.addi we print it as addi)

[apazos]

Rebased - depends on Shiva's https://reviews.llvm.org/D41658

[apazos]

Also depends on the WIP in https://reviews.llvm.org/D42228

[sabuasal]

lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp

47

Hi Alex,

I think we are actually in agreement. If we have an encoded c.addi and -riscv-noaliases is passed, NoAlias will be true, uncompress will not be called so we print the c.addi.

[efriedma]

lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

52 ↗

(On Diff #132297)

I'm not sure it makes sense to do compression here. Software using the MC layer should have full control over what instructions it's emitting, where possible. And to get the right output with "-riscv-no-aliases", you have to run compression before you output assembly.

If the backend is okay delaying compression until really late, maybe you could call it in LowerRISCVMachineInstrToMCInst() or something like that?

[asb]

lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp

47

We are now in agreement - the logic was the other way around in the original diff. I don't see a way to mark my comment on someone else's patch as 'done' - but it's fine now.

50–52

I think const_cast would be preferable here. Pehaps we could get rid of Res ? (const MCInst *)&NewMI : MI which makes it harder to read - maybe using a MCInst* that is initialised to MI and updated to &NewMI if necessary.

lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

52 ↗

(On Diff #132297)

It's important that we reuse the same MCInst->MCInst mapping both for the codegen and assembly/disassembly path, but you're right - it seems like it would be viable to call this in LowerRISCVMachineInstrToMCInst - doing the usual lowering and then trying to transform OutMI. Do you see any issues with that Ana/Sameer?

[apazos]

lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

53 ↗

(On Diff #132297)

The instruction will only be transformed if compression extension is enabled.
If the user enables compression, but does not want a particular instruction to be compressed, RISCV has no assembler directive to allow that (does it Alex? Maybe we can request that feature?). As Eli knows ARM supports "adds.w" to allow that kind of fine grain control.
We need to also check if LowerRISCVMachineInstrToMCInst is invoked when coming from assembly/disassembly path.

[sabuasal]

lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

52 ↗

(On Diff #132297)

@efriedma @asb

"LowerRISCVMachineInstrToMCInst" Is not on the path for the Assembler\Disassembler (llvm-mc). Adding compression logic there will result in llvm-mc not compressing instructions passed from an ASM file. The reason compression changes where added to the streamer is because it is the onlt location where all paths (Assembler. MI lowering) meet.

[apazos]

Addressed formatting comments.

[sabuasal]

lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp

50–52

Done.

[asb]

Adding llvm-commits as a subscriber. A couple more comments inline

lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

52 ↗

(On Diff #132297)

I recognise LowerRISCVMachineInstrToMCInst won't be called on the llvm-mc path, but this patch does add calls to the asm parser and instprinter, which at first glance seems sufficient for the llvm-mc case. Is that not so? It's been a while since I looked at this part of the instruction compression discussion, so I might be missing/forgetting something.

Updating this diff with a patch summary briefly explaining the locations compressInst is called would be helpful.

53 ↗

(On Diff #132297)

There is no current directive to control automatic compression separately from support for the C extension. If you want to compile an assembly file with support for the C extension but have complete control over when compressed instructions are chosen you currently need to use .option rvc and .option norvc (in gas - not yet implemented in llvm-mc). e.g.

.option norvc
addi x1, x1, 1
.option rvc
c.addi x1, 1

[asb]

lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

53 ↗

(On Diff #132297)

I do think it would be good to have an option for this. I identified this lack in https://github.com/riscv/riscv-toolchain-conventions#issues-for-consideration-4, and it would probably be worth trying again to engage the GCC devs and RISC-V community in trying to address some of the holes detailed in my toolchain-conventions document.

[apazos]

We need to put in the debugger to double check the flow, I recall this flow:
.s ->.o
AsmParser.cpp ->...-> RISCVAsmParser::MatchAndEmitInstruction-> MatchInstructionImpl-> Out.EmitInstruction…
.o->.s
Disassemble.cpp -> ... ->Streamer.EmitInstruction(Inst, STI);-> InstPrinter->printInst(&Inst, OS, "", STI);-> printInstruction(MI, STI, O) in RISCVInstrPrinter

The goal was to try to compress the instr before emitting the instr. And uncompress the instr when printing, depending on the alias flag.

[sabuasal]

lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

52 ↗

(On Diff #132297)

I added a summary for why every hook was added to the patch.

For the llvm-mc and llvm-objdump path having the hooks in AsmParser and in Instr Printer is sufficient for what we are trying to achieve.

The hook to the Elfstreamer was added for the path on 1.c ---> 1.o. This could be moved earlier like @efriedma suggested (I tried it by calling compression in RISCVAsmPrinter::EmitInstruction right after it calls LowerRISCVMachineInstrToMCInst). This also has another advantage of saving a call to compressInst for the path (1.s ---> 1.o); as is compressInst will be called both at the AsmParster and at the ELfStreamer.

However, the only possible side effect is that we will no longer be matching the gcc fronted in this. going from a (1.c ---> 1.s) gcc never emits a compressed asm instruction. While clang can do that if we pass -riscv-no-aliases. The gcc equivilent flag for this (-M -no-aliases) only works with gcc-objdump and not the fronted.

If we don't forsee this as an issue then we can move the hook with no problem.

[asb]

lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

52 ↗

(On Diff #132297)

Thanks for confirming Sameer. Moving earlier, to e.g. LowerRISCVMachineInstrToMCInst seems preferable.

I think the fact we can have -riscv-no-aliases affect .s emission is an advantage vs GCC.

[sabuasal]

Removed the call to EmitInstr in ELFStream.
Updated test cases.

[asb]

This diff seems to have accidentally picked up changes to a number of tests.

Other than that, this looks good to me. I expect that in the future we'll want to have the option of having the C extension enabled but not performing automatic compression, but that can always be added later.

[sabuasal]

Hi Alex,

Thanks for the review,

Yes, the changes in the test cases are caused by the fact that I rebased on the latest llvm (with mc relaxation enabled).

[sabuasal]

Committed with: https://reviews.llvm.org/D45385

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
+// Include the auto-generated portion of the compress emitter.
+#define GEN_COMPRESS_INSTR
+#include "RISCVGenCompressInstEmitter.inc"
+
 namespace {
 struct RISCVOperand;
 
 class RISCVAsmParser : public MCTargetAsmParser {
   SMLoc getLoc() const { return getParser().getTok().getLoc(); }
   bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); }
 
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                              MCStreamer &Out,
                                              uint64_t &ErrorInfo,
                                              bool MatchingInlineAsm) {
   MCInst Inst;
 
   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
   default:
     break;
-  case Match_Success:
+  case Match_Success: {
+    MCInst CInst;
+    bool Res = compressInst(CInst, Inst, getSTI(), Out.getContext());
+    CInst.setLoc(IDLoc);
     Inst.setLoc(IDLoc);
-    Out.EmitInstruction(Inst, getSTI());
+    Out.EmitInstruction((Res ? CInst : Inst), getSTI());
     return false;
+  }
   case Match_MissingFeature:
     return Error(IDLoc, "instruction use requires an option to be enabled");
   case Match_MnemonicFail:
     return Error(IDLoc, "unrecognized instruction mnemonic");
   case Match_InvalidOperand: {
     SMLoc ErrorLoc = IDLoc;
     if (ErrorInfo != ~0U) {
       if (ErrorInfo >= Operands.size())

lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp

 using namespace llvm;
 
 #define DEBUG_TYPE "asm-printer"
 
 // Include the auto-generated portion of the assembly writer.
 #define PRINT_ALIAS_INSTR
 #include "RISCVGenAsmWriter.inc"
 
+// Include the auto-generated portion of the compress emitter.
+#define GEN_UNCOMPRESS_INSTR
+#include "RISCVGenCompressInstEmitter.inc"
+
 static cl::opt<bool>
 NoAliases("riscv-no-aliases",
             cl::desc("Disable the emission of assembler pseudo instructions"),
             cl::init(false),
             cl::Hidden);
 
 void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
                                  StringRef Annot, const MCSubtargetInfo &STI) {
-  if (NoAliases || !printAliasInstr(MI, STI, O))
-    printInstruction(MI, STI, O);
+  bool Res = false;
+  const MCInst *NewMI = MI;
+  MCInst UncompressedMI;
+  if (!NoAliases)
+    Res = uncompressInst(UncompressedMI, *MI, MRI, STI);
+  if (Res)
+    NewMI = const_cast<MCInst*>(&UncompressedMI);
+  if (NoAliases || !printAliasInstr(NewMI, STI, O))
+    printInstruction(NewMI, STI, O);
   printAnnotation(O, Annot);
 }
 
 void RISCVInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
   O << getRegisterName(RegNo);
 }
 
 void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,

lib/Target/RISCV/RISCVAsmPrinter.cpp

 //===-- RISCVAsmPrinter.cpp - RISCV LLVM assembly writer ------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains a printer that converts from our internal representation
 // of machine-dependent LLVM code to the RISCV assembly language.
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCV.h"
 #include "InstPrinter/RISCVInstPrinter.h"
+#include "MCTargetDesc/RISCVMCExpr.h"
 #include "RISCVTargetMachine.h"
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCInst.h"
public:
   }
 };
 }
 
 // Simple pseudo-instructions have their lowering (with expansion to real
 // instructions) auto-generated.
 #include "RISCVGenMCPseudoLowering.inc"
 
+#define GEN_COMPRESS_INSTR
+#include "RISCVGenCompressInstEmitter.inc"
 void RISCVAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   // Do any auto-generated pseudo lowerings.
   if (emitPseudoExpansionLowering(*OutStreamer, MI))
     return;
 
-  MCInst TmpInst;
+  MCInst TmpInst, CInst;
   LowerRISCVMachineInstrToMCInst(MI, TmpInst, *this);
-  EmitToStreamer(*OutStreamer, TmpInst);
+  bool Res = compressInst(CInst, TmpInst, *TM.getMCSubtargetInfo(),
+                          OutStreamer->getContext());
+  EmitToStreamer(*OutStreamer, Res ? CInst : TmpInst);
 }
 
 bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                       unsigned AsmVariant,
                                       const char *ExtraCode, raw_ostream &OS) {
   if (AsmVariant != 0)
     report_fatal_error("There are no defined alternate asm variants");
 

test/MC/RISCV/compressed-relocations.s

+# RUN: llvm-mc -triple riscv32 -mattr=+c -riscv-no-aliases < %s -show-encoding \
+# RUN:     | FileCheck -check-prefix=INSTR -check-prefix=FIXUP %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
+# RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
+
+# Check prefixes:
+# RELOC - Check the relocation in the object.
+# FIXUP - Check the fixup on the instruction.
+# INSTR - Check the instruction is handled properly by the ASMPrinter
+c.jal foo
+# A compressed jump (c.j) to an unresolved symbol will be relaxed to a (jal).
+# RELOC: R_RISCV_JAL
+# INSTR: c.jal foo
+# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_rvc_jump
+
+c.bnez a0, foo
+# A compressed branch (c.bnez) to an unresolved symbol will be relaxed to a (bnez).
+# RELOC: R_RISCV_BRANCH
+# INSTR: c.bnez a0, foo
+# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_rvc_branch

test/MC/RISCV/fixups-compressed.s

 # RUN: llvm-mc %s -triple riscv32 -mattr=+c -show-encoding \
 # RUN:     | FileCheck -check-prefix=CHECK-FIXUP %s
 # RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c < %s \
-# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INSTR %s
+# RUN:     | llvm-objdump -d -riscv-no-aliases - | FileCheck -check-prefix=CHECK-INSTR %s
 # RUN: llvm-mc -filetype=obj -mattr=+c -triple=riscv32 %s \
 # RUN:     | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
 
 .LBB0_2:
 # CHECK-FIXUP:   fixup A - offset: 0, value: .LBB0_2, kind: fixup_riscv_rvc_jump
 # CHECK-INSTR: c.j     0
 c.j     .LBB0_2
 # CHECK:   fixup A - offset: 0, value: func1, kind: fixup_riscv_rvc_jump

test/MC/RISCV/relocations.s

-# RUN: llvm-mc -triple riscv32 -mattr=+c -riscv-no-aliases < %s -show-encoding \
+# RUN: llvm-mc -triple riscv32 -riscv-no-aliases < %s -show-encoding \
 # RUN:     | FileCheck -check-prefix=INSTR -check-prefix=FIXUP %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
 # RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
 
 # Check prefixes:
 # RELOC - Check the relocation in the object.
 # FIXUP - Check the fixup on the instruction.
 # INSTR - Check the instruction is handled properly by the ASMPrinter

 # RELOC: R_RISCV_JAL
 # INSTR: jal zero, foo
 # FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_jal
 
 bgeu a0, a1, foo
 # RELOC: R_RISCV_BRANCH
 # INSTR: bgeu a0, a1, foo
 # FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_branch
-
-c.jal foo
-# A compressed jump (c.j) to an unresolved symbol will be relaxed to a (jal).
-# RELOC: R_RISCV_JAL
-# INSTR: c.jal foo
-# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_rvc_jump
-
-c.bnez a0, foo
-# A compressed branch (c.bnez) to an unresolved symbol will be relaxed to a (bnez).
-# RELOC: R_RISCV_BRANCH
-# INSTR: c.bnez a0, foo
-# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_rvc_branch

test/MC/RISCV/rv32-relaxation.s

 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
-# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=INSTR %s
+# RUN:     | llvm-objdump -d -riscv-no-aliases - | FileCheck -check-prefix=INSTR %s
 
 FAR_JUMP_NEGATIVE:
   c.nop
 .space 2000
 
 FAR_BRANCH_NEGATIVE:
   c.nop
 .space 256
 
 NEAR_NEGATIVE:
   c.nop
 
 start:
   c.bnez a0, NEAR
 #INSTR: c.bnez a0, 72
   c.bnez a0, NEAR_NEGATIVE
 #INSTR: c.bnez a0, -4
   c.bnez a0, FAR_BRANCH
-#INSTR-NEXT: bnez a0, 326
+#INSTR-NEXT: bne a0, zero, 326
   c.bnez a0, FAR_BRANCH_NEGATIVE
-#INSTR-NEXT: bnez a0, -268
+#INSTR-NEXT: bne a0, zero, -268
   c.bnez a0, FAR_JUMP
-#INSTR-NEXT: bnez a0, 2320
+#INSTR-NEXT: bne a0, zero, 2320
   c.bnez a0, FAR_JUMP_NEGATIVE
-#INSTR-NEXT: bnez a0, -2278
+#INSTR-NEXT: bne a0, zero, -2278
 
   c.beqz a0, NEAR
 #INSTR-NEXT: c.beqz a0, 52
   c.beqz a0, NEAR_NEGATIVE
 #INSTR-NEXT: c.beqz a0, -24
   c.beqz a0, FAR_BRANCH
-#INSTR-NEXT: beqz a0, 306
+#INSTR-NEXT: beq a0, zero, 306
   c.beqz a0, FAR_BRANCH_NEGATIVE
-#INSTR-NEXT: beqz a0, -288
+#INSTR-NEXT: beq a0, zero, -288
   c.beqz a0, FAR_JUMP
-#INSTR-NEXT: beqz a0, 2300
+#INSTR-NEXT: beq a0, zero, 2300
   c.beqz a0, FAR_JUMP_NEGATIVE
-#INSTR-NEXT: beqz a0, -2298
+#INSTR-NEXT: beq a0, zero, -2298
 
   c.j NEAR
 #INSTR-NEXT: c.j 32
   c.j NEAR_NEGATIVE
 #INSTR-NEXT: c.j -44
   c.j FAR_BRANCH
 #INSTR-NEXT: c.j 286
   c.j FAR_BRANCH_NEGATIVE
 #INSTR-NEXT: c.j -306
   c.j FAR_JUMP
-#INSTR-NEXT: j 2284
+#INSTR-NEXT: jal zero, 2284
   c.j FAR_JUMP_NEGATIVE
-#INSTR-NEXT: j -2314
+#INSTR-NEXT: jal zero, -2314
 
   c.jal NEAR
 #INSTR: c.jal 16
   c.jal NEAR_NEGATIVE
 #INSTR: c.jal -60
   c.jal FAR_BRANCH
 #INSTR-NEXT: c.jal 270
   c.jal FAR_BRANCH_NEGATIVE
 #INSTR-NEXT: c.jal -322
   c.jal FAR_JUMP
-#INSTR-NEXT: jal 2268
+#INSTR-NEXT: jal ra, 2268
   c.jal FAR_JUMP_NEGATIVE
-#INSTR-NEXT: jal -2330
+#INSTR-NEXT: jal ra, -2330
 
 NEAR:
   c.nop
 .space 256
 FAR_BRANCH:
   c.nop
 .space 2000
 FAR_JUMP:
   c.nop

test/MC/RISCV/rv64-relaxation.s

 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c < %s \
-# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=INSTR %s
+# RUN:     | llvm-objdump -d -riscv-no-aliases - | FileCheck -check-prefix=INSTR %s
 
 FAR_JUMP_NEGATIVE:
   c.nop
 .space 2000
 
 FAR_BRANCH_NEGATIVE:
   c.nop
 .space 256
 
 NEAR_NEGATIVE:
   c.nop
 
 start:
   c.bnez a0, NEAR
 #INSTR: c.bnez a0, 56
   c.bnez a0, NEAR_NEGATIVE
 #INSTR: c.bnez a0, -4
   c.bnez a0, FAR_BRANCH
-#INSTR-NEXT: bnez a0, 310
+#INSTR-NEXT: bne a0, zero, 310
   c.bnez a0, FAR_BRANCH_NEGATIVE
-#INSTR-NEXT: bnez a0, -268
+#INSTR-NEXT: bne a0, zero, -268
   c.bnez a0, FAR_JUMP
-#INSTR-NEXT: bnez a0, 2304
+#INSTR-NEXT: bne a0, zero, 2304
   c.bnez a0, FAR_JUMP_NEGATIVE
-#INSTR-NEXT: bnez a0, -2278
+#INSTR-NEXT: bne a0, zero, -2278
 
   c.beqz a0, NEAR
 #INSTR-NEXT: c.beqz a0, 36
   c.beqz a0, NEAR_NEGATIVE
 #INSTR-NEXT: c.beqz a0, -24
   c.beqz a0, FAR_BRANCH
-#INSTR-NEXT: beqz a0, 290
+#INSTR-NEXT: beq a0, zero, 290
   c.beqz a0, FAR_BRANCH_NEGATIVE
-#INSTR-NEXT: beqz a0, -288
+#INSTR-NEXT: beq a0, zero, -288
   c.beqz a0, FAR_JUMP
-#INSTR-NEXT: beqz a0, 2284
+#INSTR-NEXT: beq a0, zero, 2284
   c.beqz a0, FAR_JUMP_NEGATIVE
-#INSTR-NEXT: beqz a0, -2298
+#INSTR-NEXT: beq a0, zero, -2298
 
   c.j NEAR
 #INSTR-NEXT: c.j 16
   c.j NEAR_NEGATIVE
 #INSTR-NEXT: c.j -44
   c.j FAR_BRANCH
 #INSTR-NEXT: c.j 270
   c.j FAR_BRANCH_NEGATIVE
 #INSTR-NEXT: c.j -306
   c.j FAR_JUMP
-#INSTR-NEXT: j 2268
+#INSTR-NEXT: jal zero, 2268
   c.j FAR_JUMP_NEGATIVE
-#INSTR-NEXT: j -2314
+#INSTR-NEXT: jal zero, -2314
 
 NEAR:
   c.nop
 
 .space 256
 FAR_BRANCH:
   c.nop
 
 .space 2000
 FAR_JUMP:
   c.nop