This is an archive of the discontinued LLVM Phabricator instance.

[RISCV] Tablegen-driven Instruction Compression.
ClosedPublic

Authored by sabuasal on Apr 6 2018, 12:11 PM.

Details

Summary
This patch implements a tablegen-driven Instruction Compression
mechanism for generating RISCV compressed instructions
(C Extension) from the expanded instruction form.

This tablegen backend processes CompressPat declarations in a
td file and generates all the compile-time and runtime checks
required to validate the declarations, validate the input
operands and generate correct instructions.

The checks include validating register operands, immediate
operands, fixed register operands and fixed immediate operands.

Example:
  class CompressPat<dag input, dag output> {
    dag Input  = input;
    dag Output    = output;
    list<Predicate> Predicates = [];
  }

  let Predicates = [HasStdExtC] in {
  def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
                    (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
  }

The result is an auto-generated header file
'RISCVGenCompressEmitter.inc' which exports two functions for
compressing/uncompressing MCInst instructions, plus
some helper functions:

  bool compressInst(MCInst& OutInst, const MCInst &MI,
                    const MCSubtargetInfo &STI,
                    MCContext &Context);

  bool uncompressInst(MCInst& OutInst, const MCInst &MI,
                      const MCRegisterInfo &MRI,
                      const MCSubtargetInfo &STI);

The clients that include this auto-generated header file and
invoke these functions can compress an instruction before emitting
it, in the target-specific ASM or ELF streamer, or can uncompress
an instruction before printing it, when the expanded instruction
format aliases is favored.

The following clients were added to implement compression\uncompression
for RISCV:

1) RISCVAsmParser::MatchAndEmitInstruction:
   Inserted a call to compressInst() to compresses instructions
   parsed by llvm-mc coming from an ASM input.
2) RISCVAsmPrinter::EmitInstruction:
   Inserted a call to compressInst() to compress instructions that
   were lowered from Machine Instructions (MachineInstr).
3) RVInstPrinter::printInst:
   Inserted a call to uncompressInst() to print the expanded
   version of the instruction instead of the compressed one (e.g,
   add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
   is not passed.

This patch squashes D45119 , D42780 and D41932. it was reviewed in smaller patches.

Diff Detail

Repository
rL LLVM

Event Timeline

sabuasal created this revision.Apr 6 2018, 12:11 PM
sabuasal accepted this revision.Apr 6 2018, 12:12 PM
sabuasal added reviewers: asb, efriedma, apazos, llvm-commits.

Patch was reviewed in D45119 , D42780 and D41932.

This revision is now accepted and ready to land.Apr 6 2018, 12:13 PM
sabuasal updated this revision to Diff 141401.Apr 6 2018, 12:15 PM
This revision was automatically updated to reflect the committed changes.