[AMDGPU][MC][DOC] Updated AMD GPU assembler description

[dp]

Summary

See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572

This is the first part of an update.

This change adds description of:

• syntax of all GFX7/8/9 instructions we currently support (and which passed testing);
• instruction modifiers.

For your convenience, the change is also included in html format.

AMDGPUUsage_v01.zip241 KBDownload

In the next update I'm planning to add a description of operands.

[vpykhtin]

I think it looks very good, thank you!

[artem.tamazov]

LGTM

llvm/trunk/docs/AMDGPUAsmGFX7.rst

+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+===========================
+Syntax of GFX7 Instructions
+===========================
+
+.. contents::
+  :local:
+
+
+DS
+===========================
+
+.. parsed-literal::
+
+    ds_add_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_b32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_b64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_rtn_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_rtn_b64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_src2_b32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_src2_b64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_append                      dst                            :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_b32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_b64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_f32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_f64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_b32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_b64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_f32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_f64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_condxchg32_rtn_b64          dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_consume                     dst                            :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_barrier                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_init                    src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_br                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_p                  src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_release_all        src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_v                  src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_f64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_i32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_i64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_f64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_i32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_i64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_f32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_f64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_i32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_i64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_f64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_i32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_i64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_f64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_i32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_i64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_f32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_f64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_i32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_i64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_b32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_b64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_rtn_b32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_rtn_b64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_nop                         src0
+    ds_or_b32                      src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_b64                      src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_rtn_b32                  dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_rtn_b64                  dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_src2_b32                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_src2_b64                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_ordered_count               dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2_b32                   dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2_b64                   dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2st64_b32               dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2st64_b64               dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b128                   dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b32                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b64                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b96                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i16                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i8                     dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u16                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u8                     dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_rtn_u32                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_rtn_u64                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_src2_u32               src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_src2_u64               src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_u32                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_u64                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_swizzle_b32                 dst, src0                      :ref:`sw_offset16<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrap_rtn_b32                dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2_b32                  src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2_b64                  src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2st64_b32              src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2st64_b64              src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b128                  src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b16                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b32                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b64                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b8                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b96                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_src2_b32              src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_src2_b64              src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2_rtn_b32             dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2_rtn_b64             dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2st64_rtn_b32         dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2st64_rtn_b64         dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg_rtn_b32              dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg_rtn_b64              dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_b32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_b64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_rtn_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_rtn_b64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_src2_b32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_src2_b64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+
+EXP
+===========================
+
+.. parsed-literal::
+
+    exp                            dst, src0, src1, src2, src3    :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
+
+FLAT
+===========================
+
+.. parsed-literal::
+
+    flat_atomic_add                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_add_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_and                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_and_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_cmpswap            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_cmpswap_x2         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_dec                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_dec_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fcmpswap           dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fcmpswap_x2        dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fmax               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fmax_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fmin               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fmin_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_inc                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_inc_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_or                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_or_x2              dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smax               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smax_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smin               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smin_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_sub                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_sub_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_swap               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_swap_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umax               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umax_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umin               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umin_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_xor                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_xor_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dword                dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx2              dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx3              dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx4              dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sbyte                dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sshort               dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ubyte                dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ushort               dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_byte                src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dword               src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx2             src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx3             src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx4             src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_short               src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
+MIMG
+===========================
+
+.. parsed-literal::
+
+    image_atomic_add               src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_and               src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_cmpswap           src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_dec               src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_inc               src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_or                src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_smax              src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_smin              src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_sub               src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_swap              src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_umax              src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_umin              src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_xor               src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4                  dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_b                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_b_cl             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_b_cl_o           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_b_o              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_b              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_b_cl           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_b_cl_o         dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_b_o            dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_cl             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_cl_o           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_l              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_l_o            dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_lz             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_lz_o           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_o              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_cl               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_cl_o             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_l                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_l_o              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_lz               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_lz_o             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_o                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_get_lod                  dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_get_resinfo              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load                     dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_mip                 dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample                   dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_b                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_b_cl              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_b               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_b_cl            dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_cd              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_cl              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_d               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_l               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_lz              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_cl                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_l                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_lz                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_store                    src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_store_mip                src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+
+MUBUF
+===========================
+
+.. parsed-literal::
+
+    buffer_atomic_add              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_add_x2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and_x2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap_x2       src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec_x2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc_x2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or               src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or_x2            src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax_x2          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin_x2          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub_x2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap_x2          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax_x2          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin_x2          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor_x2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dword              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_dwordx2            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dwordx3            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dwordx4            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_x           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_format_xy          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_xyz         dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_xyzw        dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_sbyte              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_sshort             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_ubyte              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_ushort             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_store_byte              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dword             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx3           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx4           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_x          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xy         src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyz        src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyzw       src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_short             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_wbinvl1
+    buffer_wbinvl1_vol
+
+SMRD
+===========================
+
+.. parsed-literal::
+
+    s_buffer_load_dword            dst, src0, src1
+    s_buffer_load_dwordx16         dst, src0, src1
+    s_buffer_load_dwordx2          dst, src0, src1
+    s_buffer_load_dwordx4          dst, src0, src1
+    s_buffer_load_dwordx8          dst, src0, src1
+    s_dcache_inv
+    s_dcache_inv_vol
+    s_load_dword                   dst, src0, src1
+    s_load_dwordx16                dst, src0, src1
+    s_load_dwordx2                 dst, src0, src1
+    s_load_dwordx4                 dst, src0, src1
+    s_load_dwordx8                 dst, src0, src1
+    s_memtime                      dst
+
+SOP1
+===========================
+
+.. parsed-literal::
+
+    s_abs_i32                      dst, src0
+    s_and_saveexec_b64             dst, src0
+    s_andn2_saveexec_b64           dst, src0
+    s_bcnt0_i32_b32                dst, src0
+    s_bcnt0_i32_b64                dst, src0
+    s_bcnt1_i32_b32                dst, src0
+    s_bcnt1_i32_b64                dst, src0
+    s_bitset0_b32                  dst, src0
+    s_bitset0_b64                  dst, src0
+    s_bitset1_b32                  dst, src0
+    s_bitset1_b64                  dst, src0
+    s_brev_b32                     dst, src0
+    s_brev_b64                     dst, src0
+    s_cbranch_join                 src0
+    s_cmov_b32                     dst, src0
+    s_cmov_b64                     dst, src0
+    s_ff0_i32_b32                  dst, src0
+    s_ff0_i32_b64                  dst, src0
+    s_ff1_i32_b32                  dst, src0
+    s_ff1_i32_b64                  dst, src0
+    s_flbit_i32                    dst, src0
+    s_flbit_i32_b32                dst, src0
+    s_flbit_i32_b64                dst, src0
+    s_flbit_i32_i64                dst, src0
+    s_getpc_b64                    dst
+    s_mov_b32                      dst, src0
+    s_mov_b64                      dst, src0
+    s_mov_fed_b32                  dst, src0
+    s_movreld_b32                  dst, src0
+    s_movreld_b64                  dst, src0
+    s_movrels_b32                  dst, src0
+    s_movrels_b64                  dst, src0
+    s_nand_saveexec_b64            dst, src0
+    s_nor_saveexec_b64             dst, src0
+    s_not_b32                      dst, src0
+    s_not_b64                      dst, src0
+    s_or_saveexec_b64              dst, src0
+    s_orn2_saveexec_b64            dst, src0
+    s_quadmask_b32                 dst, src0
+    s_quadmask_b64                 dst, src0
+    s_rfe_b64                      src0
+    s_setpc_b64                    src0
+    s_sext_i32_i16                 dst, src0
+    s_sext_i32_i8                  dst, src0
+    s_swappc_b64                   dst, src0
+    s_wqm_b32                      dst, src0
+    s_wqm_b64                      dst, src0
+    s_xnor_saveexec_b64            dst, src0
+    s_xor_saveexec_b64             dst, src0
+
+SOP2
+===========================
+
+.. parsed-literal::
+
+    s_absdiff_i32                  dst, src0, src1
+    s_add_i32                      dst, src0, src1
+    s_add_u32                      dst, src0, src1
+    s_addc_u32                     dst, src0, src1
+    s_and_b32                      dst, src0, src1
+    s_and_b64                      dst, src0, src1
+    s_andn2_b32                    dst, src0, src1
+    s_andn2_b64                    dst, src0, src1
+    s_ashr_i32                     dst, src0, src1
+    s_ashr_i64                     dst, src0, src1
+    s_bfe_i32                      dst, src0, src1
+    s_bfe_i64                      dst, src0, src1
+    s_bfe_u32                      dst, src0, src1
+    s_bfe_u64                      dst, src0, src1
+    s_bfm_b32                      dst, src0, src1
+    s_bfm_b64                      dst, src0, src1
+    s_cbranch_g_fork               src0, src1
+    s_cselect_b32                  dst, src0, src1
+    s_cselect_b64                  dst, src0, src1
+    s_lshl_b32                     dst, src0, src1
+    s_lshl_b64                     dst, src0, src1
+    s_lshr_b32                     dst, src0, src1
+    s_lshr_b64                     dst, src0, src1
+    s_max_i32                      dst, src0, src1
+    s_max_u32                      dst, src0, src1
+    s_min_i32                      dst, src0, src1
+    s_min_u32                      dst, src0, src1
+    s_mul_i32                      dst, src0, src1
+    s_nand_b32                     dst, src0, src1
+    s_nand_b64                     dst, src0, src1
+    s_nor_b32                      dst, src0, src1
+    s_nor_b64                      dst, src0, src1
+    s_or_b32                       dst, src0, src1
+    s_or_b64                       dst, src0, src1
+    s_orn2_b32                     dst, src0, src1
+    s_orn2_b64                     dst, src0, src1
+    s_sub_i32                      dst, src0, src1
+    s_sub_u32                      dst, src0, src1
+    s_subb_u32                     dst, src0, src1
+    s_xnor_b32                     dst, src0, src1
+    s_xnor_b64                     dst, src0, src1
+    s_xor_b32                      dst, src0, src1
+    s_xor_b64                      dst, src0, src1
+
+SOPC
+===========================
+
+.. parsed-literal::
+
+    s_bitcmp0_b32                  src0, src1
+    s_bitcmp0_b64                  src0, src1
+    s_bitcmp1_b32                  src0, src1
+    s_bitcmp1_b64                  src0, src1
+    s_cmp_eq_i32                   src0, src1
+    s_cmp_eq_u32                   src0, src1
+    s_cmp_ge_i32                   src0, src1
+    s_cmp_ge_u32                   src0, src1
+    s_cmp_gt_i32                   src0, src1
+    s_cmp_gt_u32                   src0, src1
+    s_cmp_le_i32                   src0, src1
+    s_cmp_le_u32                   src0, src1
+    s_cmp_lg_i32                   src0, src1
+    s_cmp_lg_u32                   src0, src1
+    s_cmp_lt_i32                   src0, src1
+    s_cmp_lt_u32                   src0, src1
+    s_setvskip                     src0, src1
+
+SOPK
+===========================
+
+.. parsed-literal::
+
+    s_addk_i32                     dst, src0
+    s_cbranch_i_fork               src0, src1
+    s_cmovk_i32                    dst, src0
+    s_cmpk_eq_i32                  src0, src1
+    s_cmpk_eq_u32                  src0, src1
+    s_cmpk_ge_i32                  src0, src1
+    s_cmpk_ge_u32                  src0, src1
+    s_cmpk_gt_i32                  src0, src1
+    s_cmpk_gt_u32                  src0, src1
+    s_cmpk_le_i32                  src0, src1
+    s_cmpk_le_u32                  src0, src1
+    s_cmpk_lg_i32                  src0, src1
+    s_cmpk_lg_u32                  src0, src1
+    s_cmpk_lt_i32                  src0, src1
+    s_cmpk_lt_u32                  src0, src1
+    s_getreg_b32                   dst, src0
+    s_movk_i32                     dst, src0
+    s_mulk_i32                     dst, src0
+    s_setreg_b32                   dst, src0
+    s_setreg_imm32_b32             dst, src0
+
+SOPP
+===========================
+
+.. parsed-literal::
+
+    s_barrier
+    s_branch                       src0
+    s_cbranch_cdbgsys              src0
+    s_cbranch_cdbgsys_and_user     src0
+    s_cbranch_cdbgsys_or_user      src0
+    s_cbranch_cdbguser             src0
+    s_cbranch_execnz               src0
+    s_cbranch_execz                src0
+    s_cbranch_scc0                 src0
+    s_cbranch_scc1                 src0
+    s_cbranch_vccnz                src0
+    s_cbranch_vccz                 src0
+    s_decperflevel                 src0
+    s_endpgm
+    s_icache_inv
+    s_incperflevel                 src0
+    s_nop                          src0
+    s_sendmsg                      src0
+    s_sendmsghalt                  src0
+    s_sethalt                      src0
+    s_setkill                      src0
+    s_setprio                      src0
+    s_sleep                        src0
+    s_trap                         src0
+    s_ttracedata
+    s_waitcnt                      src0
+
+VINTRP
+===========================
+
+.. parsed-literal::
+
+    v_interp_mov_f32               dst, src0, src1
+    v_interp_p1_f32                dst, src0, src1
+    v_interp_p2_f32                dst, src0, src1
+
+VOP1
+===========================
+
+.. parsed-literal::
+
+    v_bfrev_b32                    dst, src0
+    v_ceil_f32                     dst, src0
+    v_ceil_f64                     dst, src0
+    v_clrexcp
+    v_cos_f32                      dst, src0
+    v_cvt_f16_f32                  dst, src0
+    v_cvt_f32_f16                  dst, src0
+    v_cvt_f32_f64                  dst, src0
+    v_cvt_f32_i32                  dst, src0
+    v_cvt_f32_u32                  dst, src0
+    v_cvt_f32_ubyte0               dst, src0
+    v_cvt_f32_ubyte1               dst, src0
+    v_cvt_f32_ubyte2               dst, src0
+    v_cvt_f32_ubyte3               dst, src0
+    v_cvt_f64_f32                  dst, src0
+    v_cvt_f64_i32                  dst, src0
+    v_cvt_f64_u32                  dst, src0
+    v_cvt_flr_i32_f32              dst, src0
+    v_cvt_i32_f32                  dst, src0
+    v_cvt_i32_f64                  dst, src0
+    v_cvt_off_f32_i4               dst, src0
+    v_cvt_rpi_i32_f32              dst, src0
+    v_cvt_u32_f32                  dst, src0
+    v_cvt_u32_f64                  dst, src0
+    v_exp_f32                      dst, src0
+    v_exp_legacy_f32               dst, src0
+    v_ffbh_i32                     dst, src0
+    v_ffbh_u32                     dst, src0
+    v_ffbl_b32                     dst, src0
+    v_floor_f32                    dst, src0
+    v_floor_f64                    dst, src0
+    v_fract_f32                    dst, src0
+    v_fract_f64                    dst, src0
+    v_frexp_exp_i32_f32            dst, src0
+    v_frexp_exp_i32_f64            dst, src0
+    v_frexp_mant_f32               dst, src0
+    v_frexp_mant_f64               dst, src0
+    v_log_clamp_f32                dst, src0
+    v_log_f32                      dst, src0
+    v_log_legacy_f32               dst, src0
+    v_mov_b32                      dst, src0
+    v_mov_fed_b32                  dst, src0
+    v_movreld_b32                  dst, src0
+    v_movrels_b32                  dst, src0
+    v_movrelsd_b32                 dst, src0
+    v_nop
+    v_not_b32                      dst, src0
+    v_rcp_clamp_f32                dst, src0
+    v_rcp_clamp_f64                dst, src0
+    v_rcp_f32                      dst, src0
+    v_rcp_f64                      dst, src0
+    v_rcp_iflag_f32                dst, src0
+    v_rcp_legacy_f32               dst, src0
+    v_readfirstlane_b32            dst, src0
+    v_rndne_f32                    dst, src0
+    v_rndne_f64                    dst, src0
+    v_rsq_clamp_f32                dst, src0
+    v_rsq_clamp_f64                dst, src0
+    v_rsq_f32                      dst, src0
+    v_rsq_f64                      dst, src0
+    v_rsq_legacy_f32               dst, src0
+    v_sin_f32                      dst, src0
+    v_sqrt_f32                     dst, src0
+    v_sqrt_f64                     dst, src0
+    v_trunc_f32                    dst, src0
+    v_trunc_f64                    dst, src0
+
+VOP2
+===========================
+
+.. parsed-literal::
+
+    v_add_f32                      dst, src0, src1
+    v_add_i32                      dst0, dst1, src0, src1
+    v_addc_u32                     dst0, dst1, src0, src1, src2
+    v_and_b32                      dst, src0, src1
+    v_ashr_i32                     dst, src0, src1
+    v_ashrrev_i32                  dst, src0, src1
+    v_bcnt_u32_b32                 dst, src0, src1
+    v_bfm_b32                      dst, src0, src1
+    v_cndmask_b32                  dst, src0, src1, src2
+    v_cvt_pk_i16_i32               dst, src0, src1
+    v_cvt_pk_u16_u32               dst, src0, src1
+    v_cvt_pkaccum_u8_f32           dst, src0, src1
+    v_cvt_pknorm_i16_f32           dst, src0, src1
+    v_cvt_pknorm_u16_f32           dst, src0, src1
+    v_cvt_pkrtz_f16_f32            dst, src0, src1
+    v_ldexp_f32                    dst, src0, src1
+    v_lshl_b32                     dst, src0, src1
+    v_lshlrev_b32                  dst, src0, src1
+    v_lshr_b32                     dst, src0, src1
+    v_lshrrev_b32                  dst, src0, src1
+    v_mac_f32                      dst, src0, src1
+    v_mac_legacy_f32               dst, src0, src1
+    v_madak_f32                    dst, src0, src1, src2
+    v_madmk_f32                    dst, src0, src1, src2
+    v_max_f32                      dst, src0, src1
+    v_max_i32                      dst, src0, src1
+    v_max_legacy_f32               dst, src0, src1
+    v_max_u32                      dst, src0, src1
+    v_mbcnt_hi_u32_b32             dst, src0, src1
+    v_mbcnt_lo_u32_b32             dst, src0, src1
+    v_min_f32                      dst, src0, src1
+    v_min_i32                      dst, src0, src1
+    v_min_legacy_f32               dst, src0, src1
+    v_min_u32                      dst, src0, src1
+    v_mul_f32                      dst, src0, src1
+    v_mul_hi_i32_i24               dst, src0, src1
+    v_mul_hi_u32_u24               dst, src0, src1
+    v_mul_i32_i24                  dst, src0, src1
+    v_mul_legacy_f32               dst, src0, src1
+    v_mul_u32_u24                  dst, src0, src1
+    v_or_b32                       dst, src0, src1
+    v_readlane_b32                 dst, src0, src1
+    v_sub_f32                      dst, src0, src1
+    v_sub_i32                      dst0, dst1, src0, src1
+    v_subb_u32                     dst0, dst1, src0, src1, src2
+    v_subbrev_u32                  dst0, dst1, src0, src1, src2
+    v_subrev_f32                   dst, src0, src1
+    v_subrev_i32                   dst0, dst1, src0, src1
+    v_writelane_b32                dst, src0, src1
+    v_xor_b32                      dst, src0, src1
+
+VOP3
+===========================
+
+.. parsed-literal::
+
+    v_add_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_i32_e64                  dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
+    v_addc_u32_e64                 dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_alignbit_b32                 dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_alignbyte_b32                dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_and_b32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_ashr_i32_e64                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_ashr_i64                     dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_ashrrev_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_bcnt_u32_b32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_bfe_i32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_bfe_u32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_bfi_b32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_bfm_b32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_bfrev_b32_e64                dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_ceil_f32_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ceil_f64_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_clrexcp_e64                                                 :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_class_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_class_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_f32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_f64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_i32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_i64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_u32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_u64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lg_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lg_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_neq_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_neq_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nge_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nge_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ngt_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ngt_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nle_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nle_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlg_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlg_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlt_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlt_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_o_f32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_o_f64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_i32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_i64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_u32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_u64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_tru_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_tru_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_u_f32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_u_f64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_eq_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_eq_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_f_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_f_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_ge_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_ge_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_gt_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_gt_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_le_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_le_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_lg_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_lg_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_lt_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_lt_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_neq_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_neq_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_nge_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_nge_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_ngt_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_ngt_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_nle_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_nle_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_nlg_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_nlg_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_nlt_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_nlt_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_o_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_o_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_tru_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_tru_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_u_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmps_u_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_eq_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_eq_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_f_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_f_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_ge_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_ge_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_gt_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_gt_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_le_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_le_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_lg_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_lg_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_lt_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_lt_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_neq_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_neq_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_nge_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_nge_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_ngt_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_ngt_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_nle_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_nle_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_nlg_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_nlg_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_nlt_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_nlt_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_o_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_o_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_tru_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_tru_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_u_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpsx_u_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_class_f32_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_class_f64_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lg_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lg_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_f32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_f64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_neq_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_neq_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nge_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nge_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ngt_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ngt_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nle_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nle_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlg_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlg_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlt_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlt_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_o_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_o_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_tru_f32_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_tru_f64_e64             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_u_f32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_u_f64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cndmask_b32_e64              dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_cos_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubeid_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubema_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubesc_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubetc_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_f32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_f16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_f64_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_i32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_u32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte0_e64           dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte1_e64           dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte2_e64           dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte3_e64           dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_f32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_i32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_u32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_flr_i32_f32_e64          dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_i32_f32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_i32_f64_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_off_f32_i4_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_i16_i32_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_u16_u32_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_u8_f32                dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pkaccum_u8_f32_e64       dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pknorm_i16_f32_e64       dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pknorm_u16_f32_e64       dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pkrtz_f16_f32_e64        dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_rpi_i32_f32_e64          dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_u32_f32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_u32_f64_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f32                dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f64                dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f32                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f64                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_scale_f32                dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_div_scale_f64                dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_exp_f32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_exp_legacy_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_i32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_u32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_ffbl_b32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_floor_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_floor_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f64                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_exp_i32_f32_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_exp_i32_f64_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f32_e64           dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f64_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f64                    dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lerp_u8                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_log_clamp_f32_e64            dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_log_f32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_log_legacy_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lshl_b32_e64                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_lshl_b64                     dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_lshlrev_b32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_lshr_b32_e64                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_lshr_b64                     dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_lshrrev_b32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mac_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mac_legacy_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_f32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i32_i24                  dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i64_i32                  dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_mad_legacy_f32               dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u32_u24                  dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u64_u32                  dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_max3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_max3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_max_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_i32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_max_legacy_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mbcnt_hi_u32_b32_e64         dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mbcnt_lo_u32_b32_e64         dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_med3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_med3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_min3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_min3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_min_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_i32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_min_legacy_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mov_b32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_mov_fed_b32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_movreld_b32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_movrels_b32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_movrelsd_b32_e64             dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_mqsad_pk_u16_u8              dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_mqsad_u32_u8                 dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_msad_u8                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_mul_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_i32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_i32_i24_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_u32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_u32_u24_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_i32_i24_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_legacy_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_i32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_u32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_u32_u24_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mullit_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_nop_e64                                                     :ref:`omod<amdgpu_synid_omod>`
+    v_not_b32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_or_b32_e64                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_qsad_pk_u16_u8               dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_clamp_f32_e64            dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_clamp_f64_e64            dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_f32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_f64_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_iflag_f32_e64            dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_legacy_f32_e64           dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_clamp_f32_e64            dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_clamp_f64_e64            dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f64_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_legacy_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_hi_u8                    dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_sad_u16                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_sad_u32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_sad_u8                       dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_sin_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f32_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f64_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_i32_e64                  dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
+    v_subb_u32_e64                 dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_subbrev_u32_e64              dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_i32_e64               dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
+    v_trig_preop_f64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_xor_b32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+
+VOPC
+===========================
+
+.. parsed-literal::
+
+    v_cmp_class_f32                dst, src0, src1
+    v_cmp_class_f64                dst, src0, src1
+    v_cmp_eq_f32                   dst, src0, src1
+    v_cmp_eq_f64                   dst, src0, src1
+    v_cmp_eq_i32                   dst, src0, src1
+    v_cmp_eq_i64                   dst, src0, src1
+    v_cmp_eq_u32                   dst, src0, src1
+    v_cmp_eq_u64                   dst, src0, src1
+    v_cmp_f_f32                    dst, src0, src1
+    v_cmp_f_f64                    dst, src0, src1
+    v_cmp_f_i32                    dst, src0, src1
+    v_cmp_f_i64                    dst, src0, src1
+    v_cmp_f_u32                    dst, src0, src1
+    v_cmp_f_u64                    dst, src0, src1
+    v_cmp_ge_f32                   dst, src0, src1
+    v_cmp_ge_f64                   dst, src0, src1
+    v_cmp_ge_i32                   dst, src0, src1
+    v_cmp_ge_i64                   dst, src0, src1
+    v_cmp_ge_u32                   dst, src0, src1
+    v_cmp_ge_u64                   dst, src0, src1
+    v_cmp_gt_f32                   dst, src0, src1
+    v_cmp_gt_f64                   dst, src0, src1
+    v_cmp_gt_i32                   dst, src0, src1
+    v_cmp_gt_i64                   dst, src0, src1
+    v_cmp_gt_u32                   dst, src0, src1
+    v_cmp_gt_u64                   dst, src0, src1
+    v_cmp_le_f32                   dst, src0, src1
+    v_cmp_le_f64                   dst, src0, src1
+    v_cmp_le_i32                   dst, src0, src1
+    v_cmp_le_i64                   dst, src0, src1
+    v_cmp_le_u32                   dst, src0, src1
+    v_cmp_le_u64                   dst, src0, src1
+    v_cmp_lg_f32                   dst, src0, src1
+    v_cmp_lg_f64                   dst, src0, src1
+    v_cmp_lt_f32                   dst, src0, src1
+    v_cmp_lt_f64                   dst, src0, src1
+    v_cmp_lt_i32                   dst, src0, src1
+    v_cmp_lt_i64                   dst, src0, src1
+    v_cmp_lt_u32                   dst, src0, src1
+    v_cmp_lt_u64                   dst, src0, src1
+    v_cmp_ne_i32                   dst, src0, src1
+    v_cmp_ne_i64                   dst, src0, src1
+    v_cmp_ne_u32                   dst, src0, src1
+    v_cmp_ne_u64                   dst, src0, src1
+    v_cmp_neq_f32                  dst, src0, src1
+    v_cmp_neq_f64                  dst, src0, src1
+    v_cmp_nge_f32                  dst, src0, src1
+    v_cmp_nge_f64                  dst, src0, src1
+    v_cmp_ngt_f32                  dst, src0, src1
+    v_cmp_ngt_f64                  dst, src0, src1
+    v_cmp_nle_f32                  dst, src0, src1
+    v_cmp_nle_f64                  dst, src0, src1
+    v_cmp_nlg_f32                  dst, src0, src1
+    v_cmp_nlg_f64                  dst, src0, src1
+    v_cmp_nlt_f32                  dst, src0, src1
+    v_cmp_nlt_f64                  dst, src0, src1
+    v_cmp_o_f32                    dst, src0, src1
+    v_cmp_o_f64                    dst, src0, src1
+    v_cmp_t_i32                    dst, src0, src1
+    v_cmp_t_i64                    dst, src0, src1
+    v_cmp_t_u32                    dst, src0, src1
+    v_cmp_t_u64                    dst, src0, src1
+    v_cmp_tru_f32                  dst, src0, src1
+    v_cmp_tru_f64                  dst, src0, src1
+    v_cmp_u_f32                    dst, src0, src1
+    v_cmp_u_f64                    dst, src0, src1
+    v_cmps_eq_f32                  dst, src0, src1
+    v_cmps_eq_f64                  dst, src0, src1
+    v_cmps_f_f32                   dst, src0, src1
+    v_cmps_f_f64                   dst, src0, src1
+    v_cmps_ge_f32                  dst, src0, src1
+    v_cmps_ge_f64                  dst, src0, src1
+    v_cmps_gt_f32                  dst, src0, src1
+    v_cmps_gt_f64                  dst, src0, src1
+    v_cmps_le_f32                  dst, src0, src1
+    v_cmps_le_f64                  dst, src0, src1
+    v_cmps_lg_f32                  dst, src0, src1
+    v_cmps_lg_f64                  dst, src0, src1
+    v_cmps_lt_f32                  dst, src0, src1
+    v_cmps_lt_f64                  dst, src0, src1
+    v_cmps_neq_f32                 dst, src0, src1
+    v_cmps_neq_f64                 dst, src0, src1
+    v_cmps_nge_f32                 dst, src0, src1
+    v_cmps_nge_f64                 dst, src0, src1
+    v_cmps_ngt_f32                 dst, src0, src1
+    v_cmps_ngt_f64                 dst, src0, src1
+    v_cmps_nle_f32                 dst, src0, src1
+    v_cmps_nle_f64                 dst, src0, src1
+    v_cmps_nlg_f32                 dst, src0, src1
+    v_cmps_nlg_f64                 dst, src0, src1
+    v_cmps_nlt_f32                 dst, src0, src1
+    v_cmps_nlt_f64                 dst, src0, src1
+    v_cmps_o_f32                   dst, src0, src1
+    v_cmps_o_f64                   dst, src0, src1
+    v_cmps_tru_f32                 dst, src0, src1
+    v_cmps_tru_f64                 dst, src0, src1
+    v_cmps_u_f32                   dst, src0, src1
+    v_cmps_u_f64                   dst, src0, src1
+    v_cmpsx_eq_f32                 dst, src0, src1
+    v_cmpsx_eq_f64                 dst, src0, src1
+    v_cmpsx_f_f32                  dst, src0, src1
+    v_cmpsx_f_f64                  dst, src0, src1
+    v_cmpsx_ge_f32                 dst, src0, src1
+    v_cmpsx_ge_f64                 dst, src0, src1
+    v_cmpsx_gt_f32                 dst, src0, src1
+    v_cmpsx_gt_f64                 dst, src0, src1
+    v_cmpsx_le_f32                 dst, src0, src1
+    v_cmpsx_le_f64                 dst, src0, src1
+    v_cmpsx_lg_f32                 dst, src0, src1
+    v_cmpsx_lg_f64                 dst, src0, src1
+    v_cmpsx_lt_f32                 dst, src0, src1
+    v_cmpsx_lt_f64                 dst, src0, src1
+    v_cmpsx_neq_f32                dst, src0, src1
+    v_cmpsx_neq_f64                dst, src0, src1
+    v_cmpsx_nge_f32                dst, src0, src1
+    v_cmpsx_nge_f64                dst, src0, src1
+    v_cmpsx_ngt_f32                dst, src0, src1
+    v_cmpsx_ngt_f64                dst, src0, src1
+    v_cmpsx_nle_f32                dst, src0, src1
+    v_cmpsx_nle_f64                dst, src0, src1
+    v_cmpsx_nlg_f32                dst, src0, src1
+    v_cmpsx_nlg_f64                dst, src0, src1
+    v_cmpsx_nlt_f32                dst, src0, src1
+    v_cmpsx_nlt_f64                dst, src0, src1
+    v_cmpsx_o_f32                  dst, src0, src1
+    v_cmpsx_o_f64                  dst, src0, src1
+    v_cmpsx_tru_f32                dst, src0, src1
+    v_cmpsx_tru_f64                dst, src0, src1
+    v_cmpsx_u_f32                  dst, src0, src1
+    v_cmpsx_u_f64                  dst, src0, src1
+    v_cmpx_class_f32               dst, src0, src1
+    v_cmpx_class_f64               dst, src0, src1
+    v_cmpx_eq_f32                  dst, src0, src1
+    v_cmpx_eq_f64                  dst, src0, src1
+    v_cmpx_eq_i32                  dst, src0, src1
+    v_cmpx_eq_i64                  dst, src0, src1
+    v_cmpx_eq_u32                  dst, src0, src1
+    v_cmpx_eq_u64                  dst, src0, src1
+    v_cmpx_f_f32                   dst, src0, src1
+    v_cmpx_f_f64                   dst, src0, src1
+    v_cmpx_f_i32                   dst, src0, src1
+    v_cmpx_f_i64                   dst, src0, src1
+    v_cmpx_f_u32                   dst, src0, src1
+    v_cmpx_f_u64                   dst, src0, src1
+    v_cmpx_ge_f32                  dst, src0, src1
+    v_cmpx_ge_f64                  dst, src0, src1
+    v_cmpx_ge_i32                  dst, src0, src1
+    v_cmpx_ge_i64                  dst, src0, src1
+    v_cmpx_ge_u32                  dst, src0, src1
+    v_cmpx_ge_u64                  dst, src0, src1
+    v_cmpx_gt_f32                  dst, src0, src1
+    v_cmpx_gt_f64                  dst, src0, src1
+    v_cmpx_gt_i32                  dst, src0, src1
+    v_cmpx_gt_i64                  dst, src0, src1
+    v_cmpx_gt_u32                  dst, src0, src1
+    v_cmpx_gt_u64                  dst, src0, src1
+    v_cmpx_le_f32                  dst, src0, src1
+    v_cmpx_le_f64                  dst, src0, src1
+    v_cmpx_le_i32                  dst, src0, src1
+    v_cmpx_le_i64                  dst, src0, src1
+    v_cmpx_le_u32                  dst, src0, src1
+    v_cmpx_le_u64                  dst, src0, src1
+    v_cmpx_lg_f32                  dst, src0, src1
+    v_cmpx_lg_f64                  dst, src0, src1
+    v_cmpx_lt_f32                  dst, src0, src1
+    v_cmpx_lt_f64                  dst, src0, src1
+    v_cmpx_lt_i32                  dst, src0, src1
+    v_cmpx_lt_i64                  dst, src0, src1
+    v_cmpx_lt_u32                  dst, src0, src1
+    v_cmpx_lt_u64                  dst, src0, src1
+    v_cmpx_ne_i32                  dst, src0, src1
+    v_cmpx_ne_i64                  dst, src0, src1
+    v_cmpx_ne_u32                  dst, src0, src1
+    v_cmpx_ne_u64                  dst, src0, src1
+    v_cmpx_neq_f32                 dst, src0, src1
+    v_cmpx_neq_f64                 dst, src0, src1
+    v_cmpx_nge_f32                 dst, src0, src1
+    v_cmpx_nge_f64                 dst, src0, src1
+    v_cmpx_ngt_f32                 dst, src0, src1
+    v_cmpx_ngt_f64                 dst, src0, src1
+    v_cmpx_nle_f32                 dst, src0, src1
+    v_cmpx_nle_f64                 dst, src0, src1
+    v_cmpx_nlg_f32                 dst, src0, src1
+    v_cmpx_nlg_f64                 dst, src0, src1
+    v_cmpx_nlt_f32                 dst, src0, src1
+    v_cmpx_nlt_f64                 dst, src0, src1
+    v_cmpx_o_f32                   dst, src0, src1
+    v_cmpx_o_f64                   dst, src0, src1
+    v_cmpx_t_i32                   dst, src0, src1
+    v_cmpx_t_i64                   dst, src0, src1
+    v_cmpx_t_u32                   dst, src0, src1
+    v_cmpx_t_u64                   dst, src0, src1
+    v_cmpx_tru_f32                 dst, src0, src1
+    v_cmpx_tru_f64                 dst, src0, src1
+    v_cmpx_u_f32                   dst, src0, src1
+    v_cmpx_u_f64                   dst, src0, src1

llvm/trunk/docs/AMDGPUAsmGFX8.rst

+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+===========================
+Syntax of GFX8 Instructions
+===========================
+
+.. contents::
+  :local:
+
+
+DS
+===========================
+
+.. parsed-literal::
+
+    ds_add_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_b32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_b64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_rtn_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_rtn_b64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_src2_b32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_src2_b64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_append                      dst                            :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_bpermute_b32                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
+    ds_cmpst_b32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_b64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_f32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_f64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_b32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_b64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_f32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_f64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_condxchg32_rtn_b64          dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_consume                     dst                            :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_barrier                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_init                    src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_br                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_p                                                 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_release_all                                       :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_v                                                 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_f64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_i32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_i64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_f64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_i32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_i64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_f32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_f64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_i32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_i64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_f64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_i32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_i64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_f64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_i32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_i64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_f32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_f64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_i32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_i64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_b32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_b64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_rtn_b32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_rtn_b64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_nop
+    ds_or_b32                      src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_b64                      src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_rtn_b32                  dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_rtn_b64                  dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_src2_b32                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_src2_b64                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_ordered_count               dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_permute_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
+    ds_read2_b32                   dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2_b64                   dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2st64_b32               dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2st64_b64               dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b128                   dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b32                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b64                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b96                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i16                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i8                     dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u16                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u8                     dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_rtn_u32                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_rtn_u64                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_src2_u32               src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_src2_u64               src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_u32                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_u64                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_swizzle_b32                 dst, src0                      :ref:`sw_offset16<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrap_rtn_b32                dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2_b32                  src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2_b64                  src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2st64_b32              src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2st64_b64              src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b128                  src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b16                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b32                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b64                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b8                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b96                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_src2_b32              src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_src2_b64              src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2_rtn_b32             dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2_rtn_b64             dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2st64_rtn_b32         dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2st64_rtn_b64         dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg_rtn_b32              dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg_rtn_b64              dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_b32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_b64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_rtn_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_rtn_b64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_src2_b32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_src2_b64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+
+EXP
+===========================
+
+.. parsed-literal::
+
+    exp                            dst, src0, src1, src2, src3    :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
+
+FLAT
+===========================
+
+.. parsed-literal::
+
+    flat_atomic_add                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_add_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_and                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_and_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_cmpswap            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_cmpswap_x2         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_dec                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_dec_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_inc                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_inc_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_or                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_or_x2              dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smax               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smax_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smin               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smin_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_sub                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_sub_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_swap               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_swap_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umax               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umax_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umin               dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umin_x2            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_xor                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_xor_x2             dst, src0, src1                :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dword                dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx2              dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx3              dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx4              dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sbyte                dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sshort               dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ubyte                dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ushort               dst, src0                      :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_byte                src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dword               src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx2             src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx3             src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx4             src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_short               src0, src1                     :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
+MIMG
+===========================
+
+.. parsed-literal::
+
+    image_atomic_add               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_and               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_cmpswap           dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_dec               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_inc               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_or                dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_smax              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_smin              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_sub               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_swap              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_umax              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_umin              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_xor               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4                  dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_cl             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_cl_o           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_o              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_cl           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_cl_o         dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_o            dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_cl             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_cl_o           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_l              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_l_o            dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_lz             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_lz_o           dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_o              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_cl               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_cl_o             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_l                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_l_o              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_lz               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_lz_o             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_o                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_get_lod                  dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_get_resinfo              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load                     dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_load_mip                 dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample                   dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_cl              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_cl            dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cl              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_l               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_lz              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cl                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_l                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_lz                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_store                    src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_store_mip                src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+
+MUBUF
+===========================
+
+.. parsed-literal::
+
+    buffer_atomic_add              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_add_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap_x2       dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or               dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or_x2            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dword              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_dwordx2            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dwordx3            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dwordx4            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_x       dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_xy      dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_xyz     dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_xyzw    dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_x           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_format_xy          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_xyz         dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_xyzw        dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_sbyte              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_sshort             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_ubyte              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_ushort             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_store_byte              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dword             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx3           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx4           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_x      src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_xy     src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_xyz    src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_xyzw   src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_x          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xy         src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyz        src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyzw       src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_short             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_wbinvl1
+    buffer_wbinvl1_vol
+
+SMEM
+===========================
+
+.. parsed-literal::
+
+    s_buffer_load_dword            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx16         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx2          dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx4          dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx8          dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_store_dword           src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_store_dwordx2         src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_store_dwordx4         src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
+    s_dcache_inv
+    s_dcache_inv_vol
+    s_dcache_wb
+    s_dcache_wb_vol
+    s_load_dword                   dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx16                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx2                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx4                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx8                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_memrealtime                  dst
+    s_memtime                      dst
+    s_store_dword                  src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
+    s_store_dwordx2                src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
+    s_store_dwordx4                src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
+
+SOP1
+===========================
+
+.. parsed-literal::
+
+    s_abs_i32                      dst, src0
+    s_and_saveexec_b64             dst, src0
+    s_andn2_saveexec_b64           dst, src0
+    s_bcnt0_i32_b32                dst, src0
+    s_bcnt0_i32_b64                dst, src0
+    s_bcnt1_i32_b32                dst, src0
+    s_bcnt1_i32_b64                dst, src0
+    s_bitset0_b32                  dst, src0
+    s_bitset0_b64                  dst, src0
+    s_bitset1_b32                  dst, src0
+    s_bitset1_b64                  dst, src0
+    s_brev_b32                     dst, src0
+    s_brev_b64                     dst, src0
+    s_cbranch_join                 src0
+    s_cmov_b32                     dst, src0
+    s_cmov_b64                     dst, src0
+    s_ff0_i32_b32                  dst, src0
+    s_ff0_i32_b64                  dst, src0
+    s_ff1_i32_b32                  dst, src0
+    s_ff1_i32_b64                  dst, src0
+    s_flbit_i32                    dst, src0
+    s_flbit_i32_b32                dst, src0
+    s_flbit_i32_b64                dst, src0
+    s_flbit_i32_i64                dst, src0
+    s_getpc_b64                    dst
+    s_mov_b32                      dst, src0
+    s_mov_b64                      dst, src0
+    s_mov_fed_b32                  dst, src0
+    s_movreld_b32                  dst, src0
+    s_movreld_b64                  dst, src0
+    s_movrels_b32                  dst, src0
+    s_movrels_b64                  dst, src0
+    s_nand_saveexec_b64            dst, src0
+    s_nor_saveexec_b64             dst, src0
+    s_not_b32                      dst, src0
+    s_not_b64                      dst, src0
+    s_or_saveexec_b64              dst, src0
+    s_orn2_saveexec_b64            dst, src0
+    s_quadmask_b32                 dst, src0
+    s_quadmask_b64                 dst, src0
+    s_rfe_b64                      src0
+    s_set_gpr_idx_idx              src0
+    s_setpc_b64                    src0
+    s_sext_i32_i16                 dst, src0
+    s_sext_i32_i8                  dst, src0
+    s_swappc_b64                   dst, src0
+    s_wqm_b32                      dst, src0
+    s_wqm_b64                      dst, src0
+    s_xnor_saveexec_b64            dst, src0
+    s_xor_saveexec_b64             dst, src0
+
+SOP2
+===========================
+
+.. parsed-literal::
+
+    s_absdiff_i32                  dst, src0, src1
+    s_add_i32                      dst, src0, src1
+    s_add_u32                      dst, src0, src1
+    s_addc_u32                     dst, src0, src1
+    s_and_b32                      dst, src0, src1
+    s_and_b64                      dst, src0, src1
+    s_andn2_b32                    dst, src0, src1
+    s_andn2_b64                    dst, src0, src1
+    s_ashr_i32                     dst, src0, src1
+    s_ashr_i64                     dst, src0, src1
+    s_bfe_i32                      dst, src0, src1
+    s_bfe_i64                      dst, src0, src1
+    s_bfe_u32                      dst, src0, src1
+    s_bfe_u64                      dst, src0, src1
+    s_bfm_b32                      dst, src0, src1
+    s_bfm_b64                      dst, src0, src1
+    s_cbranch_g_fork               src0, src1
+    s_cselect_b32                  dst, src0, src1
+    s_cselect_b64                  dst, src0, src1
+    s_lshl_b32                     dst, src0, src1
+    s_lshl_b64                     dst, src0, src1
+    s_lshr_b32                     dst, src0, src1
+    s_lshr_b64                     dst, src0, src1
+    s_max_i32                      dst, src0, src1
+    s_max_u32                      dst, src0, src1
+    s_min_i32                      dst, src0, src1
+    s_min_u32                      dst, src0, src1
+    s_mul_i32                      dst, src0, src1
+    s_nand_b32                     dst, src0, src1
+    s_nand_b64                     dst, src0, src1
+    s_nor_b32                      dst, src0, src1
+    s_nor_b64                      dst, src0, src1
+    s_or_b32                       dst, src0, src1
+    s_or_b64                       dst, src0, src1
+    s_orn2_b32                     dst, src0, src1
+    s_orn2_b64                     dst, src0, src1
+    s_rfe_restore_b64              src0, src1
+    s_sub_i32                      dst, src0, src1
+    s_sub_u32                      dst, src0, src1
+    s_subb_u32                     dst, src0, src1
+    s_xnor_b32                     dst, src0, src1
+    s_xnor_b64                     dst, src0, src1
+    s_xor_b32                      dst, src0, src1
+    s_xor_b64                      dst, src0, src1
+
+SOPC
+===========================
+
+.. parsed-literal::
+
+    s_bitcmp0_b32                  src0, src1
+    s_bitcmp0_b64                  src0, src1
+    s_bitcmp1_b32                  src0, src1
+    s_bitcmp1_b64                  src0, src1
+    s_cmp_eq_i32                   src0, src1
+    s_cmp_eq_u32                   src0, src1
+    s_cmp_eq_u64                   src0, src1
+    s_cmp_ge_i32                   src0, src1
+    s_cmp_ge_u32                   src0, src1
+    s_cmp_gt_i32                   src0, src1
+    s_cmp_gt_u32                   src0, src1
+    s_cmp_le_i32                   src0, src1
+    s_cmp_le_u32                   src0, src1
+    s_cmp_lg_i32                   src0, src1
+    s_cmp_lg_u32                   src0, src1
+    s_cmp_lg_u64                   src0, src1
+    s_cmp_lt_i32                   src0, src1
+    s_cmp_lt_u32                   src0, src1
+    s_set_gpr_idx_on               src0, src1
+    s_setvskip                     src0, src1
+
+SOPK
+===========================
+
+.. parsed-literal::
+
+    s_addk_i32                     dst, src0
+    s_cbranch_i_fork               src0, src1
+    s_cmovk_i32                    dst, src0
+    s_cmpk_eq_i32                  src0, src1
+    s_cmpk_eq_u32                  src0, src1
+    s_cmpk_ge_i32                  src0, src1
+    s_cmpk_ge_u32                  src0, src1
+    s_cmpk_gt_i32                  src0, src1
+    s_cmpk_gt_u32                  src0, src1
+    s_cmpk_le_i32                  src0, src1
+    s_cmpk_le_u32                  src0, src1
+    s_cmpk_lg_i32                  src0, src1
+    s_cmpk_lg_u32                  src0, src1
+    s_cmpk_lt_i32                  src0, src1
+    s_cmpk_lt_u32                  src0, src1
+    s_getreg_b32                   dst, src0
+    s_movk_i32                     dst, src0
+    s_mulk_i32                     dst, src0
+    s_setreg_b32                   dst, src0
+    s_setreg_imm32_b32             dst, src0
+
+SOPP
+===========================
+
+.. parsed-literal::
+
+    s_barrier
+    s_branch                       src0
+    s_cbranch_cdbgsys              src0
+    s_cbranch_cdbgsys_and_user     src0
+    s_cbranch_cdbgsys_or_user      src0
+    s_cbranch_cdbguser             src0
+    s_cbranch_execnz               src0
+    s_cbranch_execz                src0
+    s_cbranch_scc0                 src0
+    s_cbranch_scc1                 src0
+    s_cbranch_vccnz                src0
+    s_cbranch_vccz                 src0
+    s_decperflevel                 src0
+    s_endpgm
+    s_endpgm_saved
+    s_icache_inv
+    s_incperflevel                 src0
+    s_nop                          src0
+    s_sendmsg                      src0
+    s_sendmsghalt                  src0
+    s_set_gpr_idx_mode             src0
+    s_set_gpr_idx_off
+    s_sethalt                      src0
+    s_setkill                      src0
+    s_setprio                      src0
+    s_sleep                        src0
+    s_trap                         src0
+    s_ttracedata
+    s_waitcnt                      src0
+    s_wakeup
+
+VINTRP
+===========================
+
+.. parsed-literal::
+
+    v_interp_mov_f32               dst, src0, src1
+    v_interp_p1_f32                dst, src0, src1
+    v_interp_p2_f32                dst, src0, src1
+
+VOP1
+===========================
+
+.. parsed-literal::
+
+    v_bfrev_b32                    dst, src0
+    v_bfrev_b32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_bfrev_b32_sdwa               dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ceil_f16                     dst, src0
+    v_ceil_f16_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ceil_f16_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ceil_f32                     dst, src0
+    v_ceil_f32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ceil_f32_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ceil_f64                     dst, src0
+    v_clrexcp
+    v_cos_f16                      dst, src0
+    v_cos_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cos_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cos_f32                      dst, src0
+    v_cos_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cos_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_f32                  dst, src0
+    v_cvt_f16_f32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f16_f32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_i16                  dst, src0
+    v_cvt_f16_i16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f16_i16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_u16                  dst, src0
+    v_cvt_f16_u16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f16_u16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_f16                  dst, src0
+    v_cvt_f32_f16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_f16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_f64                  dst, src0
+    v_cvt_f32_i32                  dst, src0
+    v_cvt_f32_i32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_i32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_u32                  dst, src0
+    v_cvt_f32_u32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_u32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte0               dst, src0
+    v_cvt_f32_ubyte0_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte0_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte1               dst, src0
+    v_cvt_f32_ubyte1_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte1_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte2               dst, src0
+    v_cvt_f32_ubyte2_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte2_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte3               dst, src0
+    v_cvt_f32_ubyte3_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte3_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f64_f32                  dst, src0
+    v_cvt_f64_i32                  dst, src0
+    v_cvt_f64_u32                  dst, src0
+    v_cvt_flr_i32_f32              dst, src0
+    v_cvt_flr_i32_f32_dpp          dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_flr_i32_f32_sdwa         dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_i16_f16                  dst, src0
+    v_cvt_i16_f16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_i16_f16_sdwa             dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_i32_f32                  dst, src0
+    v_cvt_i32_f32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_i32_f32_sdwa             dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_i32_f64                  dst, src0
+    v_cvt_off_f32_i4               dst, src0
+    v_cvt_off_f32_i4_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_off_f32_i4_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_rpi_i32_f32              dst, src0
+    v_cvt_rpi_i32_f32_dpp          dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_rpi_i32_f32_sdwa         dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_u16_f16                  dst, src0
+    v_cvt_u16_f16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_u16_f16_sdwa             dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_u32_f32                  dst, src0
+    v_cvt_u32_f32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_u32_f32_sdwa             dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_u32_f64                  dst, src0
+    v_exp_f16                      dst, src0
+    v_exp_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_exp_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_exp_f32                      dst, src0
+    v_exp_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_exp_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_exp_legacy_f32               dst, src0
+    v_exp_legacy_f32_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_exp_legacy_f32_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ffbh_i32                     dst, src0
+    v_ffbh_i32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ffbh_i32_sdwa                dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ffbh_u32                     dst, src0
+    v_ffbh_u32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ffbh_u32_sdwa                dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ffbl_b32                     dst, src0
+    v_ffbl_b32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ffbl_b32_sdwa                dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_floor_f16                    dst, src0
+    v_floor_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_floor_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_floor_f32                    dst, src0
+    v_floor_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_floor_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_floor_f64                    dst, src0
+    v_fract_f16                    dst, src0
+    v_fract_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_fract_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_fract_f32                    dst, src0
+    v_fract_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_fract_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_fract_f64                    dst, src0
+    v_frexp_exp_i16_f16            dst, src0
+    v_frexp_exp_i16_f16_dpp        dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_exp_i16_f16_sdwa       dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_exp_i32_f32            dst, src0
+    v_frexp_exp_i32_f32_dpp        dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_exp_i32_f32_sdwa       dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_exp_i32_f64            dst, src0
+    v_frexp_mant_f16               dst, src0
+    v_frexp_mant_f16_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_mant_f16_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_mant_f32               dst, src0
+    v_frexp_mant_f32_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_mant_f32_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_mant_f64               dst, src0
+    v_log_f16                      dst, src0
+    v_log_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_log_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_log_f32                      dst, src0
+    v_log_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_log_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_log_legacy_f32               dst, src0
+    v_log_legacy_f32_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_log_legacy_f32_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_mov_b32                      dst, src0
+    v_mov_b32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mov_b32_sdwa                 dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_mov_fed_b32                  dst, src0
+    v_mov_fed_b32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mov_fed_b32_sdwa             dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_movreld_b32                  dst, src0
+    v_movrels_b32                  dst, src0
+    v_movrelsd_b32                 dst, src0
+    v_nop
+    v_not_b32                      dst, src0
+    v_not_b32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_not_b32_sdwa                 dst, src0                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rcp_f16                      dst, src0
+    v_rcp_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rcp_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rcp_f32                      dst, src0
+    v_rcp_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rcp_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rcp_f64                      dst, src0
+    v_rcp_iflag_f32                dst, src0
+    v_rcp_iflag_f32_dpp            dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rcp_iflag_f32_sdwa           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_readfirstlane_b32            dst, src0
+    v_rndne_f16                    dst, src0
+    v_rndne_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rndne_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rndne_f32                    dst, src0
+    v_rndne_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rndne_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rndne_f64                    dst, src0
+    v_rsq_f16                      dst, src0
+    v_rsq_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rsq_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rsq_f32                      dst, src0
+    v_rsq_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rsq_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rsq_f64                      dst, src0
+    v_sin_f16                      dst, src0
+    v_sin_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sin_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sin_f32                      dst, src0
+    v_sin_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sin_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sqrt_f16                     dst, src0
+    v_sqrt_f16_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sqrt_f16_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sqrt_f32                     dst, src0
+    v_sqrt_f32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sqrt_f32_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sqrt_f64                     dst, src0
+    v_trunc_f16                    dst, src0
+    v_trunc_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_trunc_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_trunc_f32                    dst, src0
+    v_trunc_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_trunc_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_trunc_f64                    dst, src0
+
+VOP2
+===========================
+
+.. parsed-literal::
+
+    v_add_f16                      dst, src0, src1
+    v_add_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_f32                      dst, src0, src1
+    v_add_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_u16                      dst, src0, src1
+    v_add_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_u16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_u32                      dst0, dst1, src0, src1
+    v_add_u32_dpp                  dst0, dst1, src0, src1         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_u32_sdwa                 dst0, dst1, src0, src1         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_addc_u32                     dst0, dst1, src0, src1, src2
+    v_addc_u32_dpp                 dst0, dst1, src0, src1, src2   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_addc_u32_sdwa                dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_and_b32                      dst, src0, src1
+    v_and_b32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_and_b32_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_ashrrev_i16                  dst, src0, src1
+    v_ashrrev_i16_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ashrrev_i16_sdwa             dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_ashrrev_i32                  dst, src0, src1
+    v_ashrrev_i32_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ashrrev_i32_sdwa             dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cndmask_b32                  dst, src0, src1, src2
+    v_ldexp_f16                    dst, src0, src1
+    v_ldexp_f16_dpp                dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ldexp_f16_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshlrev_b16                  dst, src0, src1
+    v_lshlrev_b16_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshlrev_b16_sdwa             dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshlrev_b32                  dst, src0, src1
+    v_lshlrev_b32_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshlrev_b32_sdwa             dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshrrev_b16                  dst, src0, src1
+    v_lshrrev_b16_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshrrev_b16_sdwa             dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshrrev_b32                  dst, src0, src1
+    v_lshrrev_b32_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshrrev_b32_sdwa             dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mac_f16                      dst, src0, src1
+    v_mac_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mac_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mac_f32                      dst, src0, src1
+    v_mac_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mac_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_madak_f16                    dst, src0, src1, src2
+    v_madak_f32                    dst, src0, src1, src2
+    v_madmk_f16                    dst, src0, src1, src2
+    v_madmk_f32                    dst, src0, src1, src2
+    v_max_f16                      dst, src0, src1
+    v_max_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_f32                      dst, src0, src1
+    v_max_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_i16                      dst, src0, src1
+    v_max_i16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_i16_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_i32                      dst, src0, src1
+    v_max_i32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_i32_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_u16                      dst, src0, src1
+    v_max_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_u16_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_u32                      dst, src0, src1
+    v_max_u32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_u32_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_f16                      dst, src0, src1
+    v_min_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_f32                      dst, src0, src1
+    v_min_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_i16                      dst, src0, src1
+    v_min_i16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_i16_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_i32                      dst, src0, src1
+    v_min_i32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_i32_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_u16                      dst, src0, src1
+    v_min_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_u16_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_u32                      dst, src0, src1
+    v_min_u32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_u32_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_f16                      dst, src0, src1
+    v_mul_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_f32                      dst, src0, src1
+    v_mul_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_hi_i32_i24               dst, src0, src1
+    v_mul_hi_i32_i24_dpp           dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_hi_i32_i24_sdwa          dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_hi_u32_u24               dst, src0, src1
+    v_mul_hi_u32_u24_dpp           dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_hi_u32_u24_sdwa          dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_i32_i24                  dst, src0, src1
+    v_mul_i32_i24_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_i32_i24_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_legacy_f32               dst, src0, src1
+    v_mul_legacy_f32_dpp           dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_legacy_f32_sdwa          dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_lo_u16                   dst, src0, src1
+    v_mul_lo_u16_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_lo_u16_sdwa              dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_u32_u24                  dst, src0, src1
+    v_mul_u32_u24_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_u32_u24_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_or_b32                       dst, src0, src1
+    v_or_b32_dpp                   dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_or_b32_sdwa                  dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_f16                      dst, src0, src1
+    v_sub_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_f32                      dst, src0, src1
+    v_sub_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_u16                      dst, src0, src1
+    v_sub_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_u16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_u32                      dst0, dst1, src0, src1
+    v_sub_u32_dpp                  dst0, dst1, src0, src1         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_u32_sdwa                 dst0, dst1, src0, src1         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subb_u32                     dst0, dst1, src0, src1, src2
+    v_subb_u32_dpp                 dst0, dst1, src0, src1, src2   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subb_u32_sdwa                dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subbrev_u32                  dst0, dst1, src0, src1, src2
+    v_subbrev_u32_dpp              dst0, dst1, src0, src1, src2   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subbrev_u32_sdwa             dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_f16                   dst, src0, src1
+    v_subrev_f16_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_f32                   dst, src0, src1
+    v_subrev_f32_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_u16                   dst, src0, src1
+    v_subrev_u16_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_u16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_u32                   dst0, dst1, src0, src1
+    v_subrev_u32_dpp               dst0, dst1, src0, src1         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_u32_sdwa              dst0, dst1, src0, src1         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_xor_b32                      dst, src0, src1
+    v_xor_b32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_xor_b32_sdwa                 dst, src0, src1                :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+
+VOP3
+===========================
+
+.. parsed-literal::
+
+    v_add_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_add_u32_e64                  dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
+    v_addc_u32_e64                 dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_alignbit_b32                 dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_alignbyte_b32                dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_and_b32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_ashrrev_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_ashrrev_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_ashrrev_i64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_bcnt_u32_b32                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_bfe_i32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_bfe_u32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_bfi_b32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_bfm_b32                      dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_bfrev_b32_e64                dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_ceil_f16_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ceil_f32_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ceil_f64_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_clrexcp_e64                                                 :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_class_f16_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_class_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_class_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_f32_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_f64_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_i16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_i32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_i64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_u16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_u32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_u64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lg_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lg_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lg_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_neq_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_neq_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_neq_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nge_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nge_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nge_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ngt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ngt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ngt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nle_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nle_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nle_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlg_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlg_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlg_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_o_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_o_f32_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_o_f64_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_i16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_i32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_i64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_u16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_u32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_u64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_tru_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_tru_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_tru_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_u_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_u_f32_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_u_f64_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_class_f16_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_class_f32_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_class_f64_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lg_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lg_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lg_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_neq_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_neq_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_neq_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nge_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nge_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nge_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ngt_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ngt_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ngt_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nle_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nle_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nle_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlg_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlg_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlg_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlt_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlt_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlt_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_o_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_o_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_o_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_tru_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_tru_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_tru_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_u_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_u_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_u_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cndmask_b32_e64              dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_cos_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cos_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubeid_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubema_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubesc_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubetc_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_f32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_i16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_u16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_f16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_f64_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_i32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_u32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte0_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte1_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte2_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte3_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_f32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_i32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_u32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_flr_i32_f32_e64          dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_i16_f16_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_i32_f32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_i32_f64_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_off_f32_i4_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_i16_i32               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_u16_u32               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_u8_f32                dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pkaccum_u8_f32           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pknorm_i16_f32           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pknorm_u16_f32           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pkrtz_f16_f32            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_rpi_i32_f32_e64          dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_u16_f16_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_u32_f32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_u32_f64_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f16                dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f32                dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f64                dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f32                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f64                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_scale_f32                dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_div_scale_f64                dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_exp_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_legacy_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_i32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_u32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_ffbl_b32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_floor_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_floor_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_floor_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f16                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f64                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_exp_i16_f16_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_exp_i32_f32_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_exp_i32_f64_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f16_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f64_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_mov_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p1_f32_e64            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p1ll_f16              dst, src0, src1                :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p1lv_f16              dst, src0, src1, src2          :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p2_f16                dst, src0, src1, src2          :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p2_f32_e64            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f32                    dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f64                    dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lerp_u8                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_log_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_log_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_log_legacy_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lshlrev_b16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_lshlrev_b32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_lshlrev_b64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_lshrrev_b16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_lshrrev_b32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_lshrrev_b64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mac_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mac_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_f16                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_f32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i16                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i32_i24                  dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i64_i32                  dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_legacy_f32               dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u16                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u32_u24                  dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u64_u32                  dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_max3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_max_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_i16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_max_i32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_max_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_max_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mbcnt_hi_u32_b32             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mbcnt_lo_u32_b32             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_med3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_med3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_min3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_min3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_min_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_i16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_min_i32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_min_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_min_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mov_b32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_mov_fed_b32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_movreld_b32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_movrels_b32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_movrelsd_b32_e64             dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_mqsad_pk_u16_u8              dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mqsad_u32_u8                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_msad_u8                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_i32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_i32_i24_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_u32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_u32_u24_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_i32_i24_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_legacy_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_u32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_u32_u24_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_nop_e64                                                     :ref:`omod<amdgpu_synid_omod>`
+    v_not_b32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_or_b32_e64                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_perm_b32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_qsad_pk_u16_u8               dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_f64_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_iflag_f32_e64            dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_readlane_b32                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f64_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_hi_u8                    dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_u16                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_u32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_u8                       dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sin_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sin_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f16_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f32_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f64_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_sub_u32_e64                  dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
+    v_subb_u32_e64                 dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_subbrev_u32_e64              dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_u32_e64               dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
+    v_trig_preop_f64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_writelane_b32                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_xor_b32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+
+VOPC
+===========================
+
+.. parsed-literal::
+
+    v_cmp_class_f16                dst, src0, src1
+    v_cmp_class_f16_sdwa           dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_class_f32                dst, src0, src1
+    v_cmp_class_f32_sdwa           dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_class_f64                dst, src0, src1
+    v_cmp_eq_f16                   dst, src0, src1
+    v_cmp_eq_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_f32                   dst, src0, src1
+    v_cmp_eq_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_f64                   dst, src0, src1
+    v_cmp_eq_i16                   dst, src0, src1
+    v_cmp_eq_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_i32                   dst, src0, src1
+    v_cmp_eq_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_i64                   dst, src0, src1
+    v_cmp_eq_u16                   dst, src0, src1
+    v_cmp_eq_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_u32                   dst, src0, src1
+    v_cmp_eq_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_u64                   dst, src0, src1
+    v_cmp_f_f16                    dst, src0, src1
+    v_cmp_f_f16_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_f32                    dst, src0, src1
+    v_cmp_f_f32_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_f64                    dst, src0, src1
+    v_cmp_f_i16                    dst, src0, src1
+    v_cmp_f_i16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_i32                    dst, src0, src1
+    v_cmp_f_i32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_i64                    dst, src0, src1
+    v_cmp_f_u16                    dst, src0, src1
+    v_cmp_f_u16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_u32                    dst, src0, src1
+    v_cmp_f_u32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_u64                    dst, src0, src1
+    v_cmp_ge_f16                   dst, src0, src1
+    v_cmp_ge_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_f32                   dst, src0, src1
+    v_cmp_ge_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_f64                   dst, src0, src1
+    v_cmp_ge_i16                   dst, src0, src1
+    v_cmp_ge_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_i32                   dst, src0, src1
+    v_cmp_ge_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_i64                   dst, src0, src1
+    v_cmp_ge_u16                   dst, src0, src1
+    v_cmp_ge_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_u32                   dst, src0, src1
+    v_cmp_ge_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_u64                   dst, src0, src1
+    v_cmp_gt_f16                   dst, src0, src1
+    v_cmp_gt_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_f32                   dst, src0, src1
+    v_cmp_gt_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_f64                   dst, src0, src1
+    v_cmp_gt_i16                   dst, src0, src1
+    v_cmp_gt_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_i32                   dst, src0, src1
+    v_cmp_gt_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_i64                   dst, src0, src1
+    v_cmp_gt_u16                   dst, src0, src1
+    v_cmp_gt_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_u32                   dst, src0, src1
+    v_cmp_gt_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_u64                   dst, src0, src1
+    v_cmp_le_f16                   dst, src0, src1
+    v_cmp_le_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_f32                   dst, src0, src1
+    v_cmp_le_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_f64                   dst, src0, src1
+    v_cmp_le_i16                   dst, src0, src1
+    v_cmp_le_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_i32                   dst, src0, src1
+    v_cmp_le_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_i64                   dst, src0, src1
+    v_cmp_le_u16                   dst, src0, src1
+    v_cmp_le_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_u32                   dst, src0, src1
+    v_cmp_le_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_u64                   dst, src0, src1
+    v_cmp_lg_f16                   dst, src0, src1
+    v_cmp_lg_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lg_f32                   dst, src0, src1
+    v_cmp_lg_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lg_f64                   dst, src0, src1
+    v_cmp_lt_f16                   dst, src0, src1
+    v_cmp_lt_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_f32                   dst, src0, src1
+    v_cmp_lt_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_f64                   dst, src0, src1
+    v_cmp_lt_i16                   dst, src0, src1
+    v_cmp_lt_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_i32                   dst, src0, src1
+    v_cmp_lt_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_i64                   dst, src0, src1
+    v_cmp_lt_u16                   dst, src0, src1
+    v_cmp_lt_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_u32                   dst, src0, src1
+    v_cmp_lt_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_u64                   dst, src0, src1
+    v_cmp_ne_i16                   dst, src0, src1
+    v_cmp_ne_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_i32                   dst, src0, src1
+    v_cmp_ne_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_i64                   dst, src0, src1
+    v_cmp_ne_u16                   dst, src0, src1
+    v_cmp_ne_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_u32                   dst, src0, src1
+    v_cmp_ne_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_u64                   dst, src0, src1
+    v_cmp_neq_f16                  dst, src0, src1
+    v_cmp_neq_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_neq_f32                  dst, src0, src1
+    v_cmp_neq_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_neq_f64                  dst, src0, src1
+    v_cmp_nge_f16                  dst, src0, src1
+    v_cmp_nge_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nge_f32                  dst, src0, src1
+    v_cmp_nge_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nge_f64                  dst, src0, src1
+    v_cmp_ngt_f16                  dst, src0, src1
+    v_cmp_ngt_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ngt_f32                  dst, src0, src1
+    v_cmp_ngt_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ngt_f64                  dst, src0, src1
+    v_cmp_nle_f16                  dst, src0, src1
+    v_cmp_nle_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nle_f32                  dst, src0, src1
+    v_cmp_nle_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nle_f64                  dst, src0, src1
+    v_cmp_nlg_f16                  dst, src0, src1
+    v_cmp_nlg_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlg_f32                  dst, src0, src1
+    v_cmp_nlg_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlg_f64                  dst, src0, src1
+    v_cmp_nlt_f16                  dst, src0, src1
+    v_cmp_nlt_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlt_f32                  dst, src0, src1
+    v_cmp_nlt_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlt_f64                  dst, src0, src1
+    v_cmp_o_f16                    dst, src0, src1
+    v_cmp_o_f16_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_o_f32                    dst, src0, src1
+    v_cmp_o_f32_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_o_f64                    dst, src0, src1
+    v_cmp_t_i16                    dst, src0, src1
+    v_cmp_t_i16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_i32                    dst, src0, src1
+    v_cmp_t_i32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_i64                    dst, src0, src1
+    v_cmp_t_u16                    dst, src0, src1
+    v_cmp_t_u16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_u32                    dst, src0, src1
+    v_cmp_t_u32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_u64                    dst, src0, src1
+    v_cmp_tru_f16                  dst, src0, src1
+    v_cmp_tru_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_tru_f32                  dst, src0, src1
+    v_cmp_tru_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_tru_f64                  dst, src0, src1
+    v_cmp_u_f16                    dst, src0, src1
+    v_cmp_u_f16_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_u_f32                    dst, src0, src1
+    v_cmp_u_f32_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_u_f64                    dst, src0, src1
+    v_cmpx_class_f16               dst, src0, src1
+    v_cmpx_class_f16_sdwa          dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_class_f32               dst, src0, src1
+    v_cmpx_class_f32_sdwa          dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_class_f64               dst, src0, src1
+    v_cmpx_eq_f16                  dst, src0, src1
+    v_cmpx_eq_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_f32                  dst, src0, src1
+    v_cmpx_eq_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_f64                  dst, src0, src1
+    v_cmpx_eq_i16                  dst, src0, src1
+    v_cmpx_eq_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_i32                  dst, src0, src1
+    v_cmpx_eq_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_i64                  dst, src0, src1
+    v_cmpx_eq_u16                  dst, src0, src1
+    v_cmpx_eq_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_u32                  dst, src0, src1
+    v_cmpx_eq_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_u64                  dst, src0, src1
+    v_cmpx_f_f16                   dst, src0, src1
+    v_cmpx_f_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_f32                   dst, src0, src1
+    v_cmpx_f_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_f64                   dst, src0, src1
+    v_cmpx_f_i16                   dst, src0, src1
+    v_cmpx_f_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_i32                   dst, src0, src1
+    v_cmpx_f_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_i64                   dst, src0, src1
+    v_cmpx_f_u16                   dst, src0, src1
+    v_cmpx_f_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_u32                   dst, src0, src1
+    v_cmpx_f_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_u64                   dst, src0, src1
+    v_cmpx_ge_f16                  dst, src0, src1
+    v_cmpx_ge_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_f32                  dst, src0, src1
+    v_cmpx_ge_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_f64                  dst, src0, src1
+    v_cmpx_ge_i16                  dst, src0, src1
+    v_cmpx_ge_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_i32                  dst, src0, src1
+    v_cmpx_ge_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_i64                  dst, src0, src1
+    v_cmpx_ge_u16                  dst, src0, src1
+    v_cmpx_ge_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_u32                  dst, src0, src1
+    v_cmpx_ge_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_u64                  dst, src0, src1
+    v_cmpx_gt_f16                  dst, src0, src1
+    v_cmpx_gt_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_f32                  dst, src0, src1
+    v_cmpx_gt_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_f64                  dst, src0, src1
+    v_cmpx_gt_i16                  dst, src0, src1
+    v_cmpx_gt_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_i32                  dst, src0, src1
+    v_cmpx_gt_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_i64                  dst, src0, src1
+    v_cmpx_gt_u16                  dst, src0, src1
+    v_cmpx_gt_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_u32                  dst, src0, src1
+    v_cmpx_gt_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_u64                  dst, src0, src1
+    v_cmpx_le_f16                  dst, src0, src1
+    v_cmpx_le_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_f32                  dst, src0, src1
+    v_cmpx_le_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_f64                  dst, src0, src1
+    v_cmpx_le_i16                  dst, src0, src1
+    v_cmpx_le_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_i32                  dst, src0, src1
+    v_cmpx_le_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_i64                  dst, src0, src1
+    v_cmpx_le_u16                  dst, src0, src1
+    v_cmpx_le_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_u32                  dst, src0, src1
+    v_cmpx_le_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_u64                  dst, src0, src1
+    v_cmpx_lg_f16                  dst, src0, src1
+    v_cmpx_lg_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lg_f32                  dst, src0, src1
+    v_cmpx_lg_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lg_f64                  dst, src0, src1
+    v_cmpx_lt_f16                  dst, src0, src1
+    v_cmpx_lt_f16_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_f32                  dst, src0, src1
+    v_cmpx_lt_f32_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_f64                  dst, src0, src1
+    v_cmpx_lt_i16                  dst, src0, src1
+    v_cmpx_lt_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_i32                  dst, src0, src1
+    v_cmpx_lt_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_i64                  dst, src0, src1
+    v_cmpx_lt_u16                  dst, src0, src1
+    v_cmpx_lt_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_u32                  dst, src0, src1
+    v_cmpx_lt_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_u64                  dst, src0, src1
+    v_cmpx_ne_i16                  dst, src0, src1
+    v_cmpx_ne_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_i32                  dst, src0, src1
+    v_cmpx_ne_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_i64                  dst, src0, src1
+    v_cmpx_ne_u16                  dst, src0, src1
+    v_cmpx_ne_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_u32                  dst, src0, src1
+    v_cmpx_ne_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_u64                  dst, src0, src1
+    v_cmpx_neq_f16                 dst, src0, src1
+    v_cmpx_neq_f16_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_neq_f32                 dst, src0, src1
+    v_cmpx_neq_f32_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_neq_f64                 dst, src0, src1
+    v_cmpx_nge_f16                 dst, src0, src1
+    v_cmpx_nge_f16_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nge_f32                 dst, src0, src1
+    v_cmpx_nge_f32_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nge_f64                 dst, src0, src1
+    v_cmpx_ngt_f16                 dst, src0, src1
+    v_cmpx_ngt_f16_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ngt_f32                 dst, src0, src1
+    v_cmpx_ngt_f32_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ngt_f64                 dst, src0, src1
+    v_cmpx_nle_f16                 dst, src0, src1
+    v_cmpx_nle_f16_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nle_f32                 dst, src0, src1
+    v_cmpx_nle_f32_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nle_f64                 dst, src0, src1
+    v_cmpx_nlg_f16                 dst, src0, src1
+    v_cmpx_nlg_f16_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlg_f32                 dst, src0, src1
+    v_cmpx_nlg_f32_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlg_f64                 dst, src0, src1
+    v_cmpx_nlt_f16                 dst, src0, src1
+    v_cmpx_nlt_f16_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlt_f32                 dst, src0, src1
+    v_cmpx_nlt_f32_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlt_f64                 dst, src0, src1
+    v_cmpx_o_f16                   dst, src0, src1
+    v_cmpx_o_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_o_f32                   dst, src0, src1
+    v_cmpx_o_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_o_f64                   dst, src0, src1
+    v_cmpx_t_i16                   dst, src0, src1
+    v_cmpx_t_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_i32                   dst, src0, src1
+    v_cmpx_t_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_i64                   dst, src0, src1
+    v_cmpx_t_u16                   dst, src0, src1
+    v_cmpx_t_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_u32                   dst, src0, src1
+    v_cmpx_t_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_u64                   dst, src0, src1
+    v_cmpx_tru_f16                 dst, src0, src1
+    v_cmpx_tru_f16_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_tru_f32                 dst, src0, src1
+    v_cmpx_tru_f32_sdwa            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_tru_f64                 dst, src0, src1
+    v_cmpx_u_f16                   dst, src0, src1
+    v_cmpx_u_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_u_f32                   dst, src0, src1
+    v_cmpx_u_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_u_f64                   dst, src0, src1

llvm/trunk/docs/AMDGPUAsmGFX9.rst

+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+===========================
+Syntax of GFX9 Instructions
+===========================
+
+.. contents::
+  :local:
+
+
+DS
+===========================
+
+.. parsed-literal::
+
+    ds_add_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_b32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_b64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_rtn_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_rtn_b64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_src2_b32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_src2_b64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_append                      dst                            :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_bpermute_b32                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
+    ds_cmpst_b32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_b64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_f32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_f64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_b32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_b64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_f32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_f64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_condxchg32_rtn_b64          dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_consume                     dst                            :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_barrier                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_init                    src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_br                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_p                                                 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_release_all                                       :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_v                                                 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_f64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_i32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_i64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_f64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_i32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_i64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_f32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_f64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_i32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_i64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_f32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_f64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_i32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_i64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_f32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_f64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_i32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_i64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_f32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_f64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_i32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_i64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_b32                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_b64                   src0, src1, src2               :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_rtn_b32               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_rtn_b64               dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_nop
+    ds_or_b32                      src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_b64                      src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_rtn_b32                  dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_rtn_b64                  dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_src2_b32                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_src2_b64                 src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_ordered_count               dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_permute_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>`
+    ds_read2_b32                   dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2_b64                   dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2st64_b32               dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2st64_b64               dst, src0                      :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b128                   dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b32                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b64                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b96                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i16                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i8                     dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i8_d16                 dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i8_d16_hi              dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u16                    dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u16_d16                dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u16_d16_hi             dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u8                     dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u8_d16                 dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u8_d16_hi              dst, src0                      :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_rtn_u32                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_rtn_u64                dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_src2_u32               src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_src2_u64               src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_u32                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_u64                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_rtn_u32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_rtn_u64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_src2_u32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_src2_u64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_u32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_u64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_swizzle_b32                 dst, src0                      :ref:`sw_offset16<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrap_rtn_b32                dst, src0, src1, src2          :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2_b32                  src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2_b64                  src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2st64_b32              src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2st64_b64              src0, src1, src2               :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b128                  src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b16                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b16_d16_hi            src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b32                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b64                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b8                    src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b8_d16_hi             src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b96                   src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_src2_b32              src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_src2_b64              src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2_rtn_b32             dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2_rtn_b64             dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2st64_rtn_b32         dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2st64_rtn_b64         dst, src0, src1, src2          :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg_rtn_b32              dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg_rtn_b64              dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_b32                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_b64                     src0, src1                     :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_rtn_b32                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_rtn_b64                 dst, src0, src1                :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_src2_b32                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_src2_b64                src0                           :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+
+EXP
+===========================
+
+.. parsed-literal::
+
+    exp                            dst, src0, src1, src2, src3    :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
+
+FLAT
+===========================
+
+.. parsed-literal::
+
+    flat_atomic_add                dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_add_x2             dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_and                dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_and_x2             dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_cmpswap            dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_cmpswap_x2         dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_dec                dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_dec_x2             dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_inc                dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_inc_x2             dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_or                 dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_or_x2              dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smax               dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smax_x2            dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smin               dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smin_x2            dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_sub                dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_sub_x2             dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_swap               dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_swap_x2            dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umax               dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umax_x2            dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umin               dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umin_x2            dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_xor                dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_xor_x2             dst, src0, src1                :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dword                dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx2              dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx3              dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dwordx4              dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sbyte                dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sbyte_d16            dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sbyte_d16_hi         dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_short_d16            dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_short_d16_hi         dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_sshort               dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ubyte                dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ubyte_d16            dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ubyte_d16_hi         dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_ushort               dst, src0                      :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_byte                src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_byte_d16_hi         src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dword               src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx2             src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx3             src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_dwordx4             src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_short               src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_store_short_d16_hi        src0, src1                     :ref:`flat_offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_add              dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_add_x2           dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_and              dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_and_x2           dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_cmpswap          dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_cmpswap_x2       dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_dec              dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_dec_x2           dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_inc              dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_inc_x2           dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_or               dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_or_x2            dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_smax             dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_smax_x2          dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_smin             dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_smin_x2          dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_sub              dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_sub_x2           dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_swap             dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_swap_x2          dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_umax             dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_umax_x2          dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_umin             dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_umin_x2          dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_xor              dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_atomic_xor_x2           dst, src0, src1, src2          :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_load_dword              dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_load_dwordx2            dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_load_dwordx3            dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_load_dwordx4            dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_load_sbyte              dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_load_sbyte_d16          dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_load_sbyte_d16_hi       dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_load_short_d16          dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_load_short_d16_hi       dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_load_sshort             dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_load_ubyte              dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_load_ubyte_d16          dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_load_ubyte_d16_hi       dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_load_ushort             dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_store_byte              src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_store_byte_d16_hi       src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_store_dword             src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_store_dwordx2           src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_store_dwordx3           src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_store_dwordx4           src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_store_short             src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    global_store_short_d16_hi      src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>`
+    scratch_load_dword             dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_dwordx2           dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_dwordx3           dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_dwordx4           dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_sbyte             dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_sbyte_d16         dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_sbyte_d16_hi      dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_short_d16         dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_short_d16_hi      dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_sshort            dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_ubyte             dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_ubyte_d16         dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_ubyte_d16_hi      dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_load_ushort            dst, src0, src1                :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_byte             src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_byte_d16_hi      src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_dword            src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_dwordx2          src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_dwordx3          src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_dwordx4          src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_short            src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    scratch_store_short_d16_hi     src0, src1, src2               :ref:`flat_offset13<amdgpu_synid_flat_offset13>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
+MIMG
+===========================
+
+.. parsed-literal::
+
+    image_atomic_add               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_and               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_cmpswap           dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_dec               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_inc               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_or                dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_smax              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_smin              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_sub               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_swap              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_umax              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_umin              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_xor               dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_b                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_lz             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_cl               dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_l                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_lz_o             dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_o                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_get_resinfo              dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load                     dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_load_mip                 dst, src0, src1                :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_lz              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cl                dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_l                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_lz_o              dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_o                 dst, src0, src1, src2          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_store                    src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_store_mip                src0, src1, src2               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+
+MUBUF
+===========================
+
+.. parsed-literal::
+
+    buffer_atomic_add              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_add_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap_x2       dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or               dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or_x2            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin_x2          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor_x2           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dword              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_dwordx2            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dwordx3            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dwordx4            dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_x       dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_xy      dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_xyz     dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_d16_xyzw    dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_x           dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_format_xy          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_xyz         dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_xyzw        dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_sbyte              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_sbyte_d16          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_sbyte_d16_hi       dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_short_d16          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_short_d16_hi       dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_sshort             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_ubyte              dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_ubyte_d16          dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_ubyte_d16_hi       dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_ushort             dst, src0, src1, src2          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_store_byte              src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_byte_d16_hi       src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dword             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx2           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx3           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx4           src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_x      src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_xy     src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_xyz    src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_xyzw   src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_x          src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xy         src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyz        src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyzw       src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_short             src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_short_d16_hi      src0, src1, src2, src3         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_wbinvl1
+    buffer_wbinvl1_vol
+
+SMEM
+===========================
+
+.. parsed-literal::
+
+    s_buffer_load_dword            dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx16         dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx2          dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx4          dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dwordx8          dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_store_dword           src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_store_dwordx2         src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_store_dwordx4         src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
+    s_dcache_inv
+    s_dcache_inv_vol
+    s_dcache_wb
+    s_dcache_wb_vol
+    s_load_dword                   dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx16                dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx2                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx4                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_load_dwordx8                 dst, src0, src1                :ref:`glc<amdgpu_synid_glc>`
+    s_memrealtime                  dst
+    s_memtime                      dst
+    s_store_dword                  src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
+    s_store_dwordx2                src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
+    s_store_dwordx4                src0, src1, src2               :ref:`glc<amdgpu_synid_glc>`
+
+SOP1
+===========================
+
+.. parsed-literal::
+
+    s_abs_i32                      dst, src0
+    s_and_saveexec_b64             dst, src0
+    s_andn2_saveexec_b64           dst, src0
+    s_bcnt0_i32_b32                dst, src0
+    s_bcnt0_i32_b64                dst, src0
+    s_bcnt1_i32_b32                dst, src0
+    s_bcnt1_i32_b64                dst, src0
+    s_bitset0_b32                  dst, src0
+    s_bitset0_b64                  dst, src0
+    s_bitset1_b32                  dst, src0
+    s_bitset1_b64                  dst, src0
+    s_brev_b32                     dst, src0
+    s_brev_b64                     dst, src0
+    s_cbranch_join                 src0
+    s_cmov_b32                     dst, src0
+    s_cmov_b64                     dst, src0
+    s_ff0_i32_b32                  dst, src0
+    s_ff0_i32_b64                  dst, src0
+    s_ff1_i32_b32                  dst, src0
+    s_ff1_i32_b64                  dst, src0
+    s_flbit_i32                    dst, src0
+    s_flbit_i32_b32                dst, src0
+    s_flbit_i32_b64                dst, src0
+    s_flbit_i32_i64                dst, src0
+    s_getpc_b64                    dst
+    s_mov_b32                      dst, src0
+    s_mov_b64                      dst, src0
+    s_mov_fed_b32                  dst, src0
+    s_movreld_b32                  dst, src0
+    s_movreld_b64                  dst, src0
+    s_movrels_b32                  dst, src0
+    s_movrels_b64                  dst, src0
+    s_nand_saveexec_b64            dst, src0
+    s_nor_saveexec_b64             dst, src0
+    s_not_b32                      dst, src0
+    s_not_b64                      dst, src0
+    s_or_saveexec_b64              dst, src0
+    s_orn2_saveexec_b64            dst, src0
+    s_quadmask_b32                 dst, src0
+    s_quadmask_b64                 dst, src0
+    s_rfe_b64                      src0
+    s_set_gpr_idx_idx              src0
+    s_setpc_b64                    src0
+    s_sext_i32_i16                 dst, src0
+    s_sext_i32_i8                  dst, src0
+    s_swappc_b64                   dst, src0
+    s_wqm_b32                      dst, src0
+    s_wqm_b64                      dst, src0
+    s_xnor_saveexec_b64            dst, src0
+    s_xor_saveexec_b64             dst, src0
+
+SOP2
+===========================
+
+.. parsed-literal::
+
+    s_absdiff_i32                  dst, src0, src1
+    s_add_i32                      dst, src0, src1
+    s_add_u32                      dst, src0, src1
+    s_addc_u32                     dst, src0, src1
+    s_and_b32                      dst, src0, src1
+    s_and_b64                      dst, src0, src1
+    s_andn2_b32                    dst, src0, src1
+    s_andn2_b64                    dst, src0, src1
+    s_ashr_i32                     dst, src0, src1
+    s_ashr_i64                     dst, src0, src1
+    s_bfe_i32                      dst, src0, src1
+    s_bfe_i64                      dst, src0, src1
+    s_bfe_u32                      dst, src0, src1
+    s_bfe_u64                      dst, src0, src1
+    s_bfm_b32                      dst, src0, src1
+    s_bfm_b64                      dst, src0, src1
+    s_cbranch_g_fork               src0, src1
+    s_cselect_b32                  dst, src0, src1
+    s_cselect_b64                  dst, src0, src1
+    s_lshl_b32                     dst, src0, src1
+    s_lshl_b64                     dst, src0, src1
+    s_lshr_b32                     dst, src0, src1
+    s_lshr_b64                     dst, src0, src1
+    s_max_i32                      dst, src0, src1
+    s_max_u32                      dst, src0, src1
+    s_min_i32                      dst, src0, src1
+    s_min_u32                      dst, src0, src1
+    s_mul_i32                      dst, src0, src1
+    s_nand_b32                     dst, src0, src1
+    s_nand_b64                     dst, src0, src1
+    s_nor_b32                      dst, src0, src1
+    s_nor_b64                      dst, src0, src1
+    s_or_b32                       dst, src0, src1
+    s_or_b64                       dst, src0, src1
+    s_orn2_b32                     dst, src0, src1
+    s_orn2_b64                     dst, src0, src1
+    s_pack_hh_b32_b16              dst, src0, src1
+    s_pack_lh_b32_b16              dst, src0, src1
+    s_pack_ll_b32_b16              dst, src0, src1
+    s_rfe_restore_b64              src0, src1
+    s_sub_i32                      dst, src0, src1
+    s_sub_u32                      dst, src0, src1
+    s_subb_u32                     dst, src0, src1
+    s_xnor_b32                     dst, src0, src1
+    s_xnor_b64                     dst, src0, src1
+    s_xor_b32                      dst, src0, src1
+    s_xor_b64                      dst, src0, src1
+
+SOPC
+===========================
+
+.. parsed-literal::
+
+    s_bitcmp0_b32                  src0, src1
+    s_bitcmp0_b64                  src0, src1
+    s_bitcmp1_b32                  src0, src1
+    s_bitcmp1_b64                  src0, src1
+    s_cmp_eq_i32                   src0, src1
+    s_cmp_eq_u32                   src0, src1
+    s_cmp_eq_u64                   src0, src1
+    s_cmp_ge_i32                   src0, src1
+    s_cmp_ge_u32                   src0, src1
+    s_cmp_gt_i32                   src0, src1
+    s_cmp_gt_u32                   src0, src1
+    s_cmp_le_i32                   src0, src1
+    s_cmp_le_u32                   src0, src1
+    s_cmp_lg_i32                   src0, src1
+    s_cmp_lg_u32                   src0, src1
+    s_cmp_lg_u64                   src0, src1
+    s_cmp_lt_i32                   src0, src1
+    s_cmp_lt_u32                   src0, src1
+    s_set_gpr_idx_on               src0, src1
+    s_setvskip                     src0, src1
+
+SOPK
+===========================
+
+.. parsed-literal::
+
+    s_addk_i32                     dst, src0
+    s_cbranch_i_fork               src0, src1
+    s_cmovk_i32                    dst, src0
+    s_cmpk_eq_i32                  src0, src1
+    s_cmpk_eq_u32                  src0, src1
+    s_cmpk_ge_i32                  src0, src1
+    s_cmpk_ge_u32                  src0, src1
+    s_cmpk_gt_i32                  src0, src1
+    s_cmpk_gt_u32                  src0, src1
+    s_cmpk_le_i32                  src0, src1
+    s_cmpk_le_u32                  src0, src1
+    s_cmpk_lg_i32                  src0, src1
+    s_cmpk_lg_u32                  src0, src1
+    s_cmpk_lt_i32                  src0, src1
+    s_cmpk_lt_u32                  src0, src1
+    s_getreg_b32                   dst, src0
+    s_movk_i32                     dst, src0
+    s_mulk_i32                     dst, src0
+    s_setreg_b32                   dst, src0
+    s_setreg_imm32_b32             dst, src0
+
+SOPP
+===========================
+
+.. parsed-literal::
+
+    s_barrier
+    s_branch                       src0
+    s_cbranch_cdbgsys              src0
+    s_cbranch_cdbgsys_and_user     src0
+    s_cbranch_cdbgsys_or_user      src0
+    s_cbranch_cdbguser             src0
+    s_cbranch_execnz               src0
+    s_cbranch_execz                src0
+    s_cbranch_scc0                 src0
+    s_cbranch_scc1                 src0
+    s_cbranch_vccnz                src0
+    s_cbranch_vccz                 src0
+    s_decperflevel                 src0
+    s_endpgm
+    s_endpgm_saved
+    s_icache_inv
+    s_incperflevel                 src0
+    s_nop                          src0
+    s_sendmsg                      src0
+    s_sendmsghalt                  src0
+    s_set_gpr_idx_mode             src0
+    s_set_gpr_idx_off
+    s_sethalt                      src0
+    s_setkill                      src0
+    s_setprio                      src0
+    s_sleep                        src0
+    s_trap                         src0
+    s_ttracedata
+    s_waitcnt                      src0
+    s_wakeup
+
+VINTRP
+===========================
+
+.. parsed-literal::
+
+    v_interp_mov_f32               dst, src0, src1
+    v_interp_p1_f32                dst, src0, src1
+    v_interp_p2_f32                dst, src0, src1
+
+VOP1
+===========================
+
+.. parsed-literal::
+
+    v_bfrev_b32                    dst, src0
+    v_bfrev_b32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_bfrev_b32_sdwa               dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ceil_f16                     dst, src0
+    v_ceil_f16_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ceil_f16_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ceil_f32                     dst, src0
+    v_ceil_f32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ceil_f32_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ceil_f64                     dst, src0
+    v_clrexcp
+    v_cos_f16                      dst, src0
+    v_cos_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cos_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cos_f32                      dst, src0
+    v_cos_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cos_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_f32                  dst, src0
+    v_cvt_f16_f32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f16_f32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_i16                  dst, src0
+    v_cvt_f16_i16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f16_i16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_u16                  dst, src0
+    v_cvt_f16_u16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f16_u16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_f16                  dst, src0
+    v_cvt_f32_f16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_f16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_f64                  dst, src0
+    v_cvt_f32_i32                  dst, src0
+    v_cvt_f32_i32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_i32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_u32                  dst, src0
+    v_cvt_f32_u32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_u32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte0               dst, src0
+    v_cvt_f32_ubyte0_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte0_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte1               dst, src0
+    v_cvt_f32_ubyte1_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte1_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte2               dst, src0
+    v_cvt_f32_ubyte2_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte2_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte3               dst, src0
+    v_cvt_f32_ubyte3_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_f32_ubyte3_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f64_f32                  dst, src0
+    v_cvt_f64_i32                  dst, src0
+    v_cvt_f64_u32                  dst, src0
+    v_cvt_flr_i32_f32              dst, src0
+    v_cvt_flr_i32_f32_dpp          dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_flr_i32_f32_sdwa         dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_i16_f16                  dst, src0
+    v_cvt_i16_f16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_i16_f16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_i32_f32                  dst, src0
+    v_cvt_i32_f32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_i32_f32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_i32_f64                  dst, src0
+    v_cvt_off_f32_i4               dst, src0
+    v_cvt_off_f32_i4_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_off_f32_i4_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_rpi_i32_f32              dst, src0
+    v_cvt_rpi_i32_f32_dpp          dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_rpi_i32_f32_sdwa         dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_u16_f16                  dst, src0
+    v_cvt_u16_f16_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_u16_f16_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_u32_f32                  dst, src0
+    v_cvt_u32_f32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_cvt_u32_f32_sdwa             dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_u32_f64                  dst, src0
+    v_exp_f16                      dst, src0
+    v_exp_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_exp_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_exp_f32                      dst, src0
+    v_exp_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_exp_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_exp_legacy_f32               dst, src0
+    v_exp_legacy_f32_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_exp_legacy_f32_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ffbh_i32                     dst, src0
+    v_ffbh_i32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ffbh_i32_sdwa                dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ffbh_u32                     dst, src0
+    v_ffbh_u32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ffbh_u32_sdwa                dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ffbl_b32                     dst, src0
+    v_ffbl_b32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ffbl_b32_sdwa                dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_floor_f16                    dst, src0
+    v_floor_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_floor_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_floor_f32                    dst, src0
+    v_floor_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_floor_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_floor_f64                    dst, src0
+    v_fract_f16                    dst, src0
+    v_fract_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_fract_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_fract_f32                    dst, src0
+    v_fract_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_fract_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_fract_f64                    dst, src0
+    v_frexp_exp_i16_f16            dst, src0
+    v_frexp_exp_i16_f16_dpp        dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_exp_i16_f16_sdwa       dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_exp_i32_f32            dst, src0
+    v_frexp_exp_i32_f32_dpp        dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_exp_i32_f32_sdwa       dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_exp_i32_f64            dst, src0
+    v_frexp_mant_f16               dst, src0
+    v_frexp_mant_f16_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_mant_f16_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_mant_f32               dst, src0
+    v_frexp_mant_f32_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_frexp_mant_f32_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_mant_f64               dst, src0
+    v_log_f16                      dst, src0
+    v_log_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_log_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_log_f32                      dst, src0
+    v_log_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_log_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_log_legacy_f32               dst, src0
+    v_log_legacy_f32_dpp           dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_log_legacy_f32_sdwa          dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_mov_b32                      dst, src0
+    v_mov_b32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mov_b32_sdwa                 dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_mov_fed_b32                  dst, src0
+    v_mov_fed_b32_dpp              dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mov_fed_b32_sdwa             dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_nop
+    v_not_b32                      dst, src0
+    v_not_b32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_not_b32_sdwa                 dst, src0                      :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rcp_f16                      dst, src0
+    v_rcp_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rcp_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rcp_f32                      dst, src0
+    v_rcp_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rcp_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rcp_f64                      dst, src0
+    v_rcp_iflag_f32                dst, src0
+    v_rcp_iflag_f32_dpp            dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rcp_iflag_f32_sdwa           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_readfirstlane_b32            dst, src0
+    v_rndne_f16                    dst, src0
+    v_rndne_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rndne_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rndne_f32                    dst, src0
+    v_rndne_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rndne_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rndne_f64                    dst, src0
+    v_rsq_f16                      dst, src0
+    v_rsq_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rsq_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rsq_f32                      dst, src0
+    v_rsq_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_rsq_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rsq_f64                      dst, src0
+    v_sin_f16                      dst, src0
+    v_sin_f16_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sin_f16_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sin_f32                      dst, src0
+    v_sin_f32_dpp                  dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sin_f32_sdwa                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sqrt_f16                     dst, src0
+    v_sqrt_f16_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sqrt_f16_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sqrt_f32                     dst, src0
+    v_sqrt_f32_dpp                 dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sqrt_f32_sdwa                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sqrt_f64                     dst, src0
+    v_swap_b32                     dst, src0
+    v_trunc_f16                    dst, src0
+    v_trunc_f16_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_trunc_f16_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_trunc_f32                    dst, src0
+    v_trunc_f32_dpp                dst, src0                      :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_trunc_f32_sdwa               dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_trunc_f64                    dst, src0
+
+VOP2
+===========================
+
+.. parsed-literal::
+
+    v_add_co_u32                   dst0, dst1, src0, src1
+    v_add_co_u32_dpp               dst0, dst1, src0, src1         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_co_u32_sdwa              dst0, dst1, src0, src1         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_f16                      dst, src0, src1
+    v_add_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_f32                      dst, src0, src1
+    v_add_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_u16                      dst, src0, src1
+    v_add_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_u16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_u32                      dst, src0, src1
+    v_add_u32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_add_u32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_addc_co_u32                  dst0, dst1, src0, src1, src2
+    v_addc_co_u32_dpp              dst0, dst1, src0, src1, src2   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_addc_co_u32_sdwa             dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_and_b32                      dst, src0, src1
+    v_and_b32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_and_b32_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_ashrrev_i16                  dst, src0, src1
+    v_ashrrev_i16_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ashrrev_i16_sdwa             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_ashrrev_i32                  dst, src0, src1
+    v_ashrrev_i32_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ashrrev_i32_sdwa             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cndmask_b32                  dst, src0, src1, src2
+    v_ldexp_f16                    dst, src0, src1
+    v_ldexp_f16_dpp                dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_ldexp_f16_sdwa               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshlrev_b16                  dst, src0, src1
+    v_lshlrev_b16_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshlrev_b16_sdwa             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshlrev_b32                  dst, src0, src1
+    v_lshlrev_b32_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshlrev_b32_sdwa             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshrrev_b16                  dst, src0, src1
+    v_lshrrev_b16_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshrrev_b16_sdwa             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshrrev_b32                  dst, src0, src1
+    v_lshrrev_b32_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_lshrrev_b32_sdwa             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mac_f16                      dst, src0, src1
+    v_mac_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mac_f32                      dst, src0, src1
+    v_mac_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_madak_f16                    dst, src0, src1, src2
+    v_madak_f32                    dst, src0, src1, src2
+    v_madmk_f16                    dst, src0, src1, src2
+    v_madmk_f32                    dst, src0, src1, src2
+    v_max_f16                      dst, src0, src1
+    v_max_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_f32                      dst, src0, src1
+    v_max_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_i16                      dst, src0, src1
+    v_max_i16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_i16_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_i32                      dst, src0, src1
+    v_max_i32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_i32_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_u16                      dst, src0, src1
+    v_max_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_u16_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_u32                      dst, src0, src1
+    v_max_u32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_max_u32_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_f16                      dst, src0, src1
+    v_min_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_f32                      dst, src0, src1
+    v_min_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_i16                      dst, src0, src1
+    v_min_i16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_i16_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_i32                      dst, src0, src1
+    v_min_i32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_i32_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_u16                      dst, src0, src1
+    v_min_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_u16_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_u32                      dst, src0, src1
+    v_min_u32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_min_u32_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_f16                      dst, src0, src1
+    v_mul_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_f32                      dst, src0, src1
+    v_mul_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_hi_i32_i24               dst, src0, src1
+    v_mul_hi_i32_i24_dpp           dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_hi_i32_i24_sdwa          dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_hi_u32_u24               dst, src0, src1
+    v_mul_hi_u32_u24_dpp           dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_hi_u32_u24_sdwa          dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_i32_i24                  dst, src0, src1
+    v_mul_i32_i24_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_i32_i24_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_legacy_f32               dst, src0, src1
+    v_mul_legacy_f32_dpp           dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_legacy_f32_sdwa          dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_lo_u16                   dst, src0, src1
+    v_mul_lo_u16_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_lo_u16_sdwa              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_u32_u24                  dst, src0, src1
+    v_mul_u32_u24_dpp              dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_mul_u32_u24_sdwa             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_or_b32                       dst, src0, src1
+    v_or_b32_dpp                   dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_or_b32_sdwa                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_co_u32                   dst0, dst1, src0, src1
+    v_sub_co_u32_dpp               dst0, dst1, src0, src1         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_co_u32_sdwa              dst0, dst1, src0, src1         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_f16                      dst, src0, src1
+    v_sub_f16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_f16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_f32                      dst, src0, src1
+    v_sub_f32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_f32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_u16                      dst, src0, src1
+    v_sub_u16_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_u16_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_u32                      dst, src0, src1
+    v_sub_u32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_sub_u32_sdwa                 dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subb_co_u32                  dst0, dst1, src0, src1, src2
+    v_subb_co_u32_dpp              dst0, dst1, src0, src1, src2   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subb_co_u32_sdwa             dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subbrev_co_u32               dst0, dst1, src0, src1, src2
+    v_subbrev_co_u32_dpp           dst0, dst1, src0, src1, src2   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subbrev_co_u32_sdwa          dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_co_u32                dst0, dst1, src0, src1
+    v_subrev_co_u32_dpp            dst0, dst1, src0, src1         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_co_u32_sdwa           dst0, dst1, src0, src1         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_f16                   dst, src0, src1
+    v_subrev_f16_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_f16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_f32                   dst, src0, src1
+    v_subrev_f32_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_f32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_u16                   dst, src0, src1
+    v_subrev_u16_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_u16_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_u32                   dst, src0, src1
+    v_subrev_u32_dpp               dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_subrev_u32_sdwa              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_xor_b32                      dst, src0, src1
+    v_xor_b32_dpp                  dst, src0, src1                :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+    v_xor_b32_sdwa                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+
+VOP3
+===========================
+
+.. parsed-literal::
+
+    v_add3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_add_co_u32_e64               dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
+    v_add_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_i16                      dst, src0, src1                :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_i32                      dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_add_lshl_u32                 dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_add_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_add_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_addc_co_u32_e64              dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_alignbit_b32                 dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
+    v_alignbyte_b32                dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
+    v_and_b32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_and_or_b32                   dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_ashrrev_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_ashrrev_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_ashrrev_i64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_bcnt_u32_b32                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_bfe_i32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_bfe_u32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_bfi_b32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_bfm_b32                      dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_bfrev_b32_e64                dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_ceil_f16_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ceil_f32_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ceil_f64_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_clrexcp_e64                                                 :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_class_f16_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_class_f32_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_class_f64_e64            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_eq_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_f32_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_f64_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_i16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_i32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_i64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_u16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_u32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_f_u64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ge_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_gt_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_le_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lg_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lg_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lg_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_lt_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ne_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_neq_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_neq_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_neq_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nge_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nge_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nge_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ngt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ngt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_ngt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nle_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nle_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nle_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlg_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlg_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlg_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_nlt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_o_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_o_f32_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_o_f64_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_i16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_i32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_i64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_u16_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_u32_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_t_u64_e64                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_tru_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_tru_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_tru_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_u_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_u_f32_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmp_u_f64_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_class_f16_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_class_f32_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_class_f64_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_eq_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_f_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ge_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_gt_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_le_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lg_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lg_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lg_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_f16_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_f32_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_f64_e64              dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_lt_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_i16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_i32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_i64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_u16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_u32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ne_u64_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_neq_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_neq_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_neq_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nge_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nge_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nge_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ngt_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ngt_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_ngt_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nle_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nle_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nle_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlg_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlg_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlg_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlt_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlt_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_nlt_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_o_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_o_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_o_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_i16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_i32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_i64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_t_u64_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_tru_f16_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_tru_f32_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_tru_f64_e64             dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_u_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_u_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cmpx_u_f64_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cndmask_b32_e64              dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_cos_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cos_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubeid_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubema_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubesc_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubetc_f32                   dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_f32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_i16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_u16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_f16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_f64_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_i32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_u32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte0_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte1_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte2_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte3_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_f32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_i32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_u32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_flr_i32_f32_e64          dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_i16_f16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_i32_f32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_i32_f64_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_off_f32_i4_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_i16_i32               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_u16_u32               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_u8_f32                dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pkaccum_u8_f32           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pknorm_i16_f16           dst, src0, src1                :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pknorm_i16_f32           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pknorm_u16_f16           dst, src0, src1                :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pknorm_u16_f32           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pkrtz_f16_f32            dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_rpi_i32_f32_e64          dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_u16_f16_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_u32_f32_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_u32_f64_e64              dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f16                dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f32                dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f64                dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_legacy_f16         dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f32                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f64                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_scale_f32                dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_div_scale_f64                dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_exp_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_legacy_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_i32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_u32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_ffbl_b32_e64                 dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_floor_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_floor_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_floor_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f16                      dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f64                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_legacy_f16               dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_exp_i16_f16_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_exp_i32_f32_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_exp_i32_f64_e64        dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f16_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f64_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_mov_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p1_f32_e64            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p1ll_f16              dst, src0, src1                :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p1lv_f16              dst, src0, src1, src2          :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p2_f16                dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p2_f32_e64            dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p2_legacy_f16         dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f16_e64                dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f32                    dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f64                    dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lerp_u8                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_log_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_log_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_log_legacy_f32_e64           dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lshl_add_u32                 dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_lshl_or_b32                  dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_lshlrev_b16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_lshlrev_b32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_lshlrev_b64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_lshrrev_b16_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_lshrrev_b32_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_lshrrev_b64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mac_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mac_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_f16                      dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_f32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i16                      dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i32_i16                  dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i32_i24                  dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i64_i32                  dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_legacy_f16               dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_legacy_f32               dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_legacy_i16               dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_legacy_u16               dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u16                      dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u32_u16                  dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u32_u24                  dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u64_u32                  dst0, dst1, src0, src1, src2   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_f16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_i16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_max3_u16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_max_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_i16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_max_i32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_max_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_max_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mbcnt_hi_u32_b32             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mbcnt_lo_u32_b32             dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_med3_f16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_i16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_med3_u16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_min3_f16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_f32                     dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_i16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_i32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_min3_u16                     dst, src0, src1, src2          :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_u32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_min_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_i16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_min_i32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_min_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_min_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mov_b32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_mov_fed_b32_e64              dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_mqsad_pk_u16_u8              dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mqsad_u32_u8                 dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_msad_u8                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_f64                      dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_i32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_i32_i24_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_u32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_u32_u24_e64           dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_i32_i24_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_legacy_f32_e64           dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_u32                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_mul_u32_u24_e64              dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_nop_e64                                                     :ref:`omod<amdgpu_synid_omod>`
+    v_not_b32_e64                  dst, src0                      :ref:`omod<amdgpu_synid_omod>`
+    v_or3_b32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_or_b32_e64                   dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_pack_b32_f16                 dst, src0, src1                :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`omod<amdgpu_synid_omod>`
+    v_perm_b32                     dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_qsad_pk_u16_u8               dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_f64_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_iflag_f32_e64            dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_readlane_b32                 dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f64_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_hi_u8                    dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_u16                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_u32                      dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_u8                       dst, src0, src1, src2          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sin_f16_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sin_f32_e64                  dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f16_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f32_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f64_e64                 dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_co_u32_e64               dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
+    v_sub_f16_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_f32_e64                  dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_i16                      dst, src0, src1                :ref:`vop3_op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_i32                      dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_sub_u16_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_sub_u32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_subb_co_u32_e64              dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_subbrev_co_u32_e64           dst0, dst1, src0, src1, src2   :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_co_u32_e64            dst0, dst1, src0, src1         :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_f16_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_f32_e64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_u16_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_u32_e64               dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_trig_preop_f64               dst, src0, src1                :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f16_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f32_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f64_e64                dst, src0                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_writelane_b32                dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+    v_xad_u32                      dst, src0, src1, src2          :ref:`omod<amdgpu_synid_omod>`
+    v_xor_b32_e64                  dst, src0, src1                :ref:`omod<amdgpu_synid_omod>`
+
+VOP3P
+===========================
+
+.. parsed-literal::
+
+    v_mad_mix_f32                  dst, src0, src1, src2          :ref:`mad_op_sel<amdgpu_synid_mad_op_sel>` :ref:`mad_op_sel_hi<amdgpu_synid_mad_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_mixhi_f16                dst, src0, src1, src2          :ref:`mad_op_sel<amdgpu_synid_mad_op_sel>` :ref:`mad_op_sel_hi<amdgpu_synid_mad_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_mixlo_f16                dst, src0, src1, src2          :ref:`mad_op_sel<amdgpu_synid_mad_op_sel>` :ref:`mad_op_sel_hi<amdgpu_synid_mad_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_f16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_i16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_u16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_ashrrev_i16               dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_lshlrev_b16               dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_lshrrev_b16               dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_max_f16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_max_i16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_max_u16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_min_f16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_min_i16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_min_u16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_mul_f16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_mul_lo_u16                dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_sub_i16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_sub_u16                   dst, src0, src1                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+
+VOPC
+===========================
+
+.. parsed-literal::
+
+    v_cmp_class_f16                dst, src0, src1
+    v_cmp_class_f16_sdwa           dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_class_f32                dst, src0, src1
+    v_cmp_class_f32_sdwa           dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_class_f64                dst, src0, src1
+    v_cmp_eq_f16                   dst, src0, src1
+    v_cmp_eq_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_f32                   dst, src0, src1
+    v_cmp_eq_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_f64                   dst, src0, src1
+    v_cmp_eq_i16                   dst, src0, src1
+    v_cmp_eq_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_i32                   dst, src0, src1
+    v_cmp_eq_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_i64                   dst, src0, src1
+    v_cmp_eq_u16                   dst, src0, src1
+    v_cmp_eq_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_u32                   dst, src0, src1
+    v_cmp_eq_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_u64                   dst, src0, src1
+    v_cmp_f_f16                    dst, src0, src1
+    v_cmp_f_f16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_f32                    dst, src0, src1
+    v_cmp_f_f32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_f64                    dst, src0, src1
+    v_cmp_f_i16                    dst, src0, src1
+    v_cmp_f_i16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_i32                    dst, src0, src1
+    v_cmp_f_i32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_i64                    dst, src0, src1
+    v_cmp_f_u16                    dst, src0, src1
+    v_cmp_f_u16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_u32                    dst, src0, src1
+    v_cmp_f_u32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_u64                    dst, src0, src1
+    v_cmp_ge_f16                   dst, src0, src1
+    v_cmp_ge_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_f32                   dst, src0, src1
+    v_cmp_ge_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_f64                   dst, src0, src1
+    v_cmp_ge_i16                   dst, src0, src1
+    v_cmp_ge_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_i32                   dst, src0, src1
+    v_cmp_ge_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_i64                   dst, src0, src1
+    v_cmp_ge_u16                   dst, src0, src1
+    v_cmp_ge_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_u32                   dst, src0, src1
+    v_cmp_ge_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_u64                   dst, src0, src1
+    v_cmp_gt_f16                   dst, src0, src1
+    v_cmp_gt_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_f32                   dst, src0, src1
+    v_cmp_gt_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_f64                   dst, src0, src1
+    v_cmp_gt_i16                   dst, src0, src1
+    v_cmp_gt_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_i32                   dst, src0, src1
+    v_cmp_gt_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_i64                   dst, src0, src1
+    v_cmp_gt_u16                   dst, src0, src1
+    v_cmp_gt_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_u32                   dst, src0, src1
+    v_cmp_gt_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_u64                   dst, src0, src1
+    v_cmp_le_f16                   dst, src0, src1
+    v_cmp_le_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_f32                   dst, src0, src1
+    v_cmp_le_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_f64                   dst, src0, src1
+    v_cmp_le_i16                   dst, src0, src1
+    v_cmp_le_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_i32                   dst, src0, src1
+    v_cmp_le_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_i64                   dst, src0, src1
+    v_cmp_le_u16                   dst, src0, src1
+    v_cmp_le_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_u32                   dst, src0, src1
+    v_cmp_le_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_u64                   dst, src0, src1
+    v_cmp_lg_f16                   dst, src0, src1
+    v_cmp_lg_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lg_f32                   dst, src0, src1
+    v_cmp_lg_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lg_f64                   dst, src0, src1
+    v_cmp_lt_f16                   dst, src0, src1
+    v_cmp_lt_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_f32                   dst, src0, src1
+    v_cmp_lt_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_f64                   dst, src0, src1
+    v_cmp_lt_i16                   dst, src0, src1
+    v_cmp_lt_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_i32                   dst, src0, src1
+    v_cmp_lt_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_i64                   dst, src0, src1
+    v_cmp_lt_u16                   dst, src0, src1
+    v_cmp_lt_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_u32                   dst, src0, src1
+    v_cmp_lt_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_u64                   dst, src0, src1
+    v_cmp_ne_i16                   dst, src0, src1
+    v_cmp_ne_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_i32                   dst, src0, src1
+    v_cmp_ne_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_i64                   dst, src0, src1
+    v_cmp_ne_u16                   dst, src0, src1
+    v_cmp_ne_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_u32                   dst, src0, src1
+    v_cmp_ne_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_u64                   dst, src0, src1
+    v_cmp_neq_f16                  dst, src0, src1
+    v_cmp_neq_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_neq_f32                  dst, src0, src1
+    v_cmp_neq_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_neq_f64                  dst, src0, src1
+    v_cmp_nge_f16                  dst, src0, src1
+    v_cmp_nge_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nge_f32                  dst, src0, src1
+    v_cmp_nge_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nge_f64                  dst, src0, src1
+    v_cmp_ngt_f16                  dst, src0, src1
+    v_cmp_ngt_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ngt_f32                  dst, src0, src1
+    v_cmp_ngt_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ngt_f64                  dst, src0, src1
+    v_cmp_nle_f16                  dst, src0, src1
+    v_cmp_nle_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nle_f32                  dst, src0, src1
+    v_cmp_nle_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nle_f64                  dst, src0, src1
+    v_cmp_nlg_f16                  dst, src0, src1
+    v_cmp_nlg_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlg_f32                  dst, src0, src1
+    v_cmp_nlg_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlg_f64                  dst, src0, src1
+    v_cmp_nlt_f16                  dst, src0, src1
+    v_cmp_nlt_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlt_f32                  dst, src0, src1
+    v_cmp_nlt_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlt_f64                  dst, src0, src1
+    v_cmp_o_f16                    dst, src0, src1
+    v_cmp_o_f16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_o_f32                    dst, src0, src1
+    v_cmp_o_f32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_o_f64                    dst, src0, src1
+    v_cmp_t_i16                    dst, src0, src1
+    v_cmp_t_i16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_i32                    dst, src0, src1
+    v_cmp_t_i32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_i64                    dst, src0, src1
+    v_cmp_t_u16                    dst, src0, src1
+    v_cmp_t_u16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_u32                    dst, src0, src1
+    v_cmp_t_u32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_u64                    dst, src0, src1
+    v_cmp_tru_f16                  dst, src0, src1
+    v_cmp_tru_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_tru_f32                  dst, src0, src1
+    v_cmp_tru_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_tru_f64                  dst, src0, src1
+    v_cmp_u_f16                    dst, src0, src1
+    v_cmp_u_f16_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_u_f32                    dst, src0, src1
+    v_cmp_u_f32_sdwa               dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_u_f64                    dst, src0, src1
+    v_cmpx_class_f16               dst, src0, src1
+    v_cmpx_class_f16_sdwa          dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_class_f32               dst, src0, src1
+    v_cmpx_class_f32_sdwa          dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_class_f64               dst, src0, src1
+    v_cmpx_eq_f16                  dst, src0, src1
+    v_cmpx_eq_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_f32                  dst, src0, src1
+    v_cmpx_eq_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_f64                  dst, src0, src1
+    v_cmpx_eq_i16                  dst, src0, src1
+    v_cmpx_eq_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_i32                  dst, src0, src1
+    v_cmpx_eq_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_i64                  dst, src0, src1
+    v_cmpx_eq_u16                  dst, src0, src1
+    v_cmpx_eq_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_u32                  dst, src0, src1
+    v_cmpx_eq_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_u64                  dst, src0, src1
+    v_cmpx_f_f16                   dst, src0, src1
+    v_cmpx_f_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_f32                   dst, src0, src1
+    v_cmpx_f_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_f64                   dst, src0, src1
+    v_cmpx_f_i16                   dst, src0, src1
+    v_cmpx_f_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_i32                   dst, src0, src1
+    v_cmpx_f_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_i64                   dst, src0, src1
+    v_cmpx_f_u16                   dst, src0, src1
+    v_cmpx_f_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_u32                   dst, src0, src1
+    v_cmpx_f_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_u64                   dst, src0, src1
+    v_cmpx_ge_f16                  dst, src0, src1
+    v_cmpx_ge_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_f32                  dst, src0, src1
+    v_cmpx_ge_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_f64                  dst, src0, src1
+    v_cmpx_ge_i16                  dst, src0, src1
+    v_cmpx_ge_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_i32                  dst, src0, src1
+    v_cmpx_ge_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_i64                  dst, src0, src1
+    v_cmpx_ge_u16                  dst, src0, src1
+    v_cmpx_ge_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_u32                  dst, src0, src1
+    v_cmpx_ge_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_u64                  dst, src0, src1
+    v_cmpx_gt_f16                  dst, src0, src1
+    v_cmpx_gt_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_f32                  dst, src0, src1
+    v_cmpx_gt_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_f64                  dst, src0, src1
+    v_cmpx_gt_i16                  dst, src0, src1
+    v_cmpx_gt_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_i32                  dst, src0, src1
+    v_cmpx_gt_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_i64                  dst, src0, src1
+    v_cmpx_gt_u16                  dst, src0, src1
+    v_cmpx_gt_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_u32                  dst, src0, src1
+    v_cmpx_gt_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_u64                  dst, src0, src1
+    v_cmpx_le_f16                  dst, src0, src1
+    v_cmpx_le_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_f32                  dst, src0, src1
+    v_cmpx_le_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_f64                  dst, src0, src1
+    v_cmpx_le_i16                  dst, src0, src1
+    v_cmpx_le_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_i32                  dst, src0, src1
+    v_cmpx_le_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_i64                  dst, src0, src1
+    v_cmpx_le_u16                  dst, src0, src1
+    v_cmpx_le_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_u32                  dst, src0, src1
+    v_cmpx_le_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_u64                  dst, src0, src1
+    v_cmpx_lg_f16                  dst, src0, src1
+    v_cmpx_lg_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lg_f32                  dst, src0, src1
+    v_cmpx_lg_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lg_f64                  dst, src0, src1
+    v_cmpx_lt_f16                  dst, src0, src1
+    v_cmpx_lt_f16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_f32                  dst, src0, src1
+    v_cmpx_lt_f32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_f64                  dst, src0, src1
+    v_cmpx_lt_i16                  dst, src0, src1
+    v_cmpx_lt_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_i32                  dst, src0, src1
+    v_cmpx_lt_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_i64                  dst, src0, src1
+    v_cmpx_lt_u16                  dst, src0, src1
+    v_cmpx_lt_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_u32                  dst, src0, src1
+    v_cmpx_lt_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_u64                  dst, src0, src1
+    v_cmpx_ne_i16                  dst, src0, src1
+    v_cmpx_ne_i16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_i32                  dst, src0, src1
+    v_cmpx_ne_i32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_i64                  dst, src0, src1
+    v_cmpx_ne_u16                  dst, src0, src1
+    v_cmpx_ne_u16_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_u32                  dst, src0, src1
+    v_cmpx_ne_u32_sdwa             dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_u64                  dst, src0, src1
+    v_cmpx_neq_f16                 dst, src0, src1
+    v_cmpx_neq_f16_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_neq_f32                 dst, src0, src1
+    v_cmpx_neq_f32_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_neq_f64                 dst, src0, src1
+    v_cmpx_nge_f16                 dst, src0, src1
+    v_cmpx_nge_f16_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nge_f32                 dst, src0, src1
+    v_cmpx_nge_f32_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nge_f64                 dst, src0, src1
+    v_cmpx_ngt_f16                 dst, src0, src1
+    v_cmpx_ngt_f16_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ngt_f32                 dst, src0, src1
+    v_cmpx_ngt_f32_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ngt_f64                 dst, src0, src1
+    v_cmpx_nle_f16                 dst, src0, src1
+    v_cmpx_nle_f16_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nle_f32                 dst, src0, src1
+    v_cmpx_nle_f32_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nle_f64                 dst, src0, src1
+    v_cmpx_nlg_f16                 dst, src0, src1
+    v_cmpx_nlg_f16_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlg_f32                 dst, src0, src1
+    v_cmpx_nlg_f32_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlg_f64                 dst, src0, src1
+    v_cmpx_nlt_f16                 dst, src0, src1
+    v_cmpx_nlt_f16_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlt_f32                 dst, src0, src1
+    v_cmpx_nlt_f32_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlt_f64                 dst, src0, src1
+    v_cmpx_o_f16                   dst, src0, src1
+    v_cmpx_o_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_o_f32                   dst, src0, src1
+    v_cmpx_o_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_o_f64                   dst, src0, src1
+    v_cmpx_t_i16                   dst, src0, src1
+    v_cmpx_t_i16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_i32                   dst, src0, src1
+    v_cmpx_t_i32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_i64                   dst, src0, src1
+    v_cmpx_t_u16                   dst, src0, src1
+    v_cmpx_t_u16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_u32                   dst, src0, src1
+    v_cmpx_t_u32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_u64                   dst, src0, src1
+    v_cmpx_tru_f16                 dst, src0, src1
+    v_cmpx_tru_f16_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_tru_f32                 dst, src0, src1
+    v_cmpx_tru_f32_sdwa            dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_tru_f64                 dst, src0, src1
+    v_cmpx_u_f16                   dst, src0, src1
+    v_cmpx_u_f16_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_u_f32                   dst, src0, src1
+    v_cmpx_u_f32_sdwa              dst, src0, src1                :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_u_f64                   dst, src0, src1

llvm/trunk/docs/AMDGPUOperandSyntax.rst

+=================================================
+Syntax of AMDGPU Assembler Operands and Modifiers
+=================================================
+
+.. contents::
+   :local:
+
+Conventions
+===========
+
+The following conventions are used in syntax description:
+
+    =================== =============================================================
+    Notation            Description
+    =================== =============================================================
+    {0..N}              Any integer value in the range from 0 to N (inclusive).
+                        Unless stated otherwise, this value may be specified as
+                        either a literal or an llvm expression.
+    <x>                 Syntax and meaning of *<x>* is explained elsewhere.
+    =================== =============================================================
+
+.. _amdgpu_syn_operands:
+
+Operands
+========
+
+TBD
+
+.. _amdgpu_syn_modifiers:
+
+Modifiers
+=========
+
+DS Modifiers
+------------
+
+.. _amdgpu_synid_ds_offset8:
+
+ds_offset8
+~~~~~~~~~~
+
+Specifies an immediate unsigned 8-bit offset, in bytes. The default value is 0.
+
+Used with DS instructions which have 2 addresses.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    offset:{0..0xFF}                         Specifies a 8-bit offset.
+    ======================================== ================================================
+
+.. _amdgpu_synid_ds_offset16:
+
+ds_offset16
+~~~~~~~~~~~
+
+Specifies an immediate unsigned 16-bit offset, in bytes. The default value is 0.
+
+Used with DS instructions which have 1 address.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    offset:{0..0xFFFF}                       Specifies a 16-bit offset.
+    ======================================== ================================================
+
+.. _amdgpu_synid_sw_offset16:
+
+sw_offset16
+~~~~~~~~~~~
+
+This is a special modifier which may be used with *ds_swizzle_b32* instruction only.
+Specifies a sizzle pattern in numeric or symbolic form. The default value is 0.
+
+See AMD documentation for more information.
+
+    ======================================================= ===================================================
+    Syntax                                                  Description
+    ======================================================= ===================================================
+    offset:{0..0xFFFF}                                      Specifies a 16-bit swizzle pattern
+                                                            in a numeric form.
+    offset:swizzle(QUAD_PERM,{0..3},{0..3},{0..3},{0..3})   Specifies a quad permute mode pattern; each
+                                                            number is a lane id.
+    offset:swizzle(BITMASK_PERM, "<mask>")                  Specifies a bitmask permute mode pattern
+                                                            which converts a 5-bit lane id to another
+                                                            lane id with which the lane interacts.
+
+                                                            <mask> is a 5 character sequence which
+                                                            specifies how to transform the bits of the
+                                                            lane id. The following characters are allowed:
+
+                                                              * "0" - set bit to 0.
+
+                                                              * "1" - set bit to 1.
+
+                                                              * "p" - preserve bit.
+
+                                                              * "i" - inverse bit.
+
+    offset:swizzle(BROADCAST,{2..32},{0..N})                Specifies a broadcast mode.
+                                                            Broadcasts the value of any particular lane to
+                                                            all lanes in its group.
+
+                                                            The first numeric parameter is a group
+                                                            size and must be equal to 2, 4, 8, 16 or 32.
+
+                                                            The second numeric parameter is an index of the
+                                                            lane being broadcasted. The index must not exceed
+                                                            group size.
+    offset:swizzle(SWAP,{1..16})                            Specifies a swap mode.
+                                                            Swaps the neighboring groups of
+                                                            1, 2, 4, 8 or 16 lanes.
+    offset:swizzle(REVERSE,{2..32})                         Specifies a reverse mode. Reverses
+                                                            the lanes for groups of 2, 4, 8, 16 or 32 lanes.
+    ======================================================= ===================================================
+
+.. _amdgpu_synid_gds:
+
+gds
+~~~
+
+Specifies whether to use GDS or LDS memory (LDS is the default).
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    gds                                      Use GDS memory.
+    ======================================== ================================================
+
+
+EXP Modifiers
+-------------
+
+.. _amdgpu_synid_done:
+
+done
+~~~~
+
+Specifies if this is the last export from the shader to the target. By default, current
+instruction does not finish an export sequence.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    done                                     Indicates the last export operation.
+    ======================================== ================================================
+
+.. _amdgpu_synid_compr:
+
+compr
+~~~~~
+
+Indicates if the data are compressed (not compressed by default).
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    compr                                    Data are compressed.
+    ======================================== ================================================
+
+.. _amdgpu_synid_vm:
+
+vm
+~~
+
+Specifies valid mask flag state (off by default).
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    vm                                       Set valid mask flag.
+    ======================================== ================================================
+
+FLAT Modifiers
+--------------
+
+.. _amdgpu_synid_flat_offset12:
+
+flat_offset12
+~~~~~~~~~~~~~
+
+Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.
+
+Cannot be used with *global/scratch* opcodes. GFX9 only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    offset:{0..4095}                         Specifies a 12-bit unsigned offset.
+    ======================================== ================================================
+
+.. _amdgpu_synid_flat_offset13:
+
+flat_offset13
+~~~~~~~~~~~~~
+
+Specifies an immediate signed 13-bit offset, in bytes. The default value is 0.
+
+Can be used with *global/scratch* opcodes only. GFX9 only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    offset:{-4096..+4095}                    Specifies a 13-bit signed offset.
+    ======================================== ================================================
+
+glc
+~~~
+
+See a description :ref:`here<amdgpu_synid_glc>`.
+
+slc
+~~~
+
+See a description :ref:`here<amdgpu_synid_slc>`.
+
+tfe
+~~~
+
+See a description :ref:`here<amdgpu_synid_tfe>`.
+
+nv
+~~
+
+See a description :ref:`here<amdgpu_synid_nv>`.
+
+MIMG Modifiers
+--------------
+
+.. _amdgpu_synid_dmask:
+
+dmask
+~~~~~
+
+Specifies which channels (image components) are used by the operation. By default, no channels
+are used.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    dmask:{0..15}                            Each bit corresponds to one of 4 image
+                                             components (RGBA). If the specified bit value
+                                             is 0, the component is not used, value 1 means
+                                             that the component is used.
+    ======================================== ================================================
+
+This modifier has some limitations depending on instruction kind:
+
+    ======================================== ================================================
+    Instruction Kind                         Valid dmask Values
+    ======================================== ================================================
+    32-bit atomic cmpswap                    0x3
+    other 32-bit atomic instructions         0x1
+    64-bit atomic cmpswap                    0xF
+    other 64-bit atomic instructions         0x3
+    GATHER4                                  0x1, 0x2, 0x4, 0x8
+    Other instructions                       any value
+    ======================================== ================================================
+
+.. _amdgpu_synid_unorm:
+
+unorm
+~~~~~
+
+Specifies whether address is normalized or not (normalized by default).
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    unorm                                    Force address to be un-normalized.
+    ======================================== ================================================
+
+glc
+~~~
+
+See a description :ref:`here<amdgpu_synid_glc>`.
+
+slc
+~~~
+
+See a description :ref:`here<amdgpu_synid_slc>`.
+
+.. _amdgpu_synid_r128:
+
+r128
+~~~~
+
+Specifies texture resource size. The default size is 256 bits.
+
+GFX7 and GFX8 only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    r128                                     Specifies 128 bits texture resource size.
+    ======================================== ================================================
+
+tfe
+~~~
+
+See a description :ref:`here<amdgpu_synid_tfe>`.
+
+.. _amdgpu_synid_lwe:
+
+lwe
+~~~
+
+Specifies LOD warning status (LOD warning is disabled by default).
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    lwe                                      Enables LOD warning.
+    ======================================== ================================================
+
+.. _amdgpu_synid_da:
+
+da
+~~
+
+Specifies if an array index must be sent to TA. By default, array index is not sent.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    da                                       Send an array-index to TA.
+    ======================================== ================================================
+
+.. _amdgpu_synid_d16:
+
+d16
+~~~
+
+Specifies data size: 16 or 32 bits (32 bits by default). Not supported by GFX7.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    d16                                      Enables 16-bits data mode.
+
+                                             On loads, convert data in memory to 16-bit
+                                             format before storing it in VGPRs.
+
+                                             For stores, convert 16-bit data in VGPRs to
+                                             32 bits before going to memory.
+
+                                             Note that 16-bit data are stored in VGPRs
+                                             unpacked in GFX8.0. In GFX8.1 and GFX9 16-bit
+                                             data are packed.
+    ======================================== ================================================
+
+.. _amdgpu_synid_a16:
+
+a16
+~~~
+
+Specifies size of image address components: 16 or 32 bits (32 bits by default). GFX9 only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    a16                                      Enables 16-bits image address components.
+    ======================================== ================================================
+
+Miscellaneous Modifiers
+-----------------------
+
+.. _amdgpu_synid_glc:
+
+glc
+~~~
+
+This modifier has different meaning for loads, stores, and atomic operations.
+The default value is off (0).
+
+See AMD documentation for details.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    glc                                      Set glc bit to 1.
+    ======================================== ================================================
+
+.. _amdgpu_synid_slc:
+
+slc
+~~~
+
+Specifies cache policy. The default value is off (0).
+
+See AMD documentation for details.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    slc                                      Set slc bit to 1.
+    ======================================== ================================================
+
+.. _amdgpu_synid_tfe:
+
+tfe
+~~~
+
+Controls access to partially resident textures. The default value is off (0).
+
+See AMD documentation for details.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    tfe                                      Set tfe bit to 1.
+    ======================================== ================================================
+
+.. _amdgpu_synid_nv:
+
+nv
+~~
+
+Specifies if instruction is operating on non-volatile memory. By default, memory is volatile.
+
+GFX9 only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    nv                                       Indicates that instruction operates on
+                                             non-volatile memory.
+    ======================================== ================================================
+
+MUBUF/MTBUF Modifiers
+---------------------
+
+.. _amdgpu_synid_idxen:
+
+idxen
+~~~~~
+
+Specifies whether address components include an index. By default, no components are used.
+
+Can be used together with :ref:`offen<amdgpu_synid_offen>`.
+
+Cannot be used with :ref:`addr64<amdgpu_synid_addr64>`.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    idxen                                    Address components include an index.
+    ======================================== ================================================
+
+.. _amdgpu_synid_offen:
+
+offen
+~~~~~
+
+Specifies whether address components include an offset. By default, no components are used.
+
+Can be used together with :ref:`idxen<amdgpu_synid_idxen>`.
+
+Cannot be used with :ref:`addr64<amdgpu_synid_addr64>`.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    offen                                    Address components include an offset.
+    ======================================== ================================================
+
+.. _amdgpu_synid_addr64:
+
+addr64
+~~~~~~
+
+Specifies whether a 64-bit address is used. By default, no address is used.
+
+GFX7 only. Cannot be used with :ref:`offen<amdgpu_synid_offen>` and
+:ref:`idxen<amdgpu_synid_idxen>` modifiers.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    addr64                                   A 64-bit address is used.
+    ======================================== ================================================
+
+.. _amdgpu_synid_buf_offset12:
+
+buf_offset12
+~~~~~~~~~~~~
+
+Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    offset:{0..0xFFF}                        Specifies a 12-bit unsigned offset.
+    ======================================== ================================================
+
+glc
+~~~
+
+See a description :ref:`here<amdgpu_synid_glc>`.
+
+slc
+~~~
+
+See a description :ref:`here<amdgpu_synid_slc>`.
+
+.. _amdgpu_synid_lds:
+
+lds
+~~~
+
+Specifies where to store the result: VGPRs or LDS (VGPRs by default).
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    lds                                      Store result in LDS.
+    ======================================== ================================================
+
+tfe
+~~~
+
+See a description :ref:`here<amdgpu_synid_tfe>`.
+
+.. _amdgpu_synid_dfmt:
+
+dfmt
+~~~~
+
+TBD
+
+.. _amdgpu_synid_nfmt:
+
+nfmt
+~~~~
+
+TBD
+
+SMRD/SMEM Modifiers
+-------------------
+
+glc
+~~~
+
+See a description :ref:`here<amdgpu_synid_glc>`.
+
+nv
+~~
+
+See a description :ref:`here<amdgpu_synid_nv>`.
+
+VINTRP Modifiers
+----------------
+
+.. _amdgpu_synid_high:
+
+high
+~~~~
+
+Specifies which half of the LDS word to use. Low half of LDS word is used by default.
+GFX9 only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    high                                     Use high half of LDS word.
+    ======================================== ================================================
+
+VOP1/VOP2 DPP Modifiers
+-----------------------
+
+GFX8 and GFX9 only.
+
+.. _amdgpu_synid_dpp_ctrl:
+
+dpp_ctrl
+~~~~~~~~
+
+Specifies how data are shared between threads. This is a mandatory modifier.
+There is no default value.
+
+Note. The lanes of a wavefront are organized in four banks and four rows.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    quad_perm:[{0..3},{0..3},{0..3},{0..3}]  Full permute of 4 threads.
+    row_mirror                               Mirror threads within row.
+    row_half_mirror                          Mirror threads within 1/2 row (8 threads).
+    row_bcast:15                             Broadcast 15th thread of each row to next row.
+    row_bcast:31                             Broadcast thread 31 to rows 2 and 3.
+    wave_shl:1                               Wavefront left shift by 1 thread.
+    wave_rol:1                               Wavefront left rotate by 1 thread.
+    wave_shr:1                               Wavefront right shift by 1 thread.
+    wave_ror:1                               Wavefront right rotate by 1 thread.
+    row_shl:{1..15}                          Row shift left by 1-15 threads.
+    row_shr:{1..15}                          Row shift right by 1-15 threads.
+    row_ror:{1..15}                          Row rotate right by 1-15 threads.
+    ======================================== ================================================
+
+.. _amdgpu_synid_row_mask:
+
+row_mask
+~~~~~~~~
+
+Controls which rows are enabled for data sharing. By default, all rows are enabled.
+
+Note. The lanes of a wavefront are organized in four banks and four rows.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    row_mask:{0..15}                         Each of 4 bits in the mask controls one
+                                             row (0 - disabled, 1 - enabled).
+    ======================================== ================================================
+
+.. _amdgpu_synid_bank_mask:
+
+bank_mask
+~~~~~~~~~
+
+Controls which banks are enabled for data sharing. By default, all banks are enabled.
+
+Note. The lanes of a wavefront are organized in four banks and four rows.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    bank_mask:{0..15}                        Each of 4 bits in the mask controls one
+                                             bank (0 - disabled, 1 - enabled).
+    ======================================== ================================================
+
+.. _amdgpu_synid_bound_ctrl:
+
+bound_ctrl
+~~~~~~~~~~
+
+Controls data sharing when accessing an invalid lane. By default, data sharing with
+invalid lanes is disabled.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    bound_ctrl:0                             Enables data sharing with invalid lanes.
+                                             Accessing data from an invalid lane will
+                                             return zero.
+    ======================================== ================================================
+
+VOP1/VOP2/VOPC SDWA Modifiers
+-----------------------------
+
+GFX8 and GFX9 only.
+
+clamp
+~~~~~
+
+See a description :ref:`here<amdgpu_synid_clamp>`.
+
+omod
+~~~~
+
+See a description :ref:`here<amdgpu_synid_omod>`.
+
+GFX9 only.
+
+.. _amdgpu_synid_dst_sel:
+
+dst_sel
+~~~~~~~
+
+Selects which bits in the destination are affected. By default, all bits are affected.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    dst_sel:DWORD                            Use bits 31:0.
+    dst_sel:BYTE_0                           Use bits 7:0.
+    dst_sel:BYTE_1                           Use bits 15:8.
+    dst_sel:BYTE_2                           Use bits 23:16.
+    dst_sel:BYTE_3                           Use bits 31:24.
+    dst_sel:WORD_0                           Use bits 15:0.
+    dst_sel:WORD_1                           Use bits 31:16.
+    ======================================== ================================================
+
+
+.. _amdgpu_synid_dst_unused:
+
+dst_unused
+~~~~~~~~~~
+
+Controls what to do with the bits in the destination which are not selected
+by :ref:`dst_sel<amdgpu_synid_dst_sel>`.
+By default, unused bits are preserved.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    dst_unused:UNUSED_PAD                    Pad with zeros.
+    dst_unused:UNUSED_SEXT                   Sign-extend upper bits, zero lower bits.
+    dst_unused:UNUSED_PRESERVE               Preserve bits.
+    ======================================== ================================================
+
+.. _amdgpu_synid_src0_sel:
+
+src0_sel
+~~~~~~~~
+
+Controls which bits in the src0 are used. By default, all bits are used.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    src0_sel:DWORD                           Use bits 31:0.
+    src0_sel:BYTE_0                          Use bits 7:0.
+    src0_sel:BYTE_1                          Use bits 15:8.
+    src0_sel:BYTE_2                          Use bits 23:16.
+    src0_sel:BYTE_3                          Use bits 31:24.
+    src0_sel:WORD_0                          Use bits 15:0.
+    src0_sel:WORD_1                          Use bits 31:16.
+    ======================================== ================================================
+
+.. _amdgpu_synid_src1_sel:
+
+src1_sel
+~~~~~~~~
+
+Controls which bits in the src1 are used. By default, all bits are used.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    src1_sel:DWORD                           Use bits 31:0.
+    src1_sel:BYTE_0                          Use bits 7:0.
+    src1_sel:BYTE_1                          Use bits 15:8.
+    src1_sel:BYTE_2                          Use bits 23:16.
+    src1_sel:BYTE_3                          Use bits 31:24.
+    src1_sel:WORD_0                          Use bits 15:0.
+    src1_sel:WORD_1                          Use bits 31:16.
+    ======================================== ================================================
+
+VOP1/VOP2/VOPC SDWA Operand Modifiers
+-------------------------------------
+
+Operand modifiers are not used separately. They are applied to source operands.
+
+GFX8 and GFX9 only.
+
+abs
+~~~
+
+See a description :ref:`here<amdgpu_synid_abs>`.
+
+neg
+~~~
+
+See a description :ref:`here<amdgpu_synid_neg>`.
+
+.. _amdgpu_synid_sext:
+
+sext
+~~~~
+
+Sign-extends value of a (sub-dword) operand to fill all 32 bits.
+Has no effect for 32-bit operands.
+
+Valid for integer operands only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    sext(<operand>)                          Sign-extend operand value.
+    ======================================== ================================================
+
+VOP3 Modifiers
+--------------
+
+.. _amdgpu_synid_vop3_op_sel:
+
+vop3_op_sel
+~~~~~~~~~~~
+
+Selects the low [15:0] or high [31:16] operand bits for source and destination operands.
+By default, low bits are used for all operands.
+
+The number of values specified with the op_sel modifier must match the number of instruction
+operands (both source and destination). First value controls src0, second value controls src1
+and so on, except that the last value controls destination.
+The value 0 selects the low bits, while 1 selects the high bits.
+
+Note. op_sel modifier affects 16-bit operands only. For 32-bit operands the value specified
+by op_sel must be 0.
+
+GFX9 only.
+
+    ======================================== ============================================================
+    Syntax                                   Description
+    ======================================== ============================================================
+    op_sel:[{0..1},{0..1}]                   Select operand bits for instructions with 1 source operand.
+    op_sel:[{0..1},{0..1},{0..1}]            Select operand bits for instructions with 2 source operands.
+    op_sel:[{0..1},{0..1},{0..1},{0..1}]     Select operand bits for instructions with 3 source operands.
+    ======================================== ============================================================
+
+.. _amdgpu_synid_clamp:
+
+clamp
+~~~~~
+
+Clamp meaning depends on instruction.
+
+For *v_cmp* instructions, clamp modifier indicates that the compare signals
+if a floating point exception occurs. By default, signaling is disabled.
+Not supported by GFX7.
+
+For integer operations, clamp modifier indicates that the result must be clamped
+to the largest and smallest representable value. By default, there is no clamping.
+Integer clamping is not supported by GFX7.
+
+For floating point operations, clamp modifier indicates that the result must be clamped
+to the range [0.0, 1.0]. By default, there is no clamping.
+
+Note. Clamp modifier is applied after :ref:`output modifiers<amdgpu_synid_omod>` (if any).
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    clamp                                    Enables clamping (or signaling).
+    ======================================== ================================================
+
+.. _amdgpu_synid_omod:
+
+omod
+~~~~
+
+Specifies if an output modifier must be applied to the result.
+By default, no output modifiers are applied.
+
+Note. Output modifiers are applied before :ref:`clamping<amdgpu_synid_clamp>` (if any).
+
+Output modifiers are valid for f32 and f64 floating point results only.
+They must not be used with f16.
+
+Note. *v_cvt_f16_f32* is an exception. This instruction produces f16 result
+but accepts output modifiers.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    mul:2                                    Multiply the result by 2.
+    mul:4                                    Multiply the result by 4.
+    div:2                                    Multiply the result by 0.5.
+    ======================================== ================================================
+
+VOP3 Operand Modifiers
+----------------------
+
+Operand modifiers are not used separately. They are applied to source operands.
+
+.. _amdgpu_synid_abs:
+
+abs
+~~~
+
+Computes absolute value of its operand. Applied before :ref:`neg<amdgpu_synid_neg>` (if any).
+Valid for floating point operands only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    abs(<operand>)                           Get absolute value of operand.
+    \|<operand>|                             The same as above.
+    ======================================== ================================================
+
+.. _amdgpu_synid_neg:
+
+neg
+~~~
+
+Computes negative value of its operand. Applied after :ref:`abs<amdgpu_synid_abs>` (if any).
+Valid for floating point operands only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    neg(<operand>)                           Get negative value of operand.
+    -<operand>                               The same as above.
+    ======================================== ================================================
+
+VOP3P Modifiers
+---------------
+
+This section describes modifiers of regular VOP3P instructions.
+*v_mad_mix* modifiers are described :ref:`in a separate section<amdgpu_synid_mad_mix>`.
+
+GFX9 only.
+
+.. _amdgpu_synid_op_sel:
+
+op_sel
+~~~~~~
+
+Selects the low [15:0] or high [31:16] operand bits as input to the operation
+which results in the lower-half of the destination.
+By default, low bits are used for all operands.
+
+The number of values specified with the op_sel modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.
+The value 0 selects the low bits, while 1 selects the high bits.
+
+    ======================================== =============================================================
+    Syntax                                   Description
+    ======================================== =============================================================
+    op_sel:[{0..1}]                          Select operand bits for instructions with 1 source operand.
+    op_sel:[{0..1},{0..1}]                   Select operand bits for instructions with 2 source operands.
+    op_sel:[{0..1},{0..1},{0..1}]            Select operand bits for instructions with 3 source operands.
+    ======================================== =============================================================
+
+.. _amdgpu_synid_op_sel_hi:
+
+op_sel_hi
+~~~~~~~~~
+
+Selects the low [15:0] or high [31:16] operand bits as input to the operation
+which results in the upper-half of the destination.
+By default, high bits are used for all operands.
+
+The number of values specified with the op_sel_hi modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.
+The value 0 selects the low bits, while 1 selects the high bits.
+
+    ======================================== =============================================================
+    Syntax                                   Description
+    ======================================== =============================================================
+    op_sel_hi:[{0..1}]                       Select operand bits for instructions with 1 source operand.
+    op_sel_hi:[{0..1},{0..1}]                Select operand bits for instructions with 2 source operands.
+    op_sel_hi:[{0..1},{0..1},{0..1}]         Select operand bits for instructions with 3 source operands.
+    ======================================== =============================================================
+
+.. _amdgpu_synid_neg_lo:
+
+neg_lo
+~~~~~~
+
+Specifies whether to change sign of operand values selected by
+:ref:`op_sel<amdgpu_synid_op_sel>`. These values are then used
+as input to the operation which results in the upper-half of the destination.
+
+The number of values specified with this modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.
+
+The value 0 indicates that the corresponding operand value is used unmodified,
+the value 1 indicates that negative value of the operand must be used.
+
+By default, operand values are used unmodified.
+
+This modifier is valid for floating point operands only.
+
+    ======================================== ==================================================================
+    Syntax                                   Description
+    ======================================== ==================================================================
+    neg_lo:[{0..1}]                          Select affected operands for instructions with 1 source operand.
+    neg_lo:[{0..1},{0..1}]                   Select affected operands for instructions with 2 source operands.
+    neg_lo:[{0..1},{0..1},{0..1}]            Select affected operands for instructions with 3 source operands.
+    ======================================== ==================================================================
+
+.. _amdgpu_synid_neg_hi:
+
+neg_hi
+~~~~~~
+
+Specifies whether to change sign of operand values selected by
+:ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`. These values are then used
+as input to the operation which results in the upper-half of the destination.
+
+The number of values specified with this modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.
+
+The value 0 indicates that the corresponding operand value is used unmodified,
+the value 1 indicates that negative value of the operand must be used.
+
+By default, operand values are used unmodified.
+
+This modifier is valid for floating point operands only.
+
+    ======================================== ==================================================================
+    Syntax                                   Description
+    ======================================== ==================================================================
+    neg_hi:[{0..1}]                          Select affected operands for instructions with 1 source operand.
+    neg_hi:[{0..1},{0..1}]                   Select affected operands for instructions with 2 source operands.
+    neg_hi:[{0..1},{0..1},{0..1}]            Select affected operands for instructions with 3 source operands.
+    ======================================== ==================================================================
+
+clamp
+~~~~~
+
+See a description :ref:`here<amdgpu_synid_clamp>`.
+
+.. _amdgpu_synid_mad_mix:
+
+VOP3P V_MAD_MIX Modifiers
+-------------------------
+
+These instructions use VOP3P format but have different modifiers.
+
+GFX9 only.
+
+.. _amdgpu_synid_mad_op_sel:
+
+mad_op_sel
+~~~~~~~~~~
+
+Selects the size of source operands: either 32 bits or 16 bits.
+By default, 32 bits are used for all source operands.
+
+The value 0 indicates 32 bits, the value 1 indicates 16 bits.
+The location of 16 bits in the operand may be specified by
+:ref:`mad_op_sel_hi<amdgpu_synid_mad_op_sel_hi>`.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    op_sel:[{0..1},{0..1},{0..1}]            Select size of each source operand.
+    ======================================== ================================================
+
+.. _amdgpu_synid_mad_op_sel_hi:
+
+mad_op_sel_hi
+~~~~~~~~~~~~~
+
+This operand has meaning only for 16-bit source operands as indicated by
+:ref:`mad_op_sel<amdgpu_synid_mad_op_sel>`.
+It specifies to select either the low [15:0] or high [31:16] operand bits
+as input to the operation.
+
+The value 0 indicates the low bits, the value 1 indicates the high 16 bits.
+By default, low bits are used for all operands.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    op_sel_hi:[{0..1},{0..1},{0..1}]         Select location of each 16-bit source operand.
+    ======================================== ================================================
+
+abs
+~~~
+
+See a description :ref:`here<amdgpu_synid_abs>`.
+
+neg
+~~~
+
+See a description :ref:`here<amdgpu_synid_neg>`.
+
+clamp
+~~~~~
+
+See a description :ref:`here<amdgpu_synid_clamp>`.

llvm/trunk/docs/AMDGPUUsage.rst

.. TODO
    Specify what affect this has.
 
 Assembler
 ---------
 
 AMDGPU backend has LLVM-MC based assembler which is currently in development.
 It supports AMDGCN GFX6-GFX9.
 
-This section describes general syntax for instructions and operands. For more
-information about instructions, their semantics and supported combinations of
-operands, refer to one of instruction set architecture manuals
-[AMD-GCN-GFX6]_, [AMD-GCN-GFX7]_, [AMD-GCN-GFX8]_ and [AMD-GCN-GFX9]_.
+This section describes general syntax for instructions and operands.
+
+Instructions
+~~~~~~~~~~~~
+
+.. toctree::
+   :hidden:
+
+   AMDGPUAsmGFX7
+   AMDGPUAsmGFX8
+   AMDGPUAsmGFX9
+   AMDGPUOperandSyntax
+
+An instruction has the following syntax:
+
+    *<opcode> <operand0>, <operand1>,... <modifier0> <modifier1>...*
+
+Note that operands are normally comma-separated while modifiers are space-separated.
+
+The order of operands and modifiers is fixed. Most modifiers are optional and may be omitted.
 
-An instruction has the following syntax (register operands are normally
-comma-separated while extra operands are space-separated):
+See detailed instruction syntax description for :doc:`GFX7<AMDGPUAsmGFX7>`,
+:doc:`GFX8<AMDGPUAsmGFX8>` and :doc:`GFX9<AMDGPUAsmGFX9>`.
 
-*<opcode> <register_operand0>, ... <extra_operand0> ...*
+Note that features under development are not included in this description.
+
+For more information about instructions, their semantics and supported combinations of
+operands, refer to one of instruction set architecture manuals
+[AMD-GCN-GFX6]_, [AMD-GCN-GFX7]_, [AMD-GCN-GFX8]_ and [AMD-GCN-GFX9]_.
 
 Operands
 ~~~~~~~~
 
 The following syntax for register operands is supported:
 
 * SGPR registers: s0, ... or s[0], ...
 * VGPR registers: v0, ... or v[0], ...
 * TTMP registers: ttmp0, ... or ttmp[0], ...
 * Special registers: exec (exec_lo, exec_hi), vcc (vcc_lo, vcc_hi), flat_scratch (flat_scratch_lo, flat_scratch_hi)
 * Special trap registers: tba (tba_lo, tba_hi), tma (tma_lo, tma_hi)
 * Register pairs, quads, etc: s[2:3], v[10:11], ttmp[5:6], s[4:7], v[12:15], ttmp[4:7], s[8:15], ...
 * Register lists: [s0, s1], [ttmp0, ttmp1, ttmp2, ttmp3]
 * Register index expressions: v[2*2], s[1-1:2-1]
 * 'off' indicates that an operand is not enabled
 
-The following extra operands are supported:
-
-* offset, offset0, offset1
-* idxen, offen bits
-* glc, slc, tfe bits
-* waitcnt: integer or combination of counter values
-* VOP3 modifiers:
-
-  - abs (\| \|), neg (\-)
+Modifiers
+~~~~~~~~~
 
-* DPP modifiers:
-
-  - row_shl, row_shr, row_ror, row_rol
-  - row_mirror, row_half_mirror, row_bcast
-  - wave_shl, wave_shr, wave_ror, wave_rol, quad_perm
-  - row_mask, bank_mask, bound_ctrl
-
-* SDWA modifiers:
-
-  - dst_sel, src0_sel, src1_sel (BYTE_N, WORD_M, DWORD)
-  - dst_unused (UNUSED_PAD, UNUSED_SEXT, UNUSED_PRESERVE)
-  - abs, neg, sext
+Detailed description of modifiers may be found :doc:`here<AMDGPUOperandSyntax>`.
 
 Instruction Examples
 ~~~~~~~~~~~~~~~~~~~~
 
 DS
-~~
+++
 
 .. code-block:: nasm
 
   ds_add_u32 v2, v4 offset:16
   ds_write_src2_b64 v2 offset0:4 offset1:8
   ds_cmpst_f32 v2, v4, v6
   ds_min_rtn_f64 v[8:9], v2, v[4:5]