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[AArch64][SVE] Asm: Add support for RDVL/ADDVL/ADDPL instructions
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Authored by sdesmalen on Jan 10 2018, 4:39 AM.

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sdesmalen created this revision.Jan 10 2018, 4:39 AM
SjoerdMeijer added inline comments.
lib/Target/AArch64/SVEInstrFormats.td
100

I think it is clearer to split this up in 2 operands: op and opc2, which then matches with the "encoding group".

test/MC/AArch64/SVE/rdvl-diagnostics.s
4

Perhaps a nice to have, test that it doesn't accept a register operand as the 2nd operand?

sdesmalen updated this revision to Diff 130601.Jan 19 2018, 6:26 AM
  • Split up single opcode into 'op' and 'opc2'.
  • Added new negative tests.
sdesmalen marked 2 inline comments as done.Jan 19 2018, 6:26 AM
This revision is now accepted and ready to land.Jan 19 2018, 6:53 AM
This revision was automatically updated to reflect the committed changes.