[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models

[sdesmalen]

Summary

Patch [4/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions.

We add SVE as unsupported feature for CPUs that don't have SVE to prevent errors from scheduler models saying it lacks information for these instructions.

[javed.absar]

lib/Target/AArch64/AArch64SchedCyclone.td

21 ↗

(On Diff #119571)

nitpick. The blank line here and in other .td not needed i think.

[fhahn]

I think it would be good to explain why this change is necessary in the review description. Why do we need to add UnsupportedFeatures to the existing scheduling models for SVE?

[sdesmalen]

@fhahn The reason for adding it as unsupported feature (besides the fact that these CPUs don't have SVE), is that we otherwise would get errors like:

'ThunderXT8XModel' lacks information for <name of SVE instruction here>.

Thanks for the suggestion, I'll add it to the description of the patch.

[rengolin]

Simple and straightforward. Looks good, but will approve once all patches are good.

[rengolin]

Adding a few AArch64 folks, to make sure we get enough eyes on this, thus avoiding silly problems in the future, if we miss anything.

[fhahn]

The reason we need this are over-eager regular expression in scheduling models, e.g. some models match TRN1 instructions for all types and the scheduler then fails to compile, because scheduling info is missing for SVE instructions. I think ideally those regexs should be more specific, but using UnsupportedFeatures seems like a more practical way to handle this problem and is also used by SystemZ, PPC and MIPS targets.

[rengolin]

Yes, this change makes sense to me.

llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td

def CortexA53Model : SchedMachineModel {
   let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
   let LoadLatency = 3;       // Optimistic load latency assuming bypass.
                              // This is overriden by OperandCycles if the
                              // Itineraries are queried instead.
   let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
                              // Specification - Instruction Timings"
                              // v 1.0 Spreadsheet
   let CompleteModel = 1;
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available.
 
 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
 // Cortex-A53 is in-order.

llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td

def CortexA57Model : SchedMachineModel {
   let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
   let LoadLatency       =   4; // Optimistic load latency
   let MispredictPenalty =  14; // Fetch + Decode/Rename/Dispatch + Branch
 
   // Enable partial & runtime unrolling. The magic number is chosen based on
   // experiments and benchmarking data.
   let LoopMicroOpBufferSize = 16;
   let CompleteModel = 1;
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available on Cortex-A57.
 // Cortex A-57 has 8 pipelines that each has its own 8-entry queue where
 // micro-ops wait for their operands and then issue out-of-order.
 
 def A57UnitB : ProcResource<1>;  // Type B micro-ops

llvm/trunk/lib/Target/AArch64/AArch64SchedCyclone.td

 //===----------------------------------------------------------------------===//
 
 def CycloneModel : SchedMachineModel {
   let IssueWidth = 6; // 6 micro-ops are dispatched per cycle.
   let MicroOpBufferSize = 192; // Based on the reorder buffer.
   let LoadLatency = 4; // Optimistic load latency.
   let MispredictPenalty = 16; // 14-19 cycles are typical.
   let CompleteModel = 1;
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available on Cyclone.
 
 // 4 integer pipes
 def CyUnitI : ProcResource<4> {
   let BufferSize = 48;

llvm/trunk/lib/Target/AArch64/AArch64SchedFalkor.td

 
 def FalkorModel : SchedMachineModel {
   let IssueWidth = 8;          // 8 uops are dispatched per cycle.
   let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer.
   let LoopMicroOpBufferSize = 16;
   let LoadLatency = 3;         // Optimistic load latency.
   let MispredictPenalty = 11;  // Minimum branch misprediction penalty.
   let CompleteModel = 1;
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available on Falkor.
 
 let SchedModel = FalkorModel in {
 
   def FalkorUnitB    : ProcResource<1>; // Branch

llvm/trunk/lib/Target/AArch64/AArch64SchedKryo.td

def KryoModel : SchedMachineModel {
   let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer
   let LoadLatency       =   4; // Optimistic load latency
   let MispredictPenalty =  14; // Fetch + Decode/Rename/Dispatch + Branch
 
   // Enable partial & runtime unrolling. The magic number is chosen based on
   // experiments and benchmarking data.
   let LoopMicroOpBufferSize = 16;
   let CompleteModel = 1;
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available on Kryo.
 
 let SchedModel = KryoModel in {
   def KryoUnitXA : ProcResource<1>;                   // Type X(A) micro-ops
   def KryoUnitXB : ProcResource<1>;                   // Type X(B) micro-ops

llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td

 
 def ExynosM1Model : SchedMachineModel {
   let IssueWidth            =  4; // Up to 4 uops per cycle.
   let MicroOpBufferSize     = 96; // ROB size.
   let LoopMicroOpBufferSize = 24; // Based on the instruction queue size.
   let LoadLatency           =  4; // Optimistic load cases.
   let MispredictPenalty     = 14; // Minimum branch misprediction penalty.
   let CompleteModel         =  1; // Use the default model otherwise.
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available on the Exynos-M1,
 // which has 9 pipelines, each with its own queue with out-of-order dispatch.
 
 def M1UnitA  : ProcResource<2>; // Simple integer
 def M1UnitC  : ProcResource<1>; // Simple and complex integer

llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX.td

 // Cavium ThunderX T8X scheduling machine model.
 def ThunderXT8XModel : SchedMachineModel {
   let IssueWidth = 2;         // 2 micro-ops dispatched per cycle.
   let MicroOpBufferSize = 0;  // ThunderX T88/T81/T83 are in-order.
   let LoadLatency = 3;        // Optimistic load latency.
   let MispredictPenalty = 8;  // Branch mispredict penalty.
   let PostRAScheduler = 1;    // Use PostRA scheduler.
   let CompleteModel = 1;
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 // Modeling each pipeline with BufferSize == 0 since T8X is in-order.
 def THXT8XUnitALU    : ProcResource<2> { let BufferSize = 0; } // Int ALU
 def THXT8XUnitMAC    : ProcResource<1> { let BufferSize = 0; } // Int MAC
 def THXT8XUnitDiv    : ProcResource<1> { let BufferSize = 0; } // Int Division
 def THXT8XUnitLdSt   : ProcResource<1> { let BufferSize = 0; } // Load/Store
 def THXT8XUnitBr     : ProcResource<1> { let BufferSize = 0; } // Branch

llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td

def ThunderX2T99Model : SchedMachineModel {
   let IssueWidth            =   4; // 4 micro-ops dispatched at a time.
   let MicroOpBufferSize     = 180; // 180 entries in micro-op re-order buffer.
   let LoadLatency           =   4; // Optimistic load latency.
   let MispredictPenalty     =  12; // Extra cycles for mispredicted branch.
   // Determined via a mix of micro-arch details and experimentation.
   let LoopMicroOpBufferSize =  32;
   let PostRAScheduler       =   1; // Using PostRA sched.
   let CompleteModel         =   1;
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 // Define the issue ports.
 
 // Port 0: ALU, FP/SIMD.
 def THX2T99P0 : ProcResource<1>;
 
 // Port 1: ALU, FP/SIMD, integer mul/div.