[AMDGPU][MC][GFX9] Added 16-bit renamed and "_legacy" VALU opcodes

[dp]

Summary

See Bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629

Known issues:

• V_INTERP_P2_F16 and V_INTERP_P2_LEGACY_F16 should be handled in a similar way. This depends on D35902 and will be added separately.

[arsenm]

I'm confused about what exactly is meant by a legacy instruction. This isn't the first set of instructions renamed to be _legacy, so I think the bit name needs to be more specific.

What exactly is different about mad_legacy for example? Is there a new mad opcode with different behavior? Can we leave it as an MC emission quirk rather than changing codegen to have to be aware of the random instruction rename?

lib/Target/AMDGPU/SIInstrInfo.cpp

701–704 ↗

(On Diff #109756)

Move to header

lib/Target/AMDGPU/VOP3Instructions.td

328–329 ↗

(On Diff #109756)

The naming convention is the base instruction name is all caps, but the suffix is lowercase

[SamWot]

lib/Target/AMDGPU/SIInstrInfo.cpp

702 ↗

(On Diff #109756)

You should use subtarget feature rather then check generation directly

lib/Target/AMDGPU/SIInstrInfo.h

186 ↗

(On Diff #109756)

It is probably better if you create same functions for other legacy instructions (getFmaF16(), getDivFixupF16()...) although they wouldn't be used.

[dp]

Updated and a bit simplified as suggested by Matt and Sam.

[SamWot]

LGTM

llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp

int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {
   }
 }
 
 // This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
 enum SIEncodingFamily {
   SI = 0,
   VI = 1,
   SDWA = 2,
-  SDWA9 = 3
+  SDWA9 = 3,
+  GFX9 = 4
 };
 
 // Wrapper for Tablegen'd function.  enum Subtarget is not defined in any
 // header files, so we need to wrap it in a function that takes unsigned
 // instead.
 namespace llvm {
 namespace AMDGPU {
 static int getMCOpcode(uint16_t Opcode, unsigned Gen) {

 }
 
 int AMDGPUInstrInfo::pseudoToMCOpcode(int Opcode) const {
   SIEncodingFamily Gen = subtargetEncodingFamily(ST);
   if (get(Opcode).TSFlags & SIInstrFlags::SDWA)
     Gen = ST.getGeneration() == AMDGPUSubtarget::GFX9 ? SIEncodingFamily::SDWA9
                                                       : SIEncodingFamily::SDWA;
 
+  if ((get(Opcode).TSFlags & SIInstrFlags::F16_ZFILL) != 0 &&
+      ST.getGeneration() >= AMDGPUSubtarget::GFX9)
+    Gen = SIEncodingFamily::GFX9;
+
   int MCOp = AMDGPU::getMCOpcode(Opcode, Gen);
 
   // -1 means that Opcode is already a native instruction.
   if (MCOp == -1)
     return Opcode;
 
   // (uint16_t)-1 means that Opcode is a pseudo instruction that has
   // no encoding in the given subtarget generation.
   if (MCOp == (uint16_t)-1)
     return -1;
 
   return MCOp;
 }

llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

do {
     if (Res) break;
 
     if (Bytes.size() < 4) break;
     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
     Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address);
     if (Res) break;
 
     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
+    if (Res) break;
+
+    Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
   } while (false);
 
   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si ||
               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi)) {
     // Insert dummy unused src2_modifiers.
     insertNamedMCOperand(MI, MCOperand::createImm(0),
                          AMDGPU::OpName::src2_modifiers);

llvm/trunk/lib/Target/AMDGPU/SIDefines.h

// TODO: Should this be spilt into VOP3 a and b?
   DisableWQM = UINT64_C(1) << 36,
   Gather4 = UINT64_C(1) << 37,
   SOPK_ZEXT = UINT64_C(1) << 38,
   SCALAR_STORE = UINT64_C(1) << 39,
   FIXED_SIZE = UINT64_C(1) << 40,
   VOPAsmPrefer32Bit = UINT64_C(1) << 41,
   HasFPClamp = UINT64_C(1) << 42,
   VOP3_OPSEL = UINT64_C(1) << 43,
-  maybeAtomic = UINT64_C(1) << 44
+  maybeAtomic = UINT64_C(1) << 44,
+  F16_ZFILL = UINT64_C(1) << 45
 };
 
 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
 // The result is true if any of these tests are true.
 enum ClassFlags {
   S_NAN = 1 << 0,        // Signaling NaN
   Q_NAN = 1 << 1,        // Quiet NaN
   N_INFINITY = 1 << 2,   // Negative infinity

llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td

class InstSI <dag outs, dag ins, string asm = "",
 
   // This bit indicates that this is a VOP3 opcode which supports op_sel
   // modifier (gfx9 only).
   field bit VOP3_OPSEL = 0;
 
   // Is it possible for this instruction to be atomic?
   field bit maybeAtomic = 0;
 
+  // This bit indicates that this is a 16-bit instruction which zero-fills
+  // unused bits in dst. Note that new GFX9 opcodes preserve unused bits.
+  field bit F16_ZFILL = 0;
+
   // These need to be kept in sync with the enum in SIInstrFlags.
   let TSFlags{0} = SALU;
   let TSFlags{1} = VALU;
 
   let TSFlags{2} = SOP1;
   let TSFlags{3} = SOP2;
   let TSFlags{4} = SOPC;
   let TSFlags{5} = SOPK;
class InstSI <dag outs, dag ins, string asm = "",
   let TSFlags{38} = SOPKZext;
   let TSFlags{39} = ScalarStore;
   let TSFlags{40} = FixedSize;
   let TSFlags{41} = VOPAsmPrefer32Bit;
   let TSFlags{42} = FPClamp;
   let TSFlags{43} = VOP3_OPSEL;
 
   let TSFlags{44} = maybeAtomic;
+  let TSFlags{45} = F16_ZFILL;
 
   let SchedRW = [Write32Bit];
 
   field bits<1> DisableSIDecoder = 0;
   field bits<1> DisableVIDecoder = 0;
   field bits<1> DisableDecoder = 0;
 
   let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 def isCI : Predicate<"Subtarget->getGeneration() "
                       ">= SISubtarget::SEA_ISLANDS">;
 def isCIOnly : Predicate<"Subtarget->getGeneration() =="
                          "SISubtarget::SEA_ISLANDS">,
   AssemblerPredicate <"FeatureSeaIslands">;
+def isVIOnly : Predicate<"Subtarget->getGeneration() =="
+                         "SISubtarget::VOLCANIC_ISLANDS">,
+  AssemblerPredicate <"FeatureVolcanicIslands">;
 
 def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
 
 // Execpt for the NONE field, this must be kept in sync with the
 // SIEncodingFamily enum in AMDGPUInstrInfo.cpp
 def SIEncodingFamily {
   int NONE = -1;
   int SI = 0;
   int VI = 1;
   int SDWA = 2;
   int SDWA9 = 3;
+  int GFX9 = 4;
 }
 
 //===----------------------------------------------------------------------===//
 // SI DAG Nodes
 //===----------------------------------------------------------------------===//
 
 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
   SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,

 def getMCOpcodeGen : InstrMapping {
   let FilterClass = "SIMCInstr";
   let RowFields = ["PseudoInstr"];
   let ColFields = ["Subtarget"];
   let KeyCol = [!cast<string>(SIEncodingFamily.NONE)];
   let ValueCols = [[!cast<string>(SIEncodingFamily.SI)],
                    [!cast<string>(SIEncodingFamily.VI)],
                    [!cast<string>(SIEncodingFamily.SDWA)],
-                   [!cast<string>(SIEncodingFamily.SDWA9)]];
+                   [!cast<string>(SIEncodingFamily.SDWA9)],
+                   [!cast<string>(SIEncodingFamily.GFX9)]];
 }
 
 // Get equivalent SOPK instruction.
 def getSOPKOp : InstrMapping {
   let FilterClass = "SOPKInstTable";
   let RowFields = ["BaseCmpOp"];
   let ColFields = ["IsSOPK"];
   let KeyCol = ["0"];

llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td

 def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
 } // End isCommutable = 1
 
 } // End SubtargetPredicate = isCIVI
 
 
 let SubtargetPredicate = Has16BitInsts in {
 
-def V_DIV_FIXUP_F16   : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>;
+let F16_ZFILL = 1 in {
+def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>;
+}
+let SubtargetPredicate = isGFX9 in {
+def V_DIV_FIXUP_F16_gfx9   : VOP3Inst <"v_div_fixup_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16>>;
+}
 
 let isCommutable = 1 in {
 
-def V_FMA_F16         : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
+let F16_ZFILL = 1 in {
+def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
+def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
+def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
+def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
+}
+
+let SubtargetPredicate = isGFX9 in {
+def V_MAD_F16_gfx9   : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16>>;
+def V_MAD_U16_gfx9   : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16>>;
+def V_MAD_I16_gfx9   : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16>>;
+def V_FMA_F16_gfx9   : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16>>;
+} // End SubtargetPredicate = isGFX9
 
 def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>>;
 def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;
 def V_INTERP_P2_F16   : VOP3Interp <"v_interp_p2_f16",   VOP3_INTERP16<[f16, f32, i32, f32]>>;
 
-def V_MAD_F16         : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
-
-def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
-def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
-
 }  // End isCommutable = 1
 } // End SubtargetPredicate = Has16BitInsts
 
 let SubtargetPredicate = isVI in {
 def V_INTERP_P1_F32_e64  : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
 def V_INTERP_P2_F32_e64  : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
 def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
 

 
 multiclass VOP3Interp_Real_vi<bits<10> op> {
   def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
             VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
 }
 
 } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
 
+let AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI" in {
+
+multiclass VOP3_F16_Real_vi<bits<10> op> {
+  def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
+            VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
+}
+
+} // End AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI"
+
+let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in {
+
+multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
+  def _vi : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
+            VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
+              VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
+              let AsmString = AsmName # ps.AsmOperands;
+            }
+}
+
+} // End AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9"
+
 defm V_MAD_U64_U32      : VOP3be_Real_vi <0x1E8>;
 defm V_MAD_I64_I32      : VOP3be_Real_vi <0x1E9>;
 
 defm V_MAD_LEGACY_F32   : VOP3_Real_vi <0x1c0>;
 defm V_MAD_F32          : VOP3_Real_vi <0x1c1>;
 defm V_MAD_I32_I24      : VOP3_Real_vi <0x1c2>;
 defm V_MAD_U32_U24      : VOP3_Real_vi <0x1c3>;
 defm V_CUBEID_F32       : VOP3_Real_vi <0x1c4>;

 defm V_DIV_SCALE_F64    : VOP3be_Real_vi <0x1e1>;
 defm V_DIV_FMAS_F32     : VOP3_Real_vi <0x1e2>;
 defm V_DIV_FMAS_F64     : VOP3_Real_vi <0x1e3>;
 defm V_MSAD_U8          : VOP3_Real_vi <0x1e4>;
 defm V_QSAD_PK_U16_U8   : VOP3_Real_vi <0x1e5>;
 defm V_MQSAD_PK_U16_U8  : VOP3_Real_vi <0x1e6>;
 defm V_MQSAD_U32_U8     : VOP3_Real_vi <0x1e7>;
 
-defm V_MAD_F16          : VOP3_Real_vi <0x1ea>;
-defm V_MAD_U16          : VOP3_Real_vi <0x1eb>;
-defm V_MAD_I16          : VOP3_Real_vi <0x1ec>;
-
 defm V_PERM_B32         : VOP3_Real_vi <0x1ed>;
 
-defm V_FMA_F16          : VOP3_Real_vi <0x1ee>;
-defm V_DIV_FIXUP_F16    : VOP3_Real_vi <0x1ef>;
+defm V_MAD_F16          : VOP3_F16_Real_vi <0x1ea>;
+defm V_MAD_U16          : VOP3_F16_Real_vi <0x1eb>;
+defm V_MAD_I16          : VOP3_F16_Real_vi <0x1ec>;
+defm V_FMA_F16          : VOP3_F16_Real_vi <0x1ee>;
+defm V_DIV_FIXUP_F16    : VOP3_F16_Real_vi <0x1ef>;
+
+defm V_MAD_LEGACY_F16       : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16",       "v_mad_legacy_f16">;
+defm V_MAD_LEGACY_U16       : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16",       "v_mad_legacy_u16">;
+defm V_MAD_LEGACY_I16       : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16",       "v_mad_legacy_i16">;
+defm V_FMA_LEGACY_F16       : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16",       "v_fma_legacy_f16">;
+defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">;
+
+defm V_MAD_F16_gfx9         : VOP3_F16_Real_gfx9 <0x203, "V_MAD_F16_gfx9",       "v_mad_f16">;
+defm V_MAD_U16_gfx9         : VOP3_F16_Real_gfx9 <0x204, "V_MAD_U16_gfx9",       "v_mad_u16">;
+defm V_MAD_I16_gfx9         : VOP3_F16_Real_gfx9 <0x205, "V_MAD_I16_gfx9",       "v_mad_i16">;
+defm V_FMA_F16_gfx9         : VOP3_F16_Real_gfx9 <0x206, "V_FMA_F16_gfx9",       "v_fma_f16">;
+defm V_DIV_FIXUP_F16_gfx9   : VOP3_F16_Real_gfx9 <0x207, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">;
 
 defm V_INTERP_P1_F32_e64  : VOP3Interp_Real_vi <0x270>;
 defm V_INTERP_P2_F32_e64  : VOP3Interp_Real_vi <0x271>;
 defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>;
 
 defm V_INTERP_P1LL_F16  : VOP3Interp_Real_vi <0x274>;
 defm V_INTERP_P1LV_F16  : VOP3Interp_Real_vi <0x275>;
 defm V_INTERP_P2_F16    : VOP3Interp_Real_vi <0x276>;

llvm/trunk/test/MC/AMDGPU/vop3-gfx9.s

 v_sub_i16 v5, v1, v2
 // GFX9: v_sub_i16 v5, v1, v2 ; encoding: [0x05,0x00,0x9f,0xd2,0x01,0x05,0x02,0x00]
 
 v_sub_i16 v5, v1, v2 op_sel:[1,1,1]
 // GFX9: v_sub_i16 v5, v1, v2 op_sel:[1,1,1] ; encoding: [0x05,0x58,0x9f,0xd2,0x01,0x05,0x02,0x00]
 
 v_sub_i16 v5, v1, v2 clamp
 // GFX9: v_sub_i16 v5, v1, v2 clamp ; encoding: [0x05,0x80,0x9f,0xd2,0x01,0x05,0x02,0x00]
+
+v_fma_f16_e64 v5, v1, v2, v3
+// GFX9: v_fma_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, -v2, v3
+// GFX9: v_fma_f16 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x44]
+
+v_fma_f16 v5, v1, v2, |v3|
+// GFX9: v_fma_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, v3 clamp
+// GFX9: v_fma_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_legacy_f16_e64 v5, v1, v2, v3
+// GFX9: v_fma_legacy_f16 v5, v1, v2, v3 ; encoding:  [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_legacy_f16 v5, -v1, v2, v3
+// GFX9: v_fma_legacy_f16 v5, -v1, v2, v3 ; encoding:  [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x24]
+
+v_fma_legacy_f16 v5, v1, |v2|, v3
+// GFX9: v_fma_legacy_f16 v5, v1, |v2|, v3 ; encoding:  [0x05,0x02,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_legacy_f16 v5, v1, v2, v3 clamp
+// GFX9: v_fma_legacy_f16 v5, v1, v2, v3 clamp ; encoding:  [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16_e64 v5, 0.5, v2, v3
+// GFX9: v_div_fixup_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, 0.5, v3
+// GFX9: v_div_fixup_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, v2, 0.5
+// GFX9: v_div_fixup_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_f16 v5, -v1, v2, v3
+// GFX9: v_div_fixup_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_f16 v5, |v1|, v2, v3
+// GFX9: v_div_fixup_f16 v5, |v1|, v2, v3 ; encoding: [0x05,0x01,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 clamp
+// GFX9: v_div_fixup_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_legacy_f16_e64 v5, 0.5, v2, v3
+// GFX9: v_div_fixup_legacy_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, 0.5, v3
+// GFX9: v_div_fixup_legacy_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, v2, 0.5
+// GFX9: v_div_fixup_legacy_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_legacy_f16 v5, -v1, v2, v3
+// GFX9: v_div_fixup_legacy_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_legacy_f16 v5, v1, |v2|, v3
+// GFX9: v_div_fixup_legacy_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, v2, v3 clamp
+// GFX9: v_div_fixup_legacy_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f16_e64 v5, 0.5, v2, v3
+// GFX9: v_mad_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0x03,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_mad_f16 v5, v1, 0.5, v3
+// GFX9: v_mad_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_mad_f16 v5, v1, v2, 0.5
+// GFX9: v_mad_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0xc2,0x03]
+
+v_mad_f16 v5, v1, v2, -v3
+// GFX9: v_mad_f16 v5, v1, v2, -v3 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x84]
+
+v_mad_f16 v5, v1, v2, |v3|
+// GFX9: v_mad_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, v2, v3 clamp
+// GFX9: v_mad_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i16_e64 v5, 0, v2, v3
+// GFX9: v_mad_i16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mad_i16 v5, v1, -1, v3
+// GFX9: v_mad_i16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mad_i16 v5, v1, v2, -4.0
+// GFX9: v_mad_i16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x05,0xde,0x03]
+
+v_mad_legacy_f16_e64 v5, 0.5, v2, v3
+// GFX9: v_mad_legacy_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, v1, 0.5, v3
+// GFX9: v_mad_legacy_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_legacy_f16 v5, v1, v2, 0.5
+// GFX9: v_mad_legacy_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_legacy_f16 v5, v1, -v2, v3
+// GFX9: v_mad_legacy_f16 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x44]
+
+v_mad_legacy_f16 v5, v1, |v2|, v3
+// GFX9: v_mad_legacy_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f16 v5, v1, v2, v3 clamp
+// GFX9: v_mad_legacy_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_i16_e64 v5, 0, v2, v3
+// GFX9: v_mad_legacy_i16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, v1, -1, v3
+// GFX9: v_mad_legacy_i16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_legacy_i16 v5, v1, v2, -4.0
+// GFX9: v_mad_legacy_i16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_legacy_u16_e64 v5, 0, v2, v3
+// GFX9: v_mad_legacy_u16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, v1, -1, v3
+// GFX9: v_mad_legacy_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_legacy_u16 v5, v1, v2, -4.0
+// GFX9: v_mad_legacy_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_u16_e64 v5, 0, v2, v3
+// GFX9: v_mad_u16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mad_u16 v5, v1, -1, v3
+// GFX9: v_mad_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mad_u16 v5, v1, v2, -4.0
+// GFX9: v_mad_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x05,0xde,0x03]

llvm/trunk/test/MC/AMDGPU/vop3.s

 v_mul_f64 v[0:1], |0|, |0|
 // SICI: v_mul_f64 v[0:1], |0|, |0|      ; encoding: [0x00,0x03,0xca,0xd2,0x80,0x00,0x01,0x00]
 // VI:   v_mul_f64 v[0:1], |0|, |0|      ; encoding: [0x00,0x03,0x81,0xd2,0x80,0x00,0x01,0x00]
 
 v_cubeid_f32 v0, |-1|, |-1.0|, |1.0|
 // SICI: v_cubeid_f32 v0, |-1|, |-1.0|, |1.0| ; encoding: [0x00,0x07,0x88,0xd2,0xc1,0xe6,0xc9,0x03]
 // VI:   v_cubeid_f32 v0, |-1|, |-1.0|, |1.0| ; encoding: [0x00,0x07,0xc4,0xd1,0xc1,0xe6,0xc9,0x03]
 
+///===---------------------------------------------------------------------===//
+// VOP3 Legacy
+///===---------------------------------------------------------------------===//
+
+v_fma_f16_e64 v5, v1, v2, v3
+// VI: v_fma_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, 0.5
+// VI: v_fma_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0xc2,0x03]
+
+v_fma_f16 v5, -v1, -v2, -v3
+// VI: v_fma_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_fma_f16 v5, |v1|, |v2|, |v3|
+// VI: v_fma_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, v3 clamp
+// VI: v_fma_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16_e64 v5, v1, v2, v3
+// VI: v_div_fixup_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, 0.5, v2, v3
+// VI: v_div_fixup_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, 0.5, v3
+// VI: v_div_fixup_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, v2, 0.5
+// VI: v_div_fixup_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_f16 v5, v1, v2, -4.0
+// VI: v_div_fixup_f16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_fixup_f16 v5, -v1, v2, v3
+// VI: v_div_fixup_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_f16 v5, v1, |v2|, v3
+// VI: v_div_fixup_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 clamp
+// VI: v_div_fixup_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f16_e64 v5, v1, v2, v3
+// VI: v_mad_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, 0.5, v2, v3
+// VI: v_mad_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_f16 v5, v1, 0.5, v3
+// VI: v_mad_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_f16 v5, v1, v2, 0.5
+// VI: v_mad_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_f16 v5, v1, -v2, v3
+// VI: v_mad_f16 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x44]
+
+v_mad_f16 v5, v1, v2, |v3|
+// VI: v_mad_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, v2, v3 clamp
+// VI: v_mad_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i16_e64 v5, -1, v2, v3
+// VI: v_mad_i16 v5, -1, v2, v3 ; encoding: [0x05,0x00,0xec,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_i16 v5, v1, -4.0, v3
+// VI: v_mad_i16 v5, v1, -4.0, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_i16 v5, v1, v2, 0
+// VI: v_mad_i16 v5, v1, v2, 0 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_u16_e64 v5, -1, v2, v3
+// VI: v_mad_u16 v5, -1, v2, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_u16 v5, v1, 0, v3
+// VI: v_mad_u16 v5, v1, 0, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_u16 v5, v1, v2, -4.0
+// VI: v_mad_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
+
 //
 // v_interp*
 //
 
 v_interp_mov_f32_e64 v5, p10, attr0.x
 // NOSICI: error: instruction not supported on this GPU
 // VI: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
 

llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt

+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx901 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
+
+# GFX9: v_fma_f16 v5, v1, v2, v3    ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04
+
+# GFX9: v_fma_f16 v5, -v1, v2, v3    ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x24]
+0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x24
+
+# GFX9: v_fma_f16 v5, v1, |v2|, v3    ; encoding: [0x05,0x02,0x06,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x02,0x06,0xd2,0x01,0x05,0x0e,0x04
+
+# GFX9: v_fma_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04
+
+# CHECK: v_fma_legacy_f16 v5, v1, v2, v3    ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_fma_legacy_f16 v5, v1, v2, -v3    ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x84]
+0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x84
+
+# CHECK: v_fma_legacy_f16 v5, |v1|, v2, v3    ; encoding: [0x05,0x01,0xee,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x01,0xee,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_fma_legacy_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_div_fixup_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04
+
+# CHECK: v_div_fixup_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04]
+0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04
+
+# CHECK: v_div_fixup_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03]
+0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03
+
+# CHECK: v_div_fixup_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0xe4
+
+# CHECK: v_div_fixup_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0x07,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x07,0x07,0xd2,0x01,0x05,0x0e,0x04
+
+# CHECK: v_div_fixup_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04
+
+# CHECK: v_div_fixup_legacy_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04
+
+# CHECK: v_div_fixup_legacy_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
+0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04
+
+# CHECK: v_div_fixup_legacy_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
+0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03
+
+# CHECK: v_div_fixup_legacy_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4
+
+# CHECK: v_div_fixup_legacy_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_div_fixup_legacy_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0x03,0xd2,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0x03,0xd2,0xf0,0x04,0x0e,0x04
+
+# CHECK: v_mad_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0x03,0xd2,0x01,0xe1,0x0d,0x04]
+0x05,0x00,0x03,0xd2,0x01,0xe1,0x0d,0x04
+
+# CHECK: v_mad_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0xc2,0x03]
+0x05,0x00,0x03,0xd2,0x01,0x05,0xc2,0x03
+
+# CHECK: v_mad_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0xe4
+
+# CHECK: v_mad_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0x03,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x07,0x03,0xd2,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_i16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04]
+0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04
+
+# CHECK: v_mad_i16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04]
+0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04
+
+# CHECK: v_mad_i16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x05,0xde,0x03]
+0x05,0x00,0x05,0xd2,0x01,0x05,0xde,0x03
+
+# CHECK: v_mad_legacy_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04
+
+# CHECK: v_mad_legacy_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
+0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04
+
+# CHECK: v_mad_legacy_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
+0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03
+
+# CHECK: v_mad_legacy_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4
+
+# CHECK: v_mad_legacy_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_legacy_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_legacy_i16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04]
+0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04
+
+# CHECK: v_mad_legacy_i16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04]
+0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04
+
+# CHECK: v_mad_legacy_i16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xde,0x03]
+0x05,0x00,0xec,0xd1,0x01,0x05,0xde,0x03
+
+# CHECK: v_mad_legacy_u16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
+0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04
+
+# CHECK: v_mad_legacy_u16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
+0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04
+
+# CHECK: v_mad_legacy_u16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
+0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03
+
+# CHECK: v_mad_u16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04]
+0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04
+
+# CHECK: v_mad_u16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04]
+0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04
+
+# CHECK: v_mad_u16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x05,0xde,0x03]
+0x05,0x00,0x04,0xd2,0x01,0x05,0xde,0x03

llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_vi.txt

 0x09 0x00 0xc1 0xd1 0xf0 0x0a 0x22 0x84
 
 # VI:   v_ceil_f32_e64 v0, neg(-1)      ; encoding: [0x00,0x00,0x5d,0xd1,0xc1,0x00,0x00,0x20]
 0x00,0x00,0x5d,0xd1,0xc1,0x00,0x00,0x20
 
 # VI:   v_ceil_f32_e64 v0, neg(-1.0)    ; encoding: [0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20]
 0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20
 
+# VI: v_fma_f16 v5, v1, v2, v3    ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04
+
+# VI: v_fma_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xee,0xd1,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0xee,0xd1,0xf0,0x04,0x0e,0x04
+
+# VI: v_fma_f16 v5, v1, v2, |v3|    ; encoding: [0x05,0x04,0xee,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x04,0xee,0xd1,0x01,0x05,0x0e,0x04
+
+# VI: v_fma_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_div_fixup_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04
+
+# CHECK: v_div_fixup_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
+0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04
+
+# CHECK: v_div_fixup_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
+0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03
+
+# CHECK: v_div_fixup_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4
+
+# CHECK: v_div_fixup_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_div_fixup_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04
+
+# CHECK: v_mad_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
+0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04
+
+# CHECK: v_mad_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
+0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03
+
+# CHECK: v_mad_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4
+
+# CHECK: v_mad_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_i16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xec,0xd1,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0xec,0xd1,0xf0,0x04,0x0e,0x04
+
+# CHECK: v_mad_i16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0xec,0xd1,0x01,0xe1,0x0d,0x04]
+0x05,0x00,0xec,0xd1,0x01,0xe1,0x0d,0x04
+
+# CHECK: v_mad_i16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xc2,0x03]
+0x05,0x00,0xec,0xd1,0x01,0x05,0xc2,0x03
+
+# CHECK: v_mad_u16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
+0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04
+
+# CHECK: v_mad_u16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
+0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04
+
+# CHECK: v_mad_u16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
+0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03
+
 # VI: v_interp_mov_f32_e64 v5, p10, attr0.x    ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
 0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00
 
 # VI: v_interp_mov_f32_e64 v5, p10, attr32.x    ; encoding: [0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00]
 0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00
 
 # VI: v_interp_mov_f32_e64 v5, p20, attr0.x    ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00]
 0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00