[AMDGPU][MC][GFX8] added/corrected VOP3 versions of v_interp_* instructions

[dp]

Summary

Corrected syntax of v_interp_*_f16 opcodes to match sp3; added missing v_interp_*_f32_e64 opcodes.

See bug 32621: https://bugs.llvm.org//show_bug.cgi?id=32621

Known issues (postponed):

• non-vop3 v_interp opcodes are disassembled incorrectly (should have "_e32" suffix);
• there are subtle changes in gfx9 affecting v_interp_p2_f16; this will be accounted for at a later time.

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

enum ImmTy {
     ImmTySendMsg,
     ImmTyInterpSlot,
     ImmTyInterpAttr,
     ImmTyAttrChan,
     ImmTyOpSel,
     ImmTyOpSelHi,
     ImmTyNegLo,
     ImmTyNegHi,
-    ImmTySwizzle
+    ImmTySwizzle,
+    ImmTyHigh
   };
 
   struct TokOp {
     const char *Data;
     unsigned Length;
   };
 
   struct ImmOp {
public:
   bool isSDWADstUnused() const { return isImmTy(ImmTySdwaDstUnused); }
   bool isInterpSlot() const { return isImmTy(ImmTyInterpSlot); }
   bool isInterpAttr() const { return isImmTy(ImmTyInterpAttr); }
   bool isAttrChan() const { return isImmTy(ImmTyAttrChan); }
   bool isOpSel() const { return isImmTy(ImmTyOpSel); }
   bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }
   bool isNegLo() const { return isImmTy(ImmTyNegLo); }
   bool isNegHi() const { return isImmTy(ImmTyNegHi); }
+  bool isHigh() const { return isImmTy(ImmTyHigh); }
 
   bool isMod() const {
     return isClampSI() || isOModSI();
   }
 
   bool isRegOrImm() const {
     return isReg() || isImm();
   }
static void printImmTy(raw_ostream& OS, ImmTy Type) {
     case ImmTyInterpSlot: OS << "InterpSlot"; break;
     case ImmTyInterpAttr: OS << "InterpAttr"; break;
     case ImmTyAttrChan: OS << "AttrChan"; break;
     case ImmTyOpSel: OS << "OpSel"; break;
     case ImmTyOpSelHi: OS << "OpSelHi"; break;
     case ImmTyNegLo: OS << "NegLo"; break;
     case ImmTyNegHi: OS << "NegHi"; break;
     case ImmTySwizzle: OS << "Swizzle"; break;
+    case ImmTyHigh: OS << "High"; break;
     }
   }
 
   void print(raw_ostream &OS) const override {
     switch (Kind) {
     case Register:
       OS << "<register " << getReg() << " mods: " << Reg.Mods << '>';
       break;
public:
   OperandMatchResultTy parseOModOperand(OperandVector &Operands);
 
   void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
                OptionalImmIndexMap &OptionalIdx);
   void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
   void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
   void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
 
+  void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
+
   void cvtMIMG(MCInst &Inst, const OperandVector &Operands,
                bool IsAtomic = false);
   void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
 
   OperandMatchResultTy parseDPPCtrl(OperandVector &Operands);
   AMDGPUOperand::Ptr defaultRowMask() const;
   AMDGPUOperand::Ptr defaultBankMask() const;
   AMDGPUOperand::Ptr defaultBoundCtrl() const;
static const OptionalOperand AMDGPUOptionalOperandTable[] = {
   {"offset1", AMDGPUOperand::ImmTyOffset1, false, nullptr},
   {"gds",     AMDGPUOperand::ImmTyGDS, true, nullptr},
   {"offset",  AMDGPUOperand::ImmTyOffset, false, nullptr},
   {"dfmt",    AMDGPUOperand::ImmTyDFMT, false, nullptr},
   {"nfmt",    AMDGPUOperand::ImmTyNFMT, false, nullptr},
   {"glc",     AMDGPUOperand::ImmTyGLC, true, nullptr},
   {"slc",     AMDGPUOperand::ImmTySLC, true, nullptr},
   {"tfe",     AMDGPUOperand::ImmTyTFE, true, nullptr},
+  {"high",    AMDGPUOperand::ImmTyHigh, true, nullptr},
   {"clamp",   AMDGPUOperand::ImmTyClampSI, true, nullptr},
   {"omod",    AMDGPUOperand::ImmTyOModSI, false, ConvertOmodMul},
   {"unorm",   AMDGPUOperand::ImmTyUNorm, true, nullptr},
   {"da",      AMDGPUOperand::ImmTyDA,    true, nullptr},
   {"r128",    AMDGPUOperand::ImmTyR128,  true, nullptr},
   {"lwe",     AMDGPUOperand::ImmTyLWE,   true, nullptr},
   {"dmask",   AMDGPUOperand::ImmTyDMask, false, nullptr},
   {"row_mask",   AMDGPUOperand::ImmTyDppRowMask, false, nullptr},
return Desc.OpInfo[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS
       // 2. This is not last operand
       && Desc.NumOperands > (OpNum + 1)
       // 3. Next operand is register class
       && Desc.OpInfo[OpNum + 1].RegClass != -1
       // 4. Next register is not tied to any other operand
       && Desc.getOperandConstraint(OpNum + 1, MCOI::OperandConstraint::TIED_TO) == -1;
 }
 
+void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands) {
+
+  OptionalImmIndexMap OptionalIdx;
+  unsigned Opc = Inst.getOpcode();
+
+  unsigned I = 1;
+  const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
+  for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
+    ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
+  }
+
+  for (unsigned E = Operands.size(); I != E; ++I) {
+    AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
+    if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
+      Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
+    } else if (Op.isInterpSlot() ||
+               Op.isInterpAttr() ||
+               Op.isAttrChan()) {
+      Inst.addOperand(MCOperand::createImm(Op.Imm.Val));
+    } else if (Op.isImmModifier()) {
+      OptionalIdx[Op.getImmTy()] = I;
+    } else {
+      llvm_unreachable("unhandled operand type");
+    }
+  }
+
+  if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::high) != -1) {
+    addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyHigh);
+  }
+
+  if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) {
+    addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
+  }
+
+  if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) {
+    addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
+  }
+}
+
 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
                               OptionalImmIndexMap &OptionalIdx) {
   unsigned Opc = Inst.getOpcode();
 
   unsigned I = 1;
   const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
   for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
     ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);

llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h

void printExpTgt(const MCInst *MI, unsigned OpNo,
                    const MCSubtargetInfo &STI, raw_ostream &O);
 
   static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
                          StringRef Asm, StringRef Default = "");
   static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
                          char Asm);
   void printAbs(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                 raw_ostream &O);
+  void printHigh(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+                 raw_ostream &O);
   void printClamp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                   raw_ostream &O);
   void printClampSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O);
   void printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                    raw_ostream &O);
   void printLiteral(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O);

llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
   printIfSet(MI, OpNo, O, '|');
 }
 
 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
                                    const MCSubtargetInfo &STI, raw_ostream &O) {
   printIfSet(MI, OpNo, O, "_SAT");
 }
 
+void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
+                                  const MCSubtargetInfo &STI,
+                                  raw_ostream &O) {
+  if (MI->getOperand(OpNo).getImm())
+    O << " high";
+}
+
 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
                                      const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
   if (MI->getOperand(OpNo).getImm())
     O << " clamp";
 }
 
 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

 def offset : NamedOperandU16<"Offset", NamedMatchClass<"Offset">>;
 def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>;
 def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>;
 
 def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>;
 
 def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
 def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>;
+def highmod : NamedOperandBit<"High", NamedMatchClass<"High">>;
 
 def GLC : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>;
 def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
 def tfe : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>;
 def unorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>;
 def da : NamedOperandBit<"DA", NamedMatchClass<"DA">>;
 def r128 : NamedOperandBit<"R128", NamedMatchClass<"R128">>;
 def lwe : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
class VOPProfile <list<ValueType> _ArgVT> {
 
   field bit HasSrc0Mods = HasModifiers;
   field bit HasSrc1Mods = !if(HasModifiers, BitOr<HasSrc1FloatMods, HasSrc1IntMods>.ret, 0);
   field bit HasSrc2Mods = !if(HasModifiers, BitOr<HasSrc2FloatMods, HasSrc2IntMods>.ret, 0);
 
   field bit HasClamp = HasModifiers;
   field bit HasSDWAClamp = EmitDst;
   field bit HasFPClamp = BitAnd<isFloatType<DstVT>.ret, HasClamp>.ret;
+  field bit HasHigh = 0;
 
   field bit IsPacked = isPackedType<Src0VT>.ret;
   field bit HasOpSel = IsPacked;
   field bit HasOMod = !if(HasOpSel, 0, isFloatType<DstVT>.ret);
   field bit HasSDWAOMod = isFloatType<DstVT>.ret;
 
   field bit HasExt = getHasExt<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
   field bit HasSDWA9 = HasExt;

llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td

def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> {
   // FIXME: Hack to stop printing _e64
   let DstRC = RegisterOperand<VReg_64>;
 
   let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
   let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
 }
 
 //===----------------------------------------------------------------------===//
+// VOP3 INTERP
+//===----------------------------------------------------------------------===//
+
+class VOP3Interp<string OpName, VOPProfile P> : VOP3_Pseudo<OpName, P> {
+  let AsmMatchConverter = "cvtVOP3Interp";
+}
+
+def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
+  let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
+                   Attr:$attr, AttrChan:$attrchan,
+                   clampmod:$clamp, omod:$omod);
+
+  let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
+}
+
+def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
+  let Ins64 = (ins InterpSlot:$src0,
+                   Attr:$attr, AttrChan:$attrchan,
+                   clampmod:$clamp, omod:$omod);
+
+  let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
+
+  let HasClamp = 1;
+}
+
+class getInterp16Asm <bit HasSrc2, bit HasOMod> {
+  string src2 = !if(HasSrc2, ", $src2_modifiers", "");
+  string omod = !if(HasOMod, "$omod", "");
+  string ret =
+    " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod;
+}
+
+class getInterp16Ins <bit HasSrc2, bit HasOMod,
+                      Operand Src0Mod, Operand Src2Mod> {
+  dag ret = !if(HasSrc2,
+                !if(HasOMod,
+                    (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
+                         Attr:$attr, AttrChan:$attrchan,
+                         Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
+                         highmod:$high, clampmod:$clamp, omod:$omod),
+                    (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
+                         Attr:$attr, AttrChan:$attrchan,
+                         Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
+                         highmod:$high, clampmod:$clamp)
+                ),
+                (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
+                     Attr:$attr, AttrChan:$attrchan,
+                     highmod:$high, clampmod:$clamp, omod:$omod)
+            );
+}
+
+class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
+
+  let HasOMod = !if(!eq(DstVT.Value, f16.Value), 0, 1);
+  let HasHigh = 1;
+
+  let Outs64 = (outs VGPR_32:$vdst);
+  let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret;
+  let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret;
+}
+
+//===----------------------------------------------------------------------===//
 // VOP3 Instructions
 //===----------------------------------------------------------------------===//
 
 let isCommutable = 1 in {
 
 def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
 def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>;
 def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUmad_i24>;

 
 let SubtargetPredicate = Has16BitInsts in {
 
 def V_DIV_FIXUP_F16   : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>;
 
 let isCommutable = 1 in {
 
 def V_FMA_F16         : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
-def V_INTERP_P1LL_F16 : VOP3Inst <"v_interp_p1ll_f16", VOP3_Profile<VOP_F32_F32_F16>>;
-def V_INTERP_P1LV_F16 : VOP3Inst <"v_interp_p1lv_f16", VOP3_Profile<VOP_F32_F32_F16_F16>>;
-def V_INTERP_P2_F16   : VOP3Inst <"v_interp_p2_f16", VOP3_Profile<VOP_F16_F32_F16_F32>>;
+
+def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>>;
+def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;
+def V_INTERP_P2_F16   : VOP3Interp <"v_interp_p2_f16",   VOP3_INTERP16<[f16, f32, i32, f32]>>;
+
 def V_MAD_F16         : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
 
 def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
 def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
 
 }  // End isCommutable = 1
 } // End SubtargetPredicate = Has16BitInsts
 
 let SubtargetPredicate = isVI in {
+def V_INTERP_P1_F32_e64  : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
+def V_INTERP_P2_F32_e64  : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
+def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
+
 def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
 } // End SubtargetPredicate = isVI
 
 let Predicates = [Has16BitInsts] in {
 
 multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,
                              Instruction inst, SDPatternOperator op3> {
 def : Pat<
def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
             VOP3be_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
 }
 
 multiclass VOP3OpSel_Real_gfx9<bits<10> op> {
   def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
             VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
 }
 
+multiclass VOP3Interp_Real_vi<bits<10> op> {
+  def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
+            VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
+}
+
 } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
 
 defm V_MAD_U64_U32      : VOP3be_Real_vi <0x1E8>;
 defm V_MAD_I64_I32      : VOP3be_Real_vi <0x1E9>;
 
 defm V_MAD_LEGACY_F32   : VOP3_Real_vi <0x1c0>;
 defm V_MAD_F32          : VOP3_Real_vi <0x1c1>;
 defm V_MAD_I32_I24      : VOP3_Real_vi <0x1c2>;

 defm V_MAD_U16          : VOP3_Real_vi <0x1eb>;
 defm V_MAD_I16          : VOP3_Real_vi <0x1ec>;
 
 defm V_PERM_B32         : VOP3_Real_vi <0x1ed>;
 
 defm V_FMA_F16          : VOP3_Real_vi <0x1ee>;
 defm V_DIV_FIXUP_F16    : VOP3_Real_vi <0x1ef>;
 
-defm V_INTERP_P1LL_F16  : VOP3_Real_vi <0x274>;
-defm V_INTERP_P1LV_F16  : VOP3_Real_vi <0x275>;
-defm V_INTERP_P2_F16    : VOP3_Real_vi <0x276>;
+defm V_INTERP_P1_F32_e64  : VOP3Interp_Real_vi <0x270>;
+defm V_INTERP_P2_F32_e64  : VOP3Interp_Real_vi <0x271>;
+defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>;
+
+defm V_INTERP_P1LL_F16  : VOP3Interp_Real_vi <0x274>;
+defm V_INTERP_P1LV_F16  : VOP3Interp_Real_vi <0x275>;
+defm V_INTERP_P2_F16    : VOP3Interp_Real_vi <0x276>;
 defm V_ADD_F64          : VOP3_Real_vi <0x280>;
 defm V_MUL_F64          : VOP3_Real_vi <0x281>;
 defm V_MIN_F64          : VOP3_Real_vi <0x282>;
 defm V_MAX_F64          : VOP3_Real_vi <0x283>;
 defm V_LDEXP_F64        : VOP3_Real_vi <0x284>;
 defm V_MUL_LO_U32       : VOP3_Real_vi <0x285>;
 
 // removed from VI as identical to V_MUL_LO_U32

llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td

 
 class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> {
   let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0);
   let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0);
   let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0);
   let Inst{14} = !if(P.HasDst,  src0_modifiers{3}, 0);
 }
 
+// NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa
+class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> {
+  bits<2> attrchan;
+  bits<6> attr;
+  bits<1> high;
+
+  let Inst{8}     = 0; // No modifiers for src0
+  let Inst{61}    = 0;
+
+  let Inst{9}     = !if(P.HasSrc0Mods, src0_modifiers{1}, 0);
+  let Inst{62}    = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
+
+  let Inst{37-32} = attr;
+  let Inst{39-38} = attrchan;
+  let Inst{40}    = !if(P.HasHigh, high, 0);
+
+  let Inst{49-41} = src0;
+}
+
 class VOP3be <VOPProfile P> : Enc64 {
   bits<8> vdst;
   bits<2> src0_modifiers;
   bits<9> src0;
   bits<2> src1_modifiers;
   bits<9> src1;
   bits<2> src2_modifiers;
   bits<9> src2;

llvm/trunk/test/MC/AMDGPU/vop3-errs.s

 
 v_cmp_eq_f32_e64 vcc, v0, v1 mul:2
 // GCN: error: invalid operand for instruction
 
 v_cmp_le_f64_e64 vcc, v0, v1 mul:4
 // GCN: error: invalid operand for instruction
 
 v_cvt_u32_f32_e64 v0, v1 div:2
-// GCN: error: invalid operand for instruction
+// GCN: error: invalid operand for instruction
+
+//
+// v_interp*
+//
+
+v_interp_mov_f32_e64 v5, p10, attr0.x high
+// GCN: error: invalid operand for instruction
+
+v_interp_mov_f32_e64 v5, p10, attr0.x v0
+// GCN: error: invalid operand for instruction
+
+v_interp_p1_f32_e64 v5, v2, attr0.x high
+// GCN: error: invalid operand for instruction
+
+v_interp_p1_f32_e64 v5, v2, attr0.x v0
+// GCN: error: invalid operand for instruction
+
+v_interp_p2_f32_e64 v255, v2, attr0.x high
+// GCN: error: invalid operand for instruction
+
+v_interp_p2_f32_e64 v255, v2, attr0.x v0
+// GCN: error: invalid operand for instruction
+
+v_interp_p1ll_f16 v5, p0, attr31.x
+// GCN: error: invalid operand for instruction
+
+v_interp_p1ll_f16 v5, v2, attr31.x v0
+// GCN: error: invalid operand for instruction
+
+v_interp_p2_f16 v5, v2, attr1.x, v3 mul:2
+// GFX67: error: not a valid operand
+// GFX89: error: invalid operand for instruction

llvm/trunk/test/MC/AMDGPU/vop3.s

 
 v_mul_f64 v[0:1], |0|, |0|
 // SICI: v_mul_f64 v[0:1], |0|, |0|      ; encoding: [0x00,0x03,0xca,0xd2,0x80,0x00,0x01,0x00]
 // VI:   v_mul_f64 v[0:1], |0|, |0|      ; encoding: [0x00,0x03,0x81,0xd2,0x80,0x00,0x01,0x00]
 
 v_cubeid_f32 v0, |-1|, |-1.0|, |1.0|
 // SICI: v_cubeid_f32 v0, |-1|, |-1.0|, |1.0| ; encoding: [0x00,0x07,0x88,0xd2,0xc1,0xe6,0xc9,0x03]
 // VI:   v_cubeid_f32 v0, |-1|, |-1.0|, |1.0| ; encoding: [0x00,0x07,0xc4,0xd1,0xc1,0xe6,0xc9,0x03]
+
+//
+// v_interp*
+//
+
+v_interp_mov_f32_e64 v5, p10, attr0.x
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr32.x
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_mov_f32_e64 v5, p10, attr32.x ; encoding: [0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p20, attr0.x
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_mov_f32_e64 v5, p20, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.w
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.w ; encoding: [0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32 v5, p10, attr0.x clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x mul:2
+// NOSICI: error: not a valid operand
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x mul:4
+// NOSICI: error: not a valid operand
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x div:2
+// NOSICI: error: not a valid operand
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
+
+v_interp_mov_f32 v5, p10, attr0.x div:2
+// NOSICI: error: not a valid operand
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
+
+
+v_interp_p1_f32_e64 v5, v2, attr0.x
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_p1_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.y
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_p1_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x70,0xd2,0x40,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, -v2, attr0.x
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40]
+
+v_interp_p1_f32_e64 v5, |v2|, attr0.x
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32 v5, v2, attr0.x clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x mul:2
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08]
+
+
+v_interp_p2_f32_e64 v255, v2, attr0.x
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_p2_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr31.x
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_p2_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, -v2, attr0.x
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40]
+
+v_interp_p2_f32_e64 v5, |v2|, attr0.x
+// NOSICI: error: not a valid operand
+// VI: v_interp_p2_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x div:2
+// NOSICI: error: not a valid operand
+// VI: v_interp_p2_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x18]
+
+
+v_interp_p1ll_f16 v5, v2, attr31.x
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1ll_f16 v5, v2, attr31.x ; encoding: [0x05,0x00,0x74,0xd2,0x1f,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.w
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1ll_f16 v5, v2, attr0.w ; encoding: [0x05,0x00,0x74,0xd2,0xc0,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, -v2, attr0.x
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1ll_f16 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40]
+
+v_interp_p1ll_f16 v5, |v2|, attr0.x
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1ll_f16 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x high
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1ll_f16 v5, v2, attr0.x high ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1ll_f16 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x mul:4
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1ll_f16 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x10]
+
+
+v_interp_p1lv_f16 v5, v2, attr1.x, v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1lv_f16 v5, v2, attr1.x, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x01,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.z, v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1lv_f16 v5, v2, attr0.z, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x80,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, -v2, attr0.x, v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1lv_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, -v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1lv_f16 v5, v2, attr0.x, -v3 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84]
+
+v_interp_p1lv_f16 v5, |v2|, attr0.x, v3
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1lv_f16 v5, |v2|, attr0.x, v3 ; encoding: [0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, |v3|
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1lv_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 high
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:2
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:2 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x0c]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 div:2
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 div:2 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x1c]
+
+
+v_interp_p2_f16 v5, v2, attr1.x, v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f16 v5, v2, attr1.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr32.x, v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f16 v5, v2, attr32.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x20,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.w, v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, -v2, attr0.x, v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
+
+v_interp_p2_f16 v5, v2, attr0.x, -v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f16 v5, v2, attr0.x, -v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84]
+
+v_interp_p2_f16 v5, |v2|, attr0.x, v3
+// NOSICI: error: not a valid operand
+// VI: v_interp_p2_f16 v5, |v2|, attr0.x, v3 ; encoding: [0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, |v3|
+// NOSICI: error: not a valid operand
+// VI: v_interp_p2_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3 high
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]

llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_vi.txt

 # VI:   v_mad_f32 v9, 0.5, v5, -v8      ; encoding: [0x09,0x00,0xc1,0xd1,0xf0,0x0a,0x22,0x84]
 0x09 0x00 0xc1 0xd1 0xf0 0x0a 0x22 0x84
 
 # VI:   v_ceil_f32_e64 v0, neg(-1)      ; encoding: [0x00,0x00,0x5d,0xd1,0xc1,0x00,0x00,0x20]
 0x00,0x00,0x5d,0xd1,0xc1,0x00,0x00,0x20
 
 # VI:   v_ceil_f32_e64 v0, neg(-1.0)    ; encoding: [0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20]
 0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20
+
+# VI: v_interp_mov_f32_e64 v5, p10, attr0.x    ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
+0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00
+
+# VI: v_interp_mov_f32_e64 v5, p10, attr32.x    ; encoding: [0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00]
+0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00
+
+# VI: v_interp_mov_f32_e64 v5, p20, attr0.x    ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00]
+0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00
+
+# VI: v_interp_mov_f32_e64 v5, p10, attr0.w    ; encoding: [0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00]
+0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00
+
+# VI: v_interp_mov_f32_e64 v5, p10, attr0.x clamp    ; encoding: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
+0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00
+
+# VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2    ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08]
+0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08
+
+# VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4    ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10]
+0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10
+
+# VI: v_interp_mov_f32_e64 v5, p10, attr0.x div:2    ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
+0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18
+
+# VI: v_interp_p1_f32_e64 v255, v2, attr0.x    ; encoding: [0xff,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
+0xff,0x00,0x70,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p1_f32_e64 v5, v2, attr1.x    ; encoding: [0x05,0x00,0x70,0xd2,0x01,0x04,0x02,0x00]
+0x05,0x00,0x70,0xd2,0x01,0x04,0x02,0x00
+
+# VI: v_interp_p1_f32_e64 v5, -v2, attr0.x    ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40]
+0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40
+
+# VI: v_interp_p1_f32_e64 v5, |v2|, attr0.x    ; encoding: [0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p1_f32_e64 v5, v2, attr0.z    ; encoding: [0x05,0x00,0x70,0xd2,0x80,0x04,0x02,0x00]
+0x05,0x00,0x70,0xd2,0x80,0x04,0x02,0x00
+
+# VI: v_interp_p1_f32_e64 v5, v2, attr0.x clamp    ; encoding: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p1_f32_e64 v5, v2, attr0.x mul:2    ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08]
+0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08
+
+# VI: v_interp_p2_f32_e64 v5, v2, attr0.x    ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p2_f32_e64 v5, v2, attr31.x    ; encoding: [0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00]
+0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00
+
+# VI: v_interp_p2_f32_e64 v5, -v2, attr0.x    ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40]
+0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40
+
+# VI: v_interp_p2_f32_e64 v5, |v2|, attr0.x    ; encoding: [0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p2_f32_e64 v5, v2, attr0.y    ; encoding: [0x05,0x00,0x71,0xd2,0x40,0x04,0x02,0x00]
+0x05,0x00,0x71,0xd2,0x40,0x04,0x02,0x00
+
+# VI: v_interp_p2_f32_e64 v5, v2, attr0.x clamp    ; encoding: [0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p2_f32_e64 v5, v2, attr0.x mul:4    ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x10]
+0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x10
+
+# VI: v_interp_p1ll_f16 v5, v2, attr0.x    ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p1ll_f16 v5, v2, attr1.x    ; encoding: [0x05,0x00,0x74,0xd2,0x01,0x04,0x02,0x00]
+0x05,0x00,0x74,0xd2,0x01,0x04,0x02,0x00
+
+# VI: v_interp_p1ll_f16 v5, -v2, attr0.x    ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40]
+0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40
+
+# VI: v_interp_p1ll_f16 v5, |v2|, attr0.x    ; encoding: [0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p1ll_f16 v5, v2, attr0.y    ; encoding: [0x05,0x00,0x74,0xd2,0x40,0x04,0x02,0x00]
+0x05,0x00,0x74,0xd2,0x40,0x04,0x02,0x00
+
+# VI: v_interp_p1ll_f16 v5, v2, attr0.x high    ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00]
+0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00
+
+# VI: v_interp_p1ll_f16 v5, v2, attr0.x clamp    ; encoding: [0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p1ll_f16 v5, v2, attr0.x div:2    ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x18]
+0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x18
+
+# VI: v_interp_p1lv_f16 v255, v2, attr0.x, v3    ; encoding: [0xff,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04]
+0xff,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04
+
+# VI: v_interp_p1lv_f16 v5, v2, attr32.x, v3    ; encoding: [0x05,0x00,0x75,0xd2,0x20,0x04,0x0e,0x04]
+0x05,0x00,0x75,0xd2,0x20,0x04,0x0e,0x04
+
+# VI: v_interp_p1lv_f16 v5, -v2, attr0.x, v3    ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44]
+0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44
+
+# VI: v_interp_p1lv_f16 v5, v2, attr0.x, -v3    ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84]
+0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84
+
+# VI: v_interp_p1lv_f16 v5, |v2|, attr0.x, v3    ; encoding: [0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04
+
+# VI: v_interp_p1lv_f16 v5, v2, attr0.x, |v3|    ; encoding: [0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04
+
+# VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 high    ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04]
+0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04
+
+# VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp    ; encoding: [0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04
+
+# VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:4    ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x14]
+0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x14
+
+# VI: v_interp_p2_f16 v5, v2, attr0.x, v3    ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04
+
+# VI: v_interp_p2_f16 v5, v2, attr1.x, v3    ; encoding: [0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04]
+0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04
+
+# VI: v_interp_p2_f16 v5, -v2, attr0.x, v3    ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
+0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44
+
+# VI: v_interp_p2_f16 v5, v2, attr0.x, -v3    ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84]
+0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84
+
+# VI: v_interp_p2_f16 v5, |v2|, attr0.x, v3    ; encoding: [0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04
+
+# VI: v_interp_p2_f16 v5, v2, attr0.x, |v3|    ; encoding: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04
+
+# VI: v_interp_p2_f16 v5, v2, attr0.x, v3 high    ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
+0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04
+
+# VI: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp    ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04