[AArch64] Extend CallingConv::X86_64_Win64 to AArch64 as well

[mstorsjo]

Summary

Rename the enum value from X86_64_Win64 to plain Win64.

The symbol exposed in the textual IR is changed from 'x86_64_win64cc' to 'win64cc', but the numeric value is kept, keeping support for old bitcode.

[compnerd]

I don't think that we should be adding a new calling convention for this. Win/AArch64 is just AAPCS64. Just like ARM, the difference for the va_list can be abstracted out entirely in the frontend, even if it is through a new LLVM intrinsic.

[t.p.northover]

I think MSVC has to have changed the ABI from AAPCS if they've managed to get a "void *" va_list to work; the extra complexity in AAPCS isn't there for the giggles. x86 appears to mirror floating args into integer registers.

If code isn't expected to interoperate, this becomes analogous to the DarwinPCS calling convention (it exists within lib/Target/AArch64 and affects CodeGen but doesn't need to be exposed in IR). If the Wine use-case does involve interoperation (and is supported) then a separate IR-level calling convention is probably unavoidable.

[mgrang]

We are working on adding support for the Windows ARM64 COFF format and recently upstreamed two patches https://reviews.llvm.org/D34705 and https://reviews.llvm.org/D34706.
This patch is a prerequisite for us to support printf calls in our use-case. Looking forward to get this merged once comments are addressed :)

--Mandeep

[mstorsjo]

In D34474#792899, @t.p.northover wrote:

I think MSVC has to have changed the ABI from AAPCS if they've managed to get a "void *" va_list to work; the extra complexity in AAPCS isn't there for the giggles. x86 appears to mirror floating args into integer registers.

Indeed. Since I don't have access to the actual MSVC compiler for arm64, I can't easily verify what it does with float arguments to vararg functions (unless I can find a easily triggered printf case in any of the arm64 exes included in the win10 sdk), but the va_list is a plain void pointer at least.

If code isn't expected to interoperate, this becomes analogous to the DarwinPCS calling convention (it exists within lib/Target/AArch64 and affects CodeGen but doesn't need to be exposed in IR). If the Wine use-case does involve interoperation (and is supported) then a separate IR-level calling convention is probably unavoidable.

Indeed. I can try to update the patch and clarify the comments that it is mostly-AAPCS compliant, but floats are passed in integer registers (which is a sensible hypothesis until someone can confirm or deny this).

Mandeep, do you have access to proper MSVC tools for arm64? Could you verify how floats are passed as function arguments (in float registers or in integer registers) for both normal and variadic functions?

[mgrang]

@mstorsjo I have an MSVC compiler for ARM64 and I found that it always passes floats in integer registers:

float a = 1.1;
float b = 2.1;
float c = 3.1;
float d = 4.1;
float e = 5.1;
float f = 6.1;
float g = 7.1;
float h = 8.1;
float i = 9.1;
float j = 10.1;

printf("%f %f %f %f %f %f %f %f %f %f", a, b, c, d, e, f, g, h, i, j);

0000000000000058: BD0033F0  str         s16,[sp,#0x30]
000000000000005C: BD4033F0  ldr         s16,[sp,#0x30]
0000000000000060: 1E22C219  fcvt        d25,s16
0000000000000064: BD4037F0  ldr         s16,[sp,#0x34]
0000000000000068: 1E22C218  fcvt        d24,s16
000000000000006C: BD403BF0  ldr         s16,[sp,#0x38]
0000000000000070: 1E22C217  fcvt        d23,s16
0000000000000074: BD403FF0  ldr         s16,[sp,#0x3C]
0000000000000078: 1E22C216  fcvt        d22,s16
000000000000007C: BD4043F0  ldr         s16,[sp,#0x40]
0000000000000080: 1E22C215  fcvt        d21,s16
0000000000000084: BD4047F0  ldr         s16,[sp,#0x44]
0000000000000088: 1E22C214  fcvt        d20,s16
000000000000008C: BD404BF0  ldr         s16,[sp,#0x48]
0000000000000090: 1E22C213  fcvt        d19,s16
0000000000000094: BD404FF0  ldr         s16,[sp,#0x4C]
0000000000000098: 1E22C212  fcvt        d18,s16
000000000000009C: BD4053F0  ldr         s16,[sp,#0x50]
00000000000000A0: 1E22C211  fcvt        d17,s16
00000000000000A4: BD4057F0  ldr         s16,[sp,#0x54]
00000000000000A8: 1E22C210  fcvt        d16,s16
00000000000000AC: FD000BF9  str         d25,[sp,#0x10]
00000000000000B0: FD0007F8  str         d24,[sp,#8]
00000000000000B4: FD0003F7  str         d23,[sp]
00000000000000B8: 9E6602C7  fmov        x7,d22
00000000000000BC: 9E6602A6  fmov        x6,d21
00000000000000C0: 9E660285  fmov        x5,d20
00000000000000C4: 9E660264  fmov        x4,d19
00000000000000C8: 9E660243  fmov        x3,d18
00000000000000CC: 9E660222  fmov        x2,d17
00000000000000D0: 9E660201  fmov        x1,d16
00000000000000D4: 90000008  adrp        x8,$SG5071
00000000000000D8: 91000100  add         x0,x8,$SG5071
00000000000000DC: 94000000  bl          printf

[mgrang]

foo(a, b, c, d, e, f, g, h, i, j);

000000000000012C: BD402BE7  ldr         s7,[sp,#0x28]
0000000000000130: BD402FE6  ldr         s6,[sp,#0x2C]
0000000000000134: BD4033E5  ldr         s5,[sp,#0x30]
0000000000000138: BD4037E4  ldr         s4,[sp,#0x34]
000000000000013C: BD403BE3  ldr         s3,[sp,#0x38]
0000000000000140: BD403FE2  ldr         s2,[sp,#0x3C]
0000000000000144: BD4043E1  ldr         s1,[sp,#0x40]
0000000000000148: BD4047E0  ldr         s0,[sp,#0x44]
000000000000014C: 94000000  bl          foo

[mstorsjo]

In D34474#794320, @mgrang wrote:

@mstorsjo I have an MSVC compiler for ARM64 and I found that it always passes floats in integer registers:

Great, thanks for checking!

I've revised the patch now, by trying to store the variadic arguments directly below the rest of the arguments on the stack, so that they will work seamlessly as one single array.

[mstorsjo]

Updated to clarify that the windows arm64 calling convention actually differs from normal AAPCS when it comes to calling variadic functions. (Support for actually passing parameters that way is not yet implemented).

I also updated it to try to store the variadic arguments directly below the rest of the arguments on the stack, so that they will work seamlessly as one single array.

[mstorsjo]

Ping - can someone who knows aarch64 and/or LLVM internals in general, comment on whether the stack handling is correct (I'm not confident about that part of code but just tried to look at the ARM and X86 targets to figure out enough to make it work). The generated function prologues start with two "sub sp, sp, #..." instructions - one for the area reserved for storing register arguments to fit in with the rest of the arguments on the stack, and one for the rest of the stack usage.

[compnerd]

I'm still not sure I understand why we need the different CC when X86_64 is able to handle both the SysV and the MS style VAArg lowering via the ABI::LowerVAArg switching between the two. I feel that we should follow a similar approach here.

[mstorsjo]

In D34474#799086, @compnerd wrote:

I'm still not sure I understand why we need the different CC when X86_64 is able to handle both the SysV and the MS style VAArg lowering via the ABI::LowerVAArg switching between the two. I feel that we should follow a similar approach here.

This does in fact use the exat same approach as on x86_64. It's not an issue with LowerVAARG (where the handling of the MS style can be encapsulated on the clang level so there's no need for any support for that on the LLVM level at all), but the issue is with LowerVASTART. And for LowerVASTART, the handling is identical to the one on x86_64. The key parts from X86TargetLowering::LowerVASTART in lib/Target/X86/X86ISelLowering.cpp:

SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
  if (!Subtarget.is64Bit() ||   
      Subtarget.isCallingConvWin64(MF.getFunction()->getCallingConv())) {

And isCallingConvWin64 contains this (redacted):

bool isCallingConvWin64(CallingConv::ID CC) const {
  switch (CC) {
  // On Win64, all these conventions just use the default convention.
  case CallingConv::C:
    return isTargetWin64();
  // This convention allows using the Win64 convention on other targets.
  case CallingConv::X86_64_Win64:
    return true;
  // This convention allows using the SysV convention on Windows targets.
  case CallingConv::X86_64_SysV:
    return false;
  // Otherwise, who knows what this is.
  default:
    return false;
  }

As long as the windows ABI only should be used while targeting windows, we indeed don't need a separate calling convention exposed in the IR. But in order to be able to implement wine, we need to be able to signal that this particular function uses a convention different from the default of the current target triplet.

[mstorsjo]

Implemented correct handling of passing of floats in calls to vararg functions as well.

[mstorsjo]

I guess at this point, it'd make sense to split this into two patches, one for adding the general support for arm64/win varargs, and one for adding the extra keywords for enabling wine to use it in builds targeting Linux. I'll update the patches to that effect tomorrow.

[mstorsjo]

Split the patch into two, one prerequisite (D35006) which adds generic support for win64/arm64 varargs, and this one adds the necessary things for enabling this while targeting e.g. linux (basically for using it in wine).

[mstorsjo]

Added a test case, rebased on top of the version of D35006 that was committed, removed the RFC tag from the title.

[rnk]

I commented on the clang side that I think it's worth having a single ms_abi calling convention, but I don't think it matters too much for LLVM. The only code that cares about the convention is going to be in lib/Target/{X86|AArch64} anyway. It might be worth a try, though.

[t.p.northover]

I agree with Reid. There are now 2 targets using this and it seems like a generic requirement of Windows & Wine interoperability; it's time to make it generic.

[mstorsjo]

In D34474#809625, @t.p.northover wrote:

I agree with Reid. There are now 2 targets using this and it seems like a generic requirement of Windows & Wine interoperability; it's time to make it generic.

So, in unifying it and making it generic, what backwards compat requirements are there on the IR? Can I rename the calling convention enum (X86_64_Win64, to e.g. just Win64) and just force all callers (at least clang) to catch up at once? And what about textual IR? There are IR backwards compat tests that use the "x86_64_win64cc" name.

Reid also hinted at wanting to hook up the "sysv_abi" attribute for the inverse generically, but for aarch64, there's not just one inverse but two (aapcs and darwin), so I'd rather only do the win64 one first (where there's a direct need) while the others only would be for completeness (afaik, at least so far).

[t.p.northover]

So, in unifying it and making it generic, what backwards compat requirements are there on the IR? Can I rename the calling convention enum (X86_64_Win64, to e.g. just Win64) and just force all callers (at least clang) to catch up at once?

I think so. As long as you don't change the enumerator number existing .bc files should be compatible, and they're only exposed as ints on the C interface so that's not an issue. It's fine to change the name in the backwards compatibility tests IMO.

[mstorsjo]

Updated as suggested, by changing the existing CallingConvention::X86_64_Win64 into a generic CallingConvention::Win64, retaining binary compatiblity with old bitcode but changing the textual representation.

[mstorsjo]

Ping Tim and Reid - does this look an acceptable solution?

[t.p.northover]

I think this looks pretty much as I'd expect. Thanks for working on the generic refactoring.

include/llvm/IR/CallingConv.h

enum {
     /// Calling convention used for Mesa hull shaders. (= tessellation control
     /// shaders)
     AMDGPU_HS = 93,
 
     /// Calling convention used for special MSP430 rtlib functions
     /// which have an "optimized" convention using additional registers.
     MSP430_BUILTIN = 94,
 
+    /// \brief The C convention as implemented on Windows/arm64. This
+    /// is similar to the normal C (AAPCS) calling convention for normal
+    /// functions, but floats are passed in integer registers to variadic
+    /// functions.
+    AArch64_Win64 = 95,
+
     /// The highest possible calling convention ID. Must be some 2^k - 1.
     MaxID = 1023
   };
 
 } // end namespace CallingConv
 
 } // end namespace llvm
 
 #endif // LLVM_IR_CALLINGCONV_H

lib/AsmParser/LLLexer.cpp

#define KEYWORD(STR)                                                           \
   KEYWORD(hhvm_ccc);
   KEYWORD(cxx_fast_tlscc);
   KEYWORD(amdgpu_vs);
   KEYWORD(amdgpu_hs);
   KEYWORD(amdgpu_gs);
   KEYWORD(amdgpu_ps);
   KEYWORD(amdgpu_cs);
   KEYWORD(amdgpu_kernel);
+  KEYWORD(aarch64_win64cc);
 
   KEYWORD(cc);
   KEYWORD(c);
 
   KEYWORD(attributes);
 
   KEYWORD(alwaysinline);
   KEYWORD(allocsize);

lib/AsmParser/LLParser.cpp

 ///   ::= 'hhvm_ccc'
 ///   ::= 'cxx_fast_tlscc'
 ///   ::= 'amdgpu_vs'
 ///   ::= 'amdgpu_hs'
 ///   ::= 'amdgpu_gs'
 ///   ::= 'amdgpu_ps'
 ///   ::= 'amdgpu_cs'
 ///   ::= 'amdgpu_kernel'
+///   ::= 'aarch64_win64cc'
 ///   ::= 'cc' UINT
 ///
 bool LLParser::ParseOptionalCallingConv(unsigned &CC) {
   switch (Lex.getKind()) {
   default:                       CC = CallingConv::C; return false;
   case lltok::kw_ccc:            CC = CallingConv::C; break;
   case lltok::kw_fastcc:         CC = CallingConv::Fast; break;
   case lltok::kw_coldcc:         CC = CallingConv::Cold; break;
bool LLParser::ParseOptionalCallingConv(unsigned &CC) {
   case lltok::kw_hhvm_ccc:       CC = CallingConv::HHVM_C; break;
   case lltok::kw_cxx_fast_tlscc: CC = CallingConv::CXX_FAST_TLS; break;
   case lltok::kw_amdgpu_vs:      CC = CallingConv::AMDGPU_VS; break;
   case lltok::kw_amdgpu_hs:      CC = CallingConv::AMDGPU_HS; break;
   case lltok::kw_amdgpu_gs:      CC = CallingConv::AMDGPU_GS; break;
   case lltok::kw_amdgpu_ps:      CC = CallingConv::AMDGPU_PS; break;
   case lltok::kw_amdgpu_cs:      CC = CallingConv::AMDGPU_CS; break;
   case lltok::kw_amdgpu_kernel:  CC = CallingConv::AMDGPU_KERNEL; break;
+  case lltok::kw_aarch64_win64cc: CC = CallingConv::AArch64_Win64; break;
   case lltok::kw_cc: {
       Lex.Lex();
       return ParseUInt32(CC);
     }
   }
 
   Lex.Lex();
   return false;

lib/AsmParser/LLToken.h

enum Kind {
   kw_hhvm_ccc,
   kw_cxx_fast_tlscc,
   kw_amdgpu_vs,
   kw_amdgpu_hs,
   kw_amdgpu_gs,
   kw_amdgpu_ps,
   kw_amdgpu_cs,
   kw_amdgpu_kernel,
+  kw_aarch64_win64cc,
 
   // Attributes:
   kw_attributes,
   kw_allocsize,
   kw_alwaysinline,
   kw_argmemonly,
   kw_sanitize_address,
   kw_builtin,

lib/IR/AsmWriter.cpp

static void PrintCallingConv(unsigned cc, raw_ostream &Out) {
   case CallingConv::HHVM:          Out << "hhvmcc"; break;
   case CallingConv::HHVM_C:        Out << "hhvm_ccc"; break;
   case CallingConv::AMDGPU_VS:     Out << "amdgpu_vs"; break;
   case CallingConv::AMDGPU_HS:     Out << "amdgpu_hs"; break;
   case CallingConv::AMDGPU_GS:     Out << "amdgpu_gs"; break;
   case CallingConv::AMDGPU_PS:     Out << "amdgpu_ps"; break;
   case CallingConv::AMDGPU_CS:     Out << "amdgpu_cs"; break;
   case CallingConv::AMDGPU_KERNEL: Out << "amdgpu_kernel"; break;
+  case CallingConv::AArch64_Win64: Out << "aarch64_win64cc"; break;
   }
 }
 
 void llvm::PrintEscapedString(StringRef Name, raw_ostream &Out) {
   for (unsigned i = 0, e = Name.size(); i != e; ++i) {
     unsigned char C = Name[i];
     if (isprint(C) && C != '\\' && C != '"')
       Out << C;

lib/Target/AArch64/AArch64FrameLowering.cpp

 //
 // |                                   | Higher address
 // |-----------------------------------|
 // |                                   |
 // | arguments passed on the stack     |
 // |                                   |
 // |-----------------------------------|
 // |                                   |
+// | (Win64 only) varargs from reg     |
+// |                                   |
+// |-----------------------------------|
+// |                                   |
 // | prev_fp, prev_lr                  |
 // | (a.k.a. "frame record")           |
 // |-----------------------------------| <- fp(=x29)
 // |                                   |
 // | other callee-saved registers      |
 // |                                   |
 // |-----------------------------------|
 // |.empty.space.to.make.part.below....|
void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
   const Function *Fn = MF.getFunction();
   const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   MachineModuleInfo &MMI = MF.getMMI();
   AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
   bool needsFrameMoves = MMI.hasDebugInfo() || Fn->needsUnwindTableEntry();
   bool HasFP = hasFP(MF);
+  unsigned GPRSaveSize = alignTo(AFI->getVarArgsGPRSize(), 16);
+  bool IsWin64 = Subtarget.isCallingConvWin64(MF.getFunction()->getCallingConv());
 
   // Debug location must be unknown since the first debug location is used
   // to determine the end of the prologue.
   DebugLoc DL;
 
   // All calls are tail calls in GHC calling conv, and functions have no
   // prologue/epilogue.
   if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
     return;
 
+  if (GPRSaveSize && IsWin64)
+      emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, -GPRSaveSize, TII,
+                      MachineInstr::FrameSetup);
+
   int NumBytes = (int)MFI.getStackSize();
   if (!AFI->hasStackFrame()) {
     assert(!HasFP && "unexpected function without stack frame but with FP");
 
     // All of the stack allocation is for locals.
     AFI->setLocalStackSize(NumBytes);
 
     if (!NumBytes)
void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
   if (MBB.end() != MBBI) {
     DL = MBBI->getDebugLoc();
     unsigned RetOpcode = MBBI->getOpcode();
     IsTailCallReturn = RetOpcode == AArch64::TCRETURNdi ||
       RetOpcode == AArch64::TCRETURNri;
   }
   int NumBytes = MFI.getStackSize();
   const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
+  bool IsWin64 = Subtarget.isCallingConvWin64(MF.getFunction()->getCallingConv());
 
   // All calls are tail calls in GHC calling conv, and functions have no
   // prologue/epilogue.
   if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
     return;
 
   // Initial and residual are named for consistency with the prologue. Note that
   // in the epilogue, the residual adjustment is executed first.
   uint64_t ArgumentPopSize = 0;
   if (IsTailCallReturn) {
     MachineOperand &StackAdjust = MBBI->getOperand(1);
 
     // For a tail-call in a callee-pops-arguments environment, some or all of
     // the stack may actually be in use for the call's arguments, this is
     // calculated during LowerCall and consumed here...
     ArgumentPopSize = StackAdjust.getImm();
   } else {
     // ... otherwise the amount to pop is *all* of the argument space,
     // conveniently stored in the MachineFunctionInfo by
     // LowerFormalArguments. This will, of course, be zero for the C calling
     // convention.
     ArgumentPopSize = AFI->getArgumentStackToRestore();
   }
 
+  if (IsWin64)
+    ArgumentPopSize += alignTo(AFI->getVarArgsGPRSize(), 16);
+
   // The stack frame should be like below,
   //
   //      ----------------------                     ---
   //      |                    |                      |
   //      | BytesInStackArgArea|              CalleeArgStackSize
   //      | (NumReusableBytes) |                (of tail call)
   //      |                    |                     ---
   //      |                    |                      |

lib/Target/AArch64/AArch64ISelLowering.h

private:
   SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
                          SDValue TVal, SDValue FVal, const SDLoc &dl,
                          SelectionDAG &DAG) const;
   SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;

lib/Target/AArch64/AArch64ISelLowering.cpp

case CallingConv::WebKit_JS:
     return CC_AArch64_WebKit_JS;
   case CallingConv::GHC:
     return CC_AArch64_GHC;
   case CallingConv::C:
   case CallingConv::Fast:
   case CallingConv::PreserveMost:
   case CallingConv::CXX_FAST_TLS:
   case CallingConv::Swift:
+  case CallingConv::AArch64_Win64:
     if (!Subtarget->isTargetDarwin())
       return CC_AArch64_AAPCS;
     return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
   }
 }
 
 CCAssignFn *
 AArch64TargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {
   return CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
                                       : RetCC_AArch64_AAPCS;
 }
 
 SDValue AArch64TargetLowering::LowerFormalArguments(
     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo &MFI = MF.getFrameInfo();
+  bool IsWin64 = Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv());
 
   // Assign locations to all of the incoming arguments.
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
                  *DAG.getContext());
 
   // At this point, Ins[].VT may already be promoted to i32. To correctly
   // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
if (VA.isRegLoc()) {
 
       InVals.push_back(ArgValue);
     }
   }
 
   // varargs
   AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
   if (isVarArg) {
-    if (!Subtarget->isTargetDarwin()) {
+    if (!Subtarget->isTargetDarwin() || IsWin64) {
       // The AAPCS variadic function ABI is identical to the non-variadic
       // one. As a result there may be more arguments in registers and we should
       // save them for future reference.
+      // For Win64 variadic functions, all float arguments are passed in integer
+      // registers.
       saveVarArgRegisters(CCInfo, DAG, DL, Chain);
     }
 
     // This will point to the next argument passed via stack.
     unsigned StackOffset = CCInfo.getNextStackOffset();
     // We currently pass all varargs at 8-byte alignment.
     StackOffset = ((StackOffset + 7) & ~7);
     FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));

 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
                                                 SelectionDAG &DAG,
                                                 const SDLoc &DL,
                                                 SDValue &Chain) const {
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
   auto PtrVT = getPointerTy(DAG.getDataLayout());
+  bool IsWin64 = Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv());
 
   SmallVector<SDValue, 8> MemOps;
 
   static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
                                           AArch64::X3, AArch64::X4, AArch64::X5,
                                           AArch64::X6, AArch64::X7 };
   static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
   unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
 
   unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
   int GPRIdx = 0;
   if (GPRSaveSize != 0) {
+    if (IsWin64)
+      GPRIdx = MFI.CreateFixedObject(GPRSaveSize, GPRSaveSize & 15, false);
+    else
       GPRIdx = MFI.CreateStackObject(GPRSaveSize, 8, false);
 
     SDValue FIN = DAG.getFrameIndex(GPRIdx, PtrVT);
 
     for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
       unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
       SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
       SDValue Store = DAG.getStore(
           Val.getValue(1), DL, Val, FIN,
+          IsWin64 ?
+          MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), GPRIdx, 8) :
           MachinePointerInfo::getStack(DAG.getMachineFunction(), i * 8));
       MemOps.push_back(Store);
       FIN =
           DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getConstant(8, DL, PtrVT));
     }
   }
   FuncInfo->setVarArgsGPRIndex(GPRIdx);
   FuncInfo->setVarArgsGPRSize(GPRSaveSize);
 
-  if (Subtarget->hasFPARMv8()) {
+  if (Subtarget->hasFPARMv8() &&
+      !Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
     static const MCPhysReg FPRArgRegs[] = {
         AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
         AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
     static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
     unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
 
     unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
     int FPRIdx = 0;
SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
   SDLoc DL(Op);
   SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(),
                                  getPointerTy(DAG.getDataLayout()));
   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
   return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
                       MachinePointerInfo(SV));
 }
 
+SDValue AArch64TargetLowering::LowerWin64_VASTART(SDValue Op,
+                                                  SelectionDAG &DAG) const {
+  AArch64FunctionInfo *FuncInfo =
+      DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
+
+  SDLoc DL(Op);
+  SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(),
+                                 getPointerTy(DAG.getDataLayout()));
+  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
+  return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
+                      MachinePointerInfo(SV));
+}
+
 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
                                                 SelectionDAG &DAG) const {
   // The layout of the va_list struct is specified in the AArch64 Procedure Call
   // Standard, section B.3.
   MachineFunction &MF = DAG.getMachineFunction();
   AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
   auto PtrVT = getPointerTy(DAG.getDataLayout());
   SDLoc DL(Op);
MemOps.push_back(DAG.getStore(
       Chain, DL, DAG.getConstant(-FPRSize, DL, MVT::i32), VROffsAddr,
       MachinePointerInfo(SV, 28), /* Alignment = */ 4));
 
   return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
 }
 
 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
                                             SelectionDAG &DAG) const {
+  MachineFunction &MF = DAG.getMachineFunction();
+
+  if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
+    return LowerWin64_VASTART(Op, DAG);
   return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
                                      : LowerAAPCS_VASTART(Op, DAG);
 }
 
 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
                                            SelectionDAG &DAG) const {
   // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
   // pointer.
bool AArch64TargetLowering::isIntDivCheap(EVT VT, AttributeList Attr) const {
   // sequence can be performed in vector form.
   bool OptSize =
       Attr.hasAttribute(AttributeList::FunctionIndex, Attribute::MinSize);
   return OptSize && !VT.isVector();
 }
 
 unsigned
 AArch64TargetLowering::getVaListSizeInBits(const DataLayout &DL) const {
-  if (Subtarget->isTargetDarwin())
+  if (Subtarget->isTargetDarwin() || Subtarget->isTargetWindows())
     return getPointerTy(DL).getSizeInBits();
 
   return 3 * getPointerTy(DL).getSizeInBits() + 2 * 32;
 }

lib/Target/AArch64/AArch64Subtarget.h

public:
   const char *getBZeroEntry() const;
 
   void overrideSchedPolicy(MachineSchedPolicy &Policy,
                            unsigned NumRegionInstrs) const override;
 
   bool enableEarlyIfConversion() const override;
 
   std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
+
+  bool isCallingConvWin64(CallingConv::ID CC) const {
+    switch (CC) {
+    case CallingConv::C:
+      return isTargetWindows();
+    case CallingConv::AArch64_Win64:
+      return true;
+    default:
+      return false;
+    }
+  }
 };
 } // End llvm namespace
 
 #endif