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Differential D32628

Rename ExpandISelPseudo->FinalizeISel, delay register reservation
ClosedPublic

Authored by arsenm on Apr 27 2017, 5:52 PM.

Details

Reviewers
MatzeB
bogner
qcolombet
Summary

This allows targets to make more decisions about reserved registers
after isel. For example, now it should be certain there are calls or
stack objects in the frame or not, which could have been introduced by
legalization.

Diff Detail

Event Timeline

MatzeB created this revision.Apr 27 2017, 5:52 PM
Herald added subscribers: mgorny, wdng, mcrosier. · View Herald TranscriptApr 27 2017, 5:52 PM
MatzeB added a parent revision: D32621: TargetLowering: Add finalizeLowering() function; NFC.Apr 27 2017, 5:52 PM
arsenm commandeered this revision.May 31 2019, 6:06 AM
arsenm edited reviewers, added: MatzeB; removed: arsenm.
Herald added a project: Restricted Project. · View Herald TranscriptMay 31 2019, 6:06 AM
Herald added subscribers: jfb, javed.absar. · View Herald Transcript
arsenm updated this revision to Diff 202422.May 31 2019, 6:07 AM

Rebase. Defer first verifier until after FinalizeISel

Herald added subscribers: jsji, arphaman, atanasyan and 5 others. · View Herald TranscriptMay 31 2019, 6:07 AM
arsenm added reviewers: bogner, qcolombet.May 31 2019, 6:07 AM
arsenm added a child revision: D62854: AMDGPU: Invert frame index offset interpretation.Jun 4 2019, 2:59 PM
arsenm added a comment.Jun 5 2019, 11:32 AM

ping

bogner added a comment.Jun 5 2019, 4:38 PM

So if I'm reading this right this just basically just delays TLI->finalizeLowering to the end of ExpandISelPseudos/FinalizeISel. Is there motivation to this other than it makes more logical sense to freeze registers as close to regalloc as possible?

Could you update the summary to explain what this is about?

arsenm edited the summary of this revision. (Show Details)Jun 6 2019, 6:49 AM
arsenm added a comment.Jun 18 2019, 12:58 PM

ping

bogner accepted this revision.Jun 18 2019, 3:57 PM
This revision is now accepted and ready to land.Jun 18 2019, 3:57 PM
arsenm closed this revision.Jun 18 2019, 5:22 PM

r363757

arsenm mentioned this in rG18bd821f0226: DAG: Remove redundant finalizeLowering call.Jul 8 2020, 3:48 PM
foad mentioned this in D110692: [AMDGPU] Enable machine verification after AMDGPUISelDAGToDAG.Sep 29 2021, 3:44 AM
foad mentioned this in rGf9b68304a22e: [AMDGPU] Enable machine verification after AMDGPUISelDAGToDAG.Sep 29 2021, 10:50 AM

Revision Contents

PathSize
include/
llvm/
CodeGen/
5 lines
2 lines
lib/
CodeGen/
2 lines
2 lines
FinalizeISel.cpp
ExpandISelPseudos.cpp
29 lines
2 lines
SelectionDAG/
2 lines
2 lines
13 lines
Target/
AMDGPU/
3 lines
X86/
2 lines
test/
CodeGen/
AArch64/
GlobalISel/
2 lines
2 lines
2 lines
2 lines
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AMDGPU/
2 lines
ARM/
GlobalISel/
4 lines
2 lines
Windows/
6 lines
2 lines
2 lines
Generic/
2 lines
Hexagon/
2 lines
MIR/
AArch64/
2 lines
AMDGPU/
2 lines
Generic/
12 lines
Mips/
6 lines
indirect-jump-hazard/
2 lines
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instverify/
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mirparser/
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PowerPC/
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SystemZ/
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X86/
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DebugInfo/
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Diff 202422

include/llvm/CodeGen/Passes.h

Show First 20 Lines • Show All 339 Lines • ▼ Show 20 Lines/// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
FunctionPass *createWasmEHPass(); FunctionPass *createWasmEHPass();
/// LocalStackSlotAllocation - This pass assigns local frame indices to stack /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
/// slots relative to one another and allocates base registers to access them /// slots relative to one another and allocates base registers to access them
/// when it is estimated by the target to be out of range of normal frame /// when it is estimated by the target to be out of range of normal frame
/// pointer or stack pointer index addressing. /// pointer or stack pointer index addressing.
extern char &LocalStackSlotAllocationID; extern char &LocalStackSlotAllocationID;
/// ExpandISelPseudos - This pass expands pseudo-instructions. /// This pass expands pseudo-instructions, reserves registers and adjusts
extern char &ExpandISelPseudosID; /// machine frame information.
extern char &FinalizeISelID;
/// UnpackMachineBundles - This pass unpack machine instruction bundles. /// UnpackMachineBundles - This pass unpack machine instruction bundles.
extern char &UnpackMachineBundlesID; extern char &UnpackMachineBundlesID;
FunctionPass * FunctionPass *
createUnpackMachineBundles(std::function<bool(const MachineFunction &)> Ftor); createUnpackMachineBundles(std::function<bool(const MachineFunction &)> Ftor);
/// FinalizeMachineBundles - This pass finalize machine instruction /// FinalizeMachineBundles - This pass finalize machine instruction
▲ Show 20 Lines • Show All 94 Lines • Show Last 20 Lines

include/llvm/InitializePasses.h

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
void initializeEarlyCSELegacyPassPass(PassRegistry&); void initializeEarlyCSELegacyPassPass(PassRegistry&);
void initializeEarlyCSEMemSSALegacyPassPass(PassRegistry&); void initializeEarlyCSEMemSSALegacyPassPass(PassRegistry&);
void initializeEarlyIfConverterPass(PassRegistry&); void initializeEarlyIfConverterPass(PassRegistry&);
void initializeEarlyMachineLICMPass(PassRegistry&); void initializeEarlyMachineLICMPass(PassRegistry&);
void initializeEarlyTailDuplicatePass(PassRegistry&); void initializeEarlyTailDuplicatePass(PassRegistry&);
void initializeEdgeBundlesPass(PassRegistry&); void initializeEdgeBundlesPass(PassRegistry&);
void initializeEliminateAvailableExternallyLegacyPassPass(PassRegistry&); void initializeEliminateAvailableExternallyLegacyPassPass(PassRegistry&);
void initializeEntryExitInstrumenterPass(PassRegistry&); void initializeEntryExitInstrumenterPass(PassRegistry&);
void initializeExpandISelPseudosPass(PassRegistry&);
void initializeExpandMemCmpPassPass(PassRegistry&); void initializeExpandMemCmpPassPass(PassRegistry&);
void initializeExpandPostRAPass(PassRegistry&); void initializeExpandPostRAPass(PassRegistry&);
void initializeExpandReductionsPass(PassRegistry&); void initializeExpandReductionsPass(PassRegistry&);
void initializeMakeGuardsExplicitLegacyPassPass(PassRegistry&); void initializeMakeGuardsExplicitLegacyPassPass(PassRegistry&);
void initializeExternalAAWrapperPassPass(PassRegistry&); void initializeExternalAAWrapperPassPass(PassRegistry&);
void initializeFEntryInserterPass(PassRegistry&); void initializeFEntryInserterPass(PassRegistry&);
void initializeFinalizeISelPass(PassRegistry&);
void initializeFinalizeMachineBundlesPass(PassRegistry&); void initializeFinalizeMachineBundlesPass(PassRegistry&);
void initializeFlattenCFGPassPass(PassRegistry&); void initializeFlattenCFGPassPass(PassRegistry&);
void initializeFloat2IntLegacyPassPass(PassRegistry&); void initializeFloat2IntLegacyPassPass(PassRegistry&);
void initializeForceFunctionAttrsLegacyPassPass(PassRegistry&); void initializeForceFunctionAttrsLegacyPassPass(PassRegistry&);
void initializeForwardControlFlowIntegrityPass(PassRegistry&); void initializeForwardControlFlowIntegrityPass(PassRegistry&);
void initializeFuncletLayoutPass(PassRegistry&); void initializeFuncletLayoutPass(PassRegistry&);
void initializeFunctionImportLegacyPassPass(PassRegistry&); void initializeFunctionImportLegacyPassPass(PassRegistry&);
void initializeGCMachineCodeAnalysisPass(PassRegistry&); void initializeGCMachineCodeAnalysisPass(PassRegistry&);
▲ Show 20 Lines • Show All 265 Lines • Show Last 20 Lines

lib/CodeGen/CMakeLists.txt

Show All 15 Linesadd_llvm_library(LLVMCodeGen
CriticalAntiDepBreaker.cpp CriticalAntiDepBreaker.cpp
DeadMachineInstructionElim.cpp DeadMachineInstructionElim.cpp
DetectDeadLanes.cpp DetectDeadLanes.cpp
DFAPacketizer.cpp DFAPacketizer.cpp
DwarfEHPrepare.cpp DwarfEHPrepare.cpp
EarlyIfConversion.cpp EarlyIfConversion.cpp
EdgeBundles.cpp EdgeBundles.cpp
ExecutionDomainFix.cpp ExecutionDomainFix.cpp
ExpandISelPseudos.cpp
ExpandMemCmp.cpp ExpandMemCmp.cpp
ExpandPostRAPseudos.cpp ExpandPostRAPseudos.cpp
ExpandReductions.cpp ExpandReductions.cpp
FaultMaps.cpp FaultMaps.cpp
FEntryInserter.cpp FEntryInserter.cpp
FinalizeISel.cpp
FuncletLayout.cpp FuncletLayout.cpp
GCMetadata.cpp GCMetadata.cpp
GCMetadataPrinter.cpp GCMetadataPrinter.cpp
GCRootLowering.cpp GCRootLowering.cpp
GCStrategy.cpp GCStrategy.cpp
GlobalMerge.cpp GlobalMerge.cpp
IfConversion.cpp IfConversion.cpp
ImplicitNullChecks.cpp ImplicitNullChecks.cpp
▲ Show 20 Lines • Show All 142 Lines • Show Last 20 Lines

lib/CodeGen/CodeGen.cpp

Show All 24 Linesvoid llvm::initializeCodeGen(PassRegistry &Registry) {
initializeCFIInstrInserterPass(Registry); initializeCFIInstrInserterPass(Registry);
initializeCodeGenPreparePass(Registry); initializeCodeGenPreparePass(Registry);
initializeDeadMachineInstructionElimPass(Registry); initializeDeadMachineInstructionElimPass(Registry);
initializeDetectDeadLanesPass(Registry); initializeDetectDeadLanesPass(Registry);
initializeDwarfEHPreparePass(Registry); initializeDwarfEHPreparePass(Registry);
initializeEarlyIfConverterPass(Registry); initializeEarlyIfConverterPass(Registry);
initializeEarlyMachineLICMPass(Registry); initializeEarlyMachineLICMPass(Registry);
initializeEarlyTailDuplicatePass(Registry); initializeEarlyTailDuplicatePass(Registry);
initializeExpandISelPseudosPass(Registry);
initializeExpandMemCmpPassPass(Registry); initializeExpandMemCmpPassPass(Registry);
initializeExpandPostRAPass(Registry); initializeExpandPostRAPass(Registry);
initializeFEntryInserterPass(Registry); initializeFEntryInserterPass(Registry);
initializeFinalizeISelPass(Registry);
initializeFinalizeMachineBundlesPass(Registry); initializeFinalizeMachineBundlesPass(Registry);
initializeFuncletLayoutPass(Registry); initializeFuncletLayoutPass(Registry);
initializeGCMachineCodeAnalysisPass(Registry); initializeGCMachineCodeAnalysisPass(Registry);
initializeGCModuleInfoPass(Registry); initializeGCModuleInfoPass(Registry);
initializeIfConverterPass(Registry); initializeIfConverterPass(Registry);
initializeImplicitNullChecksPass(Registry); initializeImplicitNullChecksPass(Registry);
initializeIndirectBrExpandPassPass(Registry); initializeIndirectBrExpandPassPass(Registry);
initializeInterleavedLoadCombinePass(Registry); initializeInterleavedLoadCombinePass(Registry);
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

lib/CodeGen/ExpandISelPseudos.cpp

  • This file was moved to lib/CodeGen/FinalizeISel.cpp.

lib/CodeGen/FinalizeISel.cpp

  • This file was moved from lib/CodeGen/ExpandISelPseudos.cpp.
//===-- llvm/CodeGen/ExpandISelPseudos.cpp ----------------------*- C++ -*-===// //===-- llvm/CodeGen/FinalizeISel.cpp ---------------------------*- C++ -*-===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Expand Pseudo-instructions produced by ISel. These are usually to allow /// This pass expands Pseudo-instructions produced by ISel, fixes register
// the expansion to contain control flow, such as a conditional move /// reservations and may do machine frame information adjustments.
// implemented with a conditional branch and a phi, or an atomic operation /// The pseudo instructions are used to allow the expansion to contain control
// implemented with a loop. /// flow, such as a conditional move implemented with a conditional branch and a
/// phi, or an atomic operation implemented with a loop.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "expand-isel-pseudos" #define DEBUG_TYPE "finalize-isel"
namespace { namespace {
class ExpandISelPseudos : public MachineFunctionPass { class FinalizeISel : public MachineFunctionPass {
public: public:
static char ID; // Pass identification, replacement for typeid static char ID; // Pass identification, replacement for typeid
ExpandISelPseudos() : MachineFunctionPass(ID) {} FinalizeISel() : MachineFunctionPass(ID) {}
private: private:
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
void getAnalysisUsage(AnalysisUsage &AU) const override { void getAnalysisUsage(AnalysisUsage &AU) const override {
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
}; };
} // end anonymous namespace } // end anonymous namespace
char ExpandISelPseudos::ID = 0; char FinalizeISel::ID = 0;
char &llvm::ExpandISelPseudosID = ExpandISelPseudos::ID; char &llvm::FinalizeISelID = FinalizeISel::ID;
INITIALIZE_PASS(ExpandISelPseudos, DEBUG_TYPE, INITIALIZE_PASS(FinalizeISel, DEBUG_TYPE,
"Expand ISel Pseudo-instructions", false, false) "Finalize ISel and expand pseudo-instructions", false, false)
bool ExpandISelPseudos::runOnMachineFunction(MachineFunction &MF) { bool FinalizeISel::runOnMachineFunction(MachineFunction &MF) {
bool Changed = false; bool Changed = false;
const TargetLowering *TLI = MF.getSubtarget().getTargetLowering(); const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
// Iterate through each instruction in the function, looking for pseudos. // Iterate through each instruction in the function, looking for pseudos.
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) { for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
MachineBasicBlock *MBB = &*I; MachineBasicBlock *MBB = &*I;
for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end(); for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end();
MBBI != MBBE; ) { MBBI != MBBE; ) {
Show All 9 Lines for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end();
I = NewMBB->getIterator(); I = NewMBB->getIterator();
MBBI = NewMBB->begin(); MBBI = NewMBB->begin();
MBBE = NewMBB->end(); MBBE = NewMBB->end();
} }
} }
} }
} }
TLI->finalizeLowering(MF);
return Changed; return Changed;
} }

lib/CodeGen/MachineVerifier.cpp

Show First 20 Lines • Show All 212 Lines • ▼ Show 20 Lines struct MachineVerifier {
DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap; DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
bool isReserved(unsigned Reg) { bool isReserved(unsigned Reg) {
return Reg < regsReserved.size() && regsReserved.test(Reg); return Reg < regsReserved.size() && regsReserved.test(Reg);
} }
bool isAllocatable(unsigned Reg) const { bool isAllocatable(unsigned Reg) const {
return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) && return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
!regsReserved.test(Reg); !regsReserved.test(Reg);
} }
// Analysis information if available // Analysis information if available
LiveVariables *LiveVars; LiveVariables *LiveVars;
LiveIntervals *LiveInts; LiveIntervals *LiveInts;
LiveStacks *LiveStks; LiveStacks *LiveStks;
SlotIndexes *Indexes; SlotIndexes *Indexes;
▲ Show 20 Lines • Show All 2,453 Lines • Show Last 20 Lines

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 8,554 Lines • ▼ Show 20 Lines
/// Add a stack map intrinsic call's live variable operands to a stackmap /// Add a stack map intrinsic call's live variable operands to a stackmap
/// or patchpoint target node's operand list. /// or patchpoint target node's operand list.
/// ///
/// Constants are converted to TargetConstants purely as an optimization to /// Constants are converted to TargetConstants purely as an optimization to
/// avoid constant materialization and register allocation. /// avoid constant materialization and register allocation.
/// ///
/// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
/// generate addess computation nodes, and so ExpandISelPseudo can convert the /// generate addess computation nodes, and so FinalizeISel can convert the
/// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
/// address materialization and register allocation, but may also be required /// address materialization and register allocation, but may also be required
/// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
/// alloca in the entry block, then the runtime may assume that the alloca's /// alloca in the entry block, then the runtime may assume that the alloca's
/// StackMap location can be read immediately after compilation and that the /// StackMap location can be read immediately after compilation and that the
/// location is valid at any point during execution (this is similar to the /// location is valid at any point during execution (this is similar to the
/// assumption made by the llvm.gcroot intrinsic). If the alloca's location were /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
/// only available in a register, then the runtime would need to trap when /// only available in a register, then the runtime would need to trap when
▲ Show 20 Lines • Show All 2,345 Lines • Show Last 20 Lines

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Show First 20 Lines • Show All 646 Lines • ▼ Show 20 Lines for (DenseMap<unsigned, unsigned>::iterator
// Replacing one register with another won't touch the kill flags. // Replacing one register with another won't touch the kill flags.
// We need to conservatively clear the kill flags as a kill on the old // We need to conservatively clear the kill flags as a kill on the old
// register might dominate existing uses of the new register. // register might dominate existing uses of the new register.
if (!MRI.use_empty(To)) if (!MRI.use_empty(To))
MRI.clearKillFlags(From); MRI.clearKillFlags(From);
MRI.replaceRegWith(From, To); MRI.replaceRegWith(From, To);
} }
TLI->finalizeLowering(*MF);
// Release function-specific state. SDB and CurDAG are already cleared // Release function-specific state. SDB and CurDAG are already cleared
// at this point. // at this point.
FuncInfo->clear(); FuncInfo->clear();
LLVM_DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n"); LLVM_DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
LLVM_DEBUG(MF->print(dbgs())); LLVM_DEBUG(MF->print(dbgs()));
return true; return true;
▲ Show 20 Lines • Show All 2,969 Lines • Show Last 20 Lines

lib/CodeGen/TargetPassConfig.cpp

Show First 20 Lines • Show All 809 Lines • ▼ Show 20 Lines if (Selector == SelectorType::GlobalISel) {
// Provide a fallback path when we do not want to abort on // Provide a fallback path when we do not want to abort on
// not-yet-supported input. // not-yet-supported input.
if (!isGlobalISelAbortEnabled() && addInstSelector()) if (!isGlobalISelAbortEnabled() && addInstSelector())
return true; return true;
} else if (addInstSelector()) } else if (addInstSelector())
return true; return true;
// Expand pseudo-instructions emitted by ISel. Don't run the verifier before
// FinalizeISel.
addPass(&FinalizeISelID);
// Print the instruction selected machine code...
printAndVerify("After Instruction Selection");
return false; return false;
} }
bool TargetPassConfig::addISelPasses() { bool TargetPassConfig::addISelPasses() {
if (TM->useEmulatedTLS()) if (TM->useEmulatedTLS())
addPass(createLowerEmuTLSPass()); addPass(createLowerEmuTLSPass());
addPass(createPreISelIntrinsicLoweringPass()); addPass(createPreISelIntrinsicLoweringPass());
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines if (const PassInfo *TPI = getPassInfo(PrintMachineInstrsPassName)) {
const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer")); const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
assert(IPI && "failed to get \"machineinstr-printer\" PassInfo!"); assert(IPI && "failed to get \"machineinstr-printer\" PassInfo!");
const char *TID = (const char *)(TPI->getTypeInfo()); const char *TID = (const char *)(TPI->getTypeInfo());
const char *IID = (const char *)(IPI->getTypeInfo()); const char *IID = (const char *)(IPI->getTypeInfo());
insertPass(TID, IID); insertPass(TID, IID);
} }
} }
// Print the instruction selected machine code...
printAndVerify("After Instruction Selection");
// Expand pseudo-instructions emitted by ISel.
addPass(&ExpandISelPseudosID);
// Add passes that optimize machine instructions in SSA form. // Add passes that optimize machine instructions in SSA form.
if (getOptLevel() != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
addMachineSSAOptimization(); addMachineSSAOptimization();
} else { } else {
// If the target requests it, assign local variables to stack slots relative // If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible. // to one another and simplify frame index references where possible.
addPass(&LocalStackSlotAllocationID, false); addPass(&LocalStackSlotAllocationID, false);
} }
▲ Show 20 Lines • Show All 344 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Show First 20 Lines • Show All 738 Lines • ▼ Show 20 Lines
bool AMDGPUPassConfig::addPreISel() { bool AMDGPUPassConfig::addPreISel() {
addPass(createLowerSwitchPass()); addPass(createLowerSwitchPass());
addPass(createFlattenCFGPass()); addPass(createFlattenCFGPass());
return false; return false;
} }
bool AMDGPUPassConfig::addInstSelector() { bool AMDGPUPassConfig::addInstSelector() {
addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel())); // Defer the verifier until FinalizeISel.
addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
return false; return false;
} }
bool AMDGPUPassConfig::addGCPasses() { bool AMDGPUPassConfig::addGCPasses() {
// Do nothing. GC is not supported. // Do nothing. GC is not supported.
return false; return false;
} }
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lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 23,242 Lines • ▼ Show 20 Lines if (!IntrData) {
case llvm::Intrinsic::x86_flags_read_u64: case llvm::Intrinsic::x86_flags_read_u64:
case llvm::Intrinsic::x86_flags_write_u32: case llvm::Intrinsic::x86_flags_write_u32:
case llvm::Intrinsic::x86_flags_write_u64: { case llvm::Intrinsic::x86_flags_write_u64: {
// We need a frame pointer because this will get lowered to a PUSH/POP // We need a frame pointer because this will get lowered to a PUSH/POP
// sequence. // sequence.
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
MFI.setHasCopyImplyingStackAdjustment(true); MFI.setHasCopyImplyingStackAdjustment(true);
// Don't do anything here, we will expand these intrinsics out later // Don't do anything here, we will expand these intrinsics out later
// during ExpandISelPseudos in EmitInstrWithCustomInserter. // during FinalizeISel in EmitInstrWithCustomInserter.
return SDValue(); return SDValue();
} }
case Intrinsic::x86_lwpins32: case Intrinsic::x86_lwpins32:
case Intrinsic::x86_lwpins64: case Intrinsic::x86_lwpins64:
case Intrinsic::x86_umwait: case Intrinsic::x86_umwait:
case Intrinsic::x86_tpause: { case Intrinsic::x86_tpause: {
SDLoc dl(Op); SDLoc dl(Op);
SDValue Chain = Op->getOperand(0); SDValue Chain = Op->getOperand(0);
▲ Show 20 Lines • Show All 21,392 Lines • Show Last 20 Lines

test/CodeGen/AArch64/GlobalISel/gisel-commandline-option-fastisel.ll

Show All 19 Lines
; Check that the right instruction selector is chosen when using ; Check that the right instruction selector is chosen when using
; -global-isel=false. FastISel should be used at -O0 (unless -fast-isel=false is ; -global-isel=false. FastISel should be used at -O0 (unless -fast-isel=false is
; also present) and SelectionDAG otherwise. ; also present) and SelectionDAG otherwise.
; DISABLED-NOT: IRTranslator ; DISABLED-NOT: IRTranslator
; DISABLED: AArch64 Instruction Selection ; DISABLED: AArch64 Instruction Selection
; DISABLED: Expand ISel Pseudo-instructions ; DISABLED: Finalize ISel and expand pseudo-instructions
; FASTISEL: Enabling fast-isel ; FASTISEL: Enabling fast-isel
; NOFASTISEL-NOT: Enabling fast-isel ; NOFASTISEL-NOT: Enabling fast-isel
define void @empty() { define void @empty() {
ret void ret void
} }

test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; ENABLED-NEXT: ResetMachineFunction ; ENABLED-NEXT: ResetMachineFunction
; FALLBACK: AArch64 Instruction Selection ; FALLBACK: AArch64 Instruction Selection
; NOFALLBACK-NOT: AArch64 Instruction Selection ; NOFALLBACK-NOT: AArch64 Instruction Selection
; DISABLED-NOT: IRTranslator ; DISABLED-NOT: IRTranslator
; DISABLED: AArch64 Instruction Selection ; DISABLED: AArch64 Instruction Selection
; DISABLED: Expand ISel Pseudo-instructions ; DISABLED: Finalize ISel and expand pseudo-instructions
define void @empty() { define void @empty() {
ret void ret void
} }

test/CodeGen/AArch64/O0-pipeline.ll

Show All 36 Lines
; CHECK-NEXT: AArch64PreLegalizerCombiner ; CHECK-NEXT: AArch64PreLegalizerCombiner
; CHECK-NEXT: Analysis containing CSE Info ; CHECK-NEXT: Analysis containing CSE Info
; CHECK-NEXT: Legalizer ; CHECK-NEXT: Legalizer
; CHECK-NEXT: RegBankSelect ; CHECK-NEXT: RegBankSelect
; CHECK-NEXT: Localizer ; CHECK-NEXT: Localizer
; CHECK-NEXT: InstructionSelect ; CHECK-NEXT: InstructionSelect
; CHECK-NEXT: ResetMachineFunction ; CHECK-NEXT: ResetMachineFunction
; CHECK-NEXT: AArch64 Instruction Selection ; CHECK-NEXT: AArch64 Instruction Selection
; CHECK-NEXT: Expand ISel Pseudo-instructions ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
; CHECK-NEXT: Local Stack Slot Allocation ; CHECK-NEXT: Local Stack Slot Allocation
; CHECK-NEXT: Eliminate PHI nodes for register allocation ; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Two-Address instruction pass ; CHECK-NEXT: Two-Address instruction pass
; CHECK-NEXT: Fast Register Allocator ; CHECK-NEXT: Fast Register Allocator
; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter ; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization ; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
; CHECK-NEXT: Post-RA pseudo instruction expansion pass ; CHECK-NEXT: Post-RA pseudo instruction expansion pass
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test/CodeGen/AArch64/O3-pipeline.ll

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; CHECK-NEXT: Dominator Tree Construction ; CHECK-NEXT: Dominator Tree Construction
; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Function Alias Analysis Results
; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: Natural Loop Information
; CHECK-NEXT: Branch Probability Analysis ; CHECK-NEXT: Branch Probability Analysis
; CHECK-NEXT: AArch64 Instruction Selection ; CHECK-NEXT: AArch64 Instruction Selection
; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: AArch64 Local Dynamic TLS Access Clean-up ; CHECK-NEXT: AArch64 Local Dynamic TLS Access Clean-up
; CHECK-NEXT: Expand ISel Pseudo-instructions ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
; CHECK-NEXT: Early Tail Duplication ; CHECK-NEXT: Early Tail Duplication
; CHECK-NEXT: Optimize machine instruction PHIs ; CHECK-NEXT: Optimize machine instruction PHIs
; CHECK-NEXT: Slot index numbering ; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Merge disjoint stack slots ; CHECK-NEXT: Merge disjoint stack slots
; CHECK-NEXT: Local Stack Slot Allocation ; CHECK-NEXT: Local Stack Slot Allocation
; CHECK-NEXT: Remove dead machine instructions ; CHECK-NEXT: Remove dead machine instructions
; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: AArch64 Condition Optimizer ; CHECK-NEXT: AArch64 Condition Optimizer
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test/CodeGen/AArch64/apple-latest-cpu.ll

; RUN: llc -mtriple=arm64-apple-ios -mcpu=apple-latest -stop-before=expand-isel-pseudos -o - 2>&1 < %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-ios -mcpu=apple-latest -stop-before=finalize-isel -o - 2>&1 < %s | FileCheck %s
; CHECK-LABEL: @dummy ; CHECK-LABEL: @dummy
; CHECK: "target-cpu"="apple-latest" ; CHECK: "target-cpu"="apple-latest"
define void @dummy() { define void @dummy() {
ret void ret void
} }

test/CodeGen/AArch64/arm64-fast-isel-rem.ll

; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
; RUN: llc %s -O0 -fast-isel -fast-isel-abort=1 -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t ; RUN: llc %s -O0 -fast-isel -fast-isel-abort=1 -mtriple=arm64-apple-darwin -print-after=finalize-isel -o /dev/null 2> %t
; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA ; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA
; CHECK-SSA-LABEL: Machine code for function t1 ; CHECK-SSA-LABEL: Machine code for function t1
; CHECK-SSA: [[QUOTREG:%[0-9]+]]:gpr32 = SDIVWr ; CHECK-SSA: [[QUOTREG:%[0-9]+]]:gpr32 = SDIVWr
; CHECK-SSA-NOT: [[QUOTREG]] = ; CHECK-SSA-NOT: [[QUOTREG]] =
; CHECK-SSA: {{%[0-9]+}}:gpr32 = MSUBWrrr killed [[QUOTREG]] ; CHECK-SSA: {{%[0-9]+}}:gpr32 = MSUBWrrr killed [[QUOTREG]]
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test/CodeGen/AArch64/fast-isel-dbg.ll

; RUN: llc -o - %s -fast-isel -stop-before=expand-isel-pseudos | FileCheck %s ; RUN: llc -o - %s -fast-isel -stop-before=finalize-isel | FileCheck %s
; Make sure fast-isel produces DBG_VALUE instructions even if no debug printer ; Make sure fast-isel produces DBG_VALUE instructions even if no debug printer
; is scheduled because of -stop-before. ; is scheduled because of -stop-before.
target triple="aarch64--" target triple="aarch64--"
; CHECK-LABEL: name: func ; CHECK-LABEL: name: func
; CHECK: DBG_VALUE ; CHECK: DBG_VALUE
define void @func(i32 %a) !dbg !4 { define void @func(i32 %a) !dbg !4 {
call void @llvm.dbg.declare(metadata i32 %a, metadata !5, metadata !DIExpression()), !dbg !7 call void @llvm.dbg.declare(metadata i32 %a, metadata !5, metadata !DIExpression()), !dbg !7
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test/CodeGen/AArch64/tail-call-unused-zext.ll

; RUN: llc -mtriple=arm64--- -stop-after=expand-isel-pseudos -o - %s | FileCheck %s ; RUN: llc -mtriple=arm64--- -stop-after=finalize-isel -o - %s | FileCheck %s
; Check that we ignore the zeroext attribute on the return type of the tail ; Check that we ignore the zeroext attribute on the return type of the tail
; call, since the return value is unused. This happens during CodeGenPrepare in ; call, since the return value is unused. This happens during CodeGenPrepare in
; dupRetToEnableTailCallOpts, which calls attributesPermitTailCall to check if ; dupRetToEnableTailCallOpts, which calls attributesPermitTailCall to check if
; the attributes of the caller and the callee match. ; the attributes of the caller and the callee match.
declare zeroext i1 @zcallee() declare zeroext i1 @zcallee()
define void @zcaller() { define void @zcaller() {
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test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll

; RUN: llc -o - %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after expand-isel-pseudos | FileCheck %s ; RUN: llc -o - %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after finalize-isel | FileCheck %s
; This test verifies that the instruction selection will add the implicit ; This test verifies that the instruction selection will add the implicit
; register operands in the correct order when modifying the opcode of an ; register operands in the correct order when modifying the opcode of an
; instruction to V_ADD_I32_e32. ; instruction to V_ADD_I32_e32.
; CHECK: %{{[0-9]+}}:vgpr_32 = V_ADD_I32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def $vcc, implicit $exec ; CHECK: %{{[0-9]+}}:vgpr_32 = V_ADD_I32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def $vcc, implicit $exec
define amdgpu_kernel void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { define amdgpu_kernel void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
entry: entry:
%b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
%a = load volatile i32, i32 addrspace(1)* %in %a = load volatile i32, i32 addrspace(1)* %in
%b = load volatile i32, i32 addrspace(1)* %b_ptr %b = load volatile i32, i32 addrspace(1)* %b_ptr
%result = add i32 %a, %b %result = add i32 %a, %b
store i32 %result, i32 addrspace(1)* %out store i32 %result, i32 addrspace(1)* %out
ret void ret void
} }

test/CodeGen/ARM/GlobalISel/pr35375.ll

; RUN: llc -O0 -mtriple armv7-- -stop-before=expand-isel-pseudos < %s ; RUN: llc -O0 -mtriple armv7-- -stop-before=finalize-isel < %s
; RUN: llc -O0 -mtriple armv7-- -stop-before=expand-isel-pseudos -global-isel < %s ; RUN: llc -O0 -mtriple armv7-- -stop-before=finalize-isel -global-isel < %s
; CHECK: PKHBT ; CHECK: PKHBT
define arm_aapcscc i32 @pkh(i32 %x, i32 %y) { define arm_aapcscc i32 @pkh(i32 %x, i32 %y) {
%andx = and i32 %x, 65535 %andx = and i32 %x, 65535
%shl = shl i32 %y, 1 %shl = shl i32 %y, 1
%andy = and i32 %shl, 4294901760 ; same as -65536 %andy = and i32 %shl, 4294901760 ; same as -65536
%or = or i32 %andx, %andy %or = or i32 %andx, %andy
ret i32 %or ret i32 %or
} }

test/CodeGen/ARM/O3-pipeline.ll

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; CHECK-NEXT: Insert stack protectors ; CHECK-NEXT: Insert stack protectors
; CHECK-NEXT: Module Verifier ; CHECK-NEXT: Module Verifier
; CHECK-NEXT: Dominator Tree Construction ; CHECK-NEXT: Dominator Tree Construction
; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Function Alias Analysis Results
; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: Natural Loop Information
; CHECK-NEXT: Branch Probability Analysis ; CHECK-NEXT: Branch Probability Analysis
; CHECK-NEXT: ARM Instruction Selection ; CHECK-NEXT: ARM Instruction Selection
; CHECK-NEXT: Expand ISel Pseudo-instructions ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
; CHECK-NEXT: Early Tail Duplication ; CHECK-NEXT: Early Tail Duplication
; CHECK-NEXT: Optimize machine instruction PHIs ; CHECK-NEXT: Optimize machine instruction PHIs
; CHECK-NEXT: Slot index numbering ; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Merge disjoint stack slots ; CHECK-NEXT: Merge disjoint stack slots
; CHECK-NEXT: Local Stack Slot Allocation ; CHECK-NEXT: Local Stack Slot Allocation
; CHECK-NEXT: Remove dead machine instructions ; CHECK-NEXT: Remove dead machine instructions
; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Machine Natural Loop Construction ; CHECK-NEXT: Machine Natural Loop Construction
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test/CodeGen/ARM/Windows/dbzchk.ll

; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-DIV ; RUN: llc -mtriple thumbv7--windows-itanium -print-after=finalize-isel -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-DIV
; int f(int n, int d) { ; int f(int n, int d) {
; if (n / d) ; if (n / d)
; return 1; ; return 1;
; return 0; ; return 0;
; } ; }
define arm_aapcs_vfpcc i32 @f(i32 %n, i32 %d) { define arm_aapcs_vfpcc i32 @f(i32 %n, i32 %d) {
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; CHECK-DIV-DAG: %bb.0 ; CHECK-DIV-DAG: %bb.0
; CHECK-DIV-DAG: successors: %bb.1({{.*}}), %bb.2 ; CHECK-DIV-DAG: successors: %bb.1({{.*}}), %bb.2
; CHECK-DIV-DAG: %bb.1 ; CHECK-DIV-DAG: %bb.1
; CHECK-DIV-DAG: successors: %bb.3 ; CHECK-DIV-DAG: successors: %bb.3
; CHECK-DIV-DAG: %bb.2 ; CHECK-DIV-DAG: %bb.2
; CHECK-DIV-DAG: successors: %bb.3 ; CHECK-DIV-DAG: successors: %bb.3
; CHECK-DIV-DAG: %bb.3 ; CHECK-DIV-DAG: %bb.3
; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD ; RUN: llc -mtriple thumbv7--windows-itanium -print-after=finalize-isel -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD
; int r; ; int r;
; int g(int l, int m) { ; int g(int l, int m) {
; if (m <= 0) ; if (m <= 0)
; return 0; ; return 0;
; return (r = l % m); ; return (r = l % m);
; } ; }
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; CHECK-MOD-DAG: %bb.0 ; CHECK-MOD-DAG: %bb.0
; CHECK-MOD-DAG: successors: %bb.2({{.*}}), %bb.1 ; CHECK-MOD-DAG: successors: %bb.2({{.*}}), %bb.1
; CHECK-MOD-DAG: %bb.1 ; CHECK-MOD-DAG: %bb.1
; CHECK-MOD-DAG: successors: %bb.3 ; CHECK-MOD-DAG: successors: %bb.3
; CHECK-MOD-DAG: %bb.3 ; CHECK-MOD-DAG: %bb.3
; CHECK-MOD-DAG: successors: %bb.2 ; CHECK-MOD-DAG: successors: %bb.2
; CHECK-MOD-DAG: %bb.2 ; CHECK-MOD-DAG: %bb.2
; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG ; RUN: llc -mtriple thumbv7--windows-itanium -print-after=finalize-isel -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG
; RUN: llc -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-CFG-ASM ; RUN: llc -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-CFG-ASM
; unsigned c; ; unsigned c;
; extern unsigned long g(void); ; extern unsigned long g(void);
; int f(unsigned u, signed char b) { ; int f(unsigned u, signed char b) {
; if (b) ; if (b)
; c = g() % u; ; c = g() % u;
; return c; ; return c;
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test/CodeGen/ARM/Windows/vla-cpsr.ll

; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o /dev/null %s -print-machineinstrs=expand-isel-pseudos 2>&1 | FileCheck %s ; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o /dev/null %s -print-after=finalize-isel 2>&1 | FileCheck %s
declare arm_aapcs_vfpcc void @g(i8*) local_unnamed_addr declare arm_aapcs_vfpcc void @g(i8*) local_unnamed_addr
define arm_aapcs_vfpcc void @f(i32 %i) local_unnamed_addr { define arm_aapcs_vfpcc void @f(i32 %i) local_unnamed_addr {
entry: entry:
%vla = alloca i8, i32 %i, align 1 %vla = alloca i8, i32 %i, align 1
call arm_aapcs_vfpcc void @g(i8* nonnull %vla) call arm_aapcs_vfpcc void @g(i8* nonnull %vla)
ret void ret void
} }
; CHECK: tBL 14, $noreg, &__chkstk, implicit-def $lr, implicit $sp, implicit killed $r4, implicit-def $r4, implicit-def dead $r12, implicit-def dead $cpsr ; CHECK: tBL 14, $noreg, &__chkstk, implicit-def $lr, implicit $sp, implicit killed $r4, implicit-def $r4, implicit-def dead $r12, implicit-def dead $cpsr

test/CodeGen/ARM/copy-by-struct-i32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=armv7-unknown-linux < %s -stop-before=expand-isel-pseudos | FileCheck --check-prefix=BEFORE-EXPAND %s ; RUN: llc -mtriple=armv7-unknown-linux < %s -stop-before=finalize-isel | FileCheck --check-prefix=BEFORE-EXPAND %s
; RUN: llc -mtriple=armv7-unknown-linux < %s | FileCheck --check-prefix=ASSEMBLY %s ; RUN: llc -mtriple=armv7-unknown-linux < %s | FileCheck --check-prefix=ASSEMBLY %s
; Check COPY_STRUCT_BYVAL_I32 has CPSR as operand. ; Check COPY_STRUCT_BYVAL_I32 has CPSR as operand.
; BEFORE-EXPAND: COPY_STRUCT_BYVAL_I32 {{.*}} implicit-def dead $cpsr ; BEFORE-EXPAND: COPY_STRUCT_BYVAL_I32 {{.*}} implicit-def dead $cpsr
; BEFORE-EXPAND: COPY_STRUCT_BYVAL_I32 {{.*}} implicit-def dead $cpsr ; BEFORE-EXPAND: COPY_STRUCT_BYVAL_I32 {{.*}} implicit-def dead $cpsr
%struct.anon = type { i32, i32, i32, i32, i32, i32, i32, %struct.f, i32, i64, i32 } %struct.anon = type { i32, i32, i32, i32, i32, i32, i32, %struct.f, i32, i64, i32 }
%struct.f = type { i32, i32, i32, i32, i32 } %struct.f = type { i32, i32, i32, i32, i32 }
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test/CodeGen/Generic/MachineBranchProb.ll

; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s ; RUN: llc < %s -print-after=finalize-isel -o /dev/null 2>&1 | FileCheck %s
; Hexagon runs passes that renumber the basic blocks, causing this test ; Hexagon runs passes that renumber the basic blocks, causing this test
; to fail. ; to fail.
; XFAIL: hexagon ; XFAIL: hexagon
declare void @foo() declare void @foo()
; Make sure we have the correct weight attached to each successor. ; Make sure we have the correct weight attached to each successor.
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test/CodeGen/Hexagon/call-v4.ll

; RUN: llc -march=hexagon -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 < %s | FileCheck %s ; RUN: llc -march=hexagon -print-after=finalize-isel -o /dev/null 2>&1 < %s | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
; CHECK: J2_call @f1 ; CHECK: J2_call @f1
; CHECK: PS_call_nr @f2 ; CHECK: PS_call_nr @f2
target triple = "hexagon" target triple = "hexagon"
@g0 = external global i32 @g0 = external global i32
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test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir

# RUN: llc -mtriple aarch64-- -run-pass instruction-select -simplify-mir \ # RUN: llc -mtriple aarch64-- -run-pass instruction-select -simplify-mir \
# RUN: -verify-machineinstrs %s -o - | FileCheck %s # RUN: -verify-machineinstrs %s -o - | FileCheck %s
# #
# RUN: llc -mtriple aarch64-- -global-isel=true -global-isel-abort=2 \ # RUN: llc -mtriple aarch64-- -global-isel=true -global-isel-abort=2 \
# RUN: -start-after=regbankselect -stop-before=expand-isel-pseudos \ # RUN: -start-after=regbankselect -stop-before=finalize-isel \
# RUN: -simplify-mir -verify-machineinstrs %s -o - 2>&1 \ # RUN: -simplify-mir -verify-machineinstrs %s -o - 2>&1 \
# RUN: | FileCheck %s --check-prefix=FALLBACK # RUN: | FileCheck %s --check-prefix=FALLBACK
# Test that: # Test that:
# 1) MIRParser can deserialize FailedISel property. # 1) MIRParser can deserialize FailedISel property.
# 2) Machine Verifier respects FailedISel and doesn't complain needlessly. # 2) Machine Verifier respects FailedISel and doesn't complain needlessly.
# 3) MIRPrinter is able to print FailedISel MIR after InstructionSelect pass. # 3) MIRPrinter is able to print FailedISel MIR after InstructionSelect pass.
# 4) MIRPrinter can serialize FailedISel property. # 4) MIRPrinter can serialize FailedISel property.
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test/CodeGen/MIR/AMDGPU/machine-function-info.ll

; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after expand-isel-pseudos -o %t.mir %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after finalize-isel -o %t.mir %s
; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s ; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s
; Test that SIMachineFunctionInfo can be round trip serialized through ; Test that SIMachineFunctionInfo can be round trip serialized through
; MIR. ; MIR.
@lds = addrspace(3) global [512 x float] undef, align 4 @lds = addrspace(3) global [512 x float] undef, align 4
; CHECK-LABEL: {{^}}name: kernel ; CHECK-LABEL: {{^}}name: kernel
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test/CodeGen/MIR/Generic/multiRunPass.mir

# RUN: llc -run-pass expand-isel-pseudos -run-pass peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE # RUN: llc -run-pass finalize-isel -run-pass peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE
# RUN: llc -run-pass expand-isel-pseudos,peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE # RUN: llc -run-pass finalize-isel,peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE
# RUN: llc -run-pass peephole-opt -run-pass expand-isel-pseudos -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO # RUN: llc -run-pass peephole-opt -run-pass finalize-isel -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO
# RUN: llc -run-pass peephole-opt,expand-isel-pseudos -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO # RUN: llc -run-pass peephole-opt,finalize-isel -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO
# REQUIRES: asserts # REQUIRES: asserts
# This test ensures that the command line accepts # This test ensures that the command line accepts
# several run passes on the same command line and # several run passes on the same command line and
# actually create the proper pipeline for it. # actually create the proper pipeline for it.
# PSEUDO_PEEPHOLE: -expand-isel-pseudos # PSEUDO_PEEPHOLE: -finalize-isel
# PSEUDO_PEEPHOLE-SAME: {{(-machineverifier )?}}-peephole-opt # PSEUDO_PEEPHOLE-SAME: {{(-machineverifier )?}}-peephole-opt
# PEEPHOLE_PSEUDO: -peephole-opt {{(-machineverifier )?}}-expand-isel-pseudos # PEEPHOLE_PSEUDO: -peephole-opt {{(-machineverifier )?}}-finalize-isel
# Make sure there are no other passes happening after what we asked. # Make sure there are no other passes happening after what we asked.
# CHECK-NEXT: --- | # CHECK-NEXT: --- |
--- ---
# CHECK: name: foo # CHECK: name: foo
name: foo name: foo
body: | body: |
bb.0: bb.0:
... ...

test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll

; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \ ; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \
; RUN: -mcpu=mips32 -mattr=+fpxx \ ; RUN: -mcpu=mips32 -mattr=+fpxx \
; RUN: -stop-after=expand-isel-pseudos | \ ; RUN: -stop-after=finalize-isel | \
; RUN: FileCheck %s -check-prefix=FPXX-IMPLICIT-SP ; RUN: FileCheck %s -check-prefix=FPXX-IMPLICIT-SP
; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \ ; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \
; RUN: -mcpu=mips32r6 -mattr=+fp64,+nooddspreg \ ; RUN: -mcpu=mips32r6 -mattr=+fp64,+nooddspreg \
; RUN: -stop-after=expand-isel-pseudos | \ ; RUN: -stop-after=finalize-isel | \
; RUN: FileCheck %s -check-prefix=FP64-IMPLICIT-SP ; RUN: FileCheck %s -check-prefix=FP64-IMPLICIT-SP
; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \ ; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \
; RUN: -mcpu=mips32r2 -mattr=+fpxx \ ; RUN: -mcpu=mips32r2 -mattr=+fpxx \
; RUN: -stop-after=expand-isel-pseudos | \ ; RUN: -stop-after=finalize-isel | \
; RUN: FileCheck %s -check-prefix=NO-IMPLICIT-SP ; RUN: FileCheck %s -check-prefix=NO-IMPLICIT-SP
define double @foo2(i32 signext %v1, double %d1) { define double @foo2(i32 signext %v1, double %d1) {
entry: entry:
; FPXX-IMPLICIT-SP: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp ; FPXX-IMPLICIT-SP: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp
; FPXX-IMPLICIT-SP: ExtractElementF64 killed %{{[0-9]+}}, 1, implicit $sp ; FPXX-IMPLICIT-SP: ExtractElementF64 killed %{{[0-9]+}}, 1, implicit $sp
; FP64-IMPLICIT-SP: BuildPairF64_64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp ; FP64-IMPLICIT-SP: BuildPairF64_64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp
; FP64-IMPLICIT-SP: ExtractElementF64_64 killed %{{[0-9]+}}, 1, implicit $sp ; FP64-IMPLICIT-SP: ExtractElementF64_64 killed %{{[0-9]+}}, 1, implicit $sp
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test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir

# RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \ # RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \
# RUN: -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \ # RUN: -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \
# RUN: | FileCheck %s # RUN: | FileCheck %s
# Test that calls are checked when using indirect jumps guards (hazard variant). # Test that calls are checked when using indirect jumps guards (hazard variant).
# CHECK: Bad machine code: invalid instruction when using jump guards! # CHECK: Bad machine code: invalid instruction when using jump guards!
--- | --- |
define i32 @fooTail(i32 (i32)* nocapture %f1) { define i32 @fooTail(i32 (i32)* nocapture %f1) {
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test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir

# RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \ # RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \
# RUN: -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \ # RUN: -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \
# RUN: | FileCheck %s # RUN: | FileCheck %s
# That that tail calls are checked when using indirect jump guards (hazard variant). # That that tail calls are checked when using indirect jump guards (hazard variant).
# CHECK: Bad machine code: invalid instruction when using jump guards! # CHECK: Bad machine code: invalid instruction when using jump guards!
--- | --- |
define i32 @fooTail(i32 (i32)* nocapture %f1) { define i32 @fooTail(i32 (i32)* nocapture %f1) {
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test/CodeGen/Mips/instverify/dext-pos.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range! # CHECK: Position operand is out of range!
# Check that the machine verifier checks the position operand is in the range 0..31 # Check that the machine verifier checks the position operand is in the range 0..31
--- ---
name: dext name: dext
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dext-size.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range! # CHECK: Size operand is out of range!
# Check that the machine verifier checks the size operand is in the range 1..32 # Check that the machine verifier checks the size operand is in the range 1..32
--- ---
name: dext name: dext
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dextm-pos-size.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position + Size is out of range! # CHECK: Position + Size is out of range!
# Check that the machine verifier checks the pos + size is in the range 33..64 # Check that the machine verifier checks the pos + size is in the range 33..64
--- ---
name: dextm name: dextm
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dextm-pos.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range! # CHECK: Position operand is out of range!
# Check that the machine verifier checks the position operand is in the range 0..31 # Check that the machine verifier checks the position operand is in the range 0..31
--- ---
name: dextm name: dextm
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dextm-size.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range! # CHECK: Size operand is out of range!
# Check that the machine verifier checks the size operand is in the range 33..64 # Check that the machine verifier checks the size operand is in the range 33..64
--- ---
name: dextm name: dextm
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dextu-pos-size.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position + Size is out of range! # CHECK: Position + Size is out of range!
# Check that the machine verifier checks the pos + size is in the range 33..64 # Check that the machine verifier checks the pos + size is in the range 33..64
--- ---
name: dextu name: dextu
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dextu-pos.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range! # CHECK: Position operand is out of range!
# Check that the machine verifier checks the position operand is in the range 32..63 # Check that the machine verifier checks the position operand is in the range 32..63
--- ---
name: dextu name: dextu
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dextu-size-valid.mir

# RUN: llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK-NOT: Size operand is out of range! # CHECK-NOT: Size operand is out of range!
# Check that the machine verifier checks the size operand is in the range 1..32 # Check that the machine verifier checks the size operand is in the range 1..32
--- ---
name: dextu name: dextu
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dextu-size.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range! # CHECK: Size operand is out of range!
# Check that the machine verifier checks the size operand is in the range 1..32 # Check that the machine verifier checks the size operand is in the range 1..32
--- ---
name: dextu name: dextu
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dins-pos-size.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position + Size is out of range! # CHECK: Position + Size is out of range!
# Check that the machine verifier checks the pos + size is in the range 1..32 # Check that the machine verifier checks the pos + size is in the range 1..32
--- ---
name: dins name: dins
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dins-pos.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range! # CHECK: Position operand is out of range!
# Check that the machine verifier checks the position operand is in the range 0..31 # Check that the machine verifier checks the position operand is in the range 0..31
--- ---
name: dins name: dins
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dins-size.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range! # CHECK: Size operand is out of range!
# Check that the machine verifier checks the size operand is in the range 1..32 # Check that the machine verifier checks the size operand is in the range 1..32
--- ---
name: dins name: dins
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dinsm-pos-size.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position + Size is out of range! # CHECK: Position + Size is out of range!
# Check that the machine verifier checks the pos + size is in the range 33..64 # Check that the machine verifier checks the pos + size is in the range 33..64
--- ---
name: dinsu name: dinsu
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dinsm-pos.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range! # CHECK: Position operand is out of range!
# Check that the machine verifier checks the position operand is in the range 0..31 # Check that the machine verifier checks the position operand is in the range 0..31
--- ---
name: dinsm name: dinsm
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dinsm-size.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range! # CHECK: Size operand is out of range!
# Check that the machine verifier checks the size operand is in the range 2..64 # Check that the machine verifier checks the size operand is in the range 2..64
--- ---
name: dinsm name: dinsm
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dinsu-pos-size.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position + Size is out of range! # CHECK: Position + Size is out of range!
# Check that the machine verifier checks the pos + size is in the range 33..64 # Check that the machine verifier checks the pos + size is in the range 33..64
--- ---
name: dinsu name: dinsu
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dinsu-pos.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range! # CHECK: Position operand is out of range!
# Check that the machine verifier checks the position operand is in the range 32..63 # Check that the machine verifier checks the position operand is in the range 32..63
--- ---
name: dinsu name: dinsu
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/dinsu-size.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range! # CHECK: Size operand is out of range!
# Check that the machine verifier checks the size operand is in the range 1..32 # Check that the machine verifier checks the size operand is in the range 1..32
--- ---
name: dinsu name: dinsu
alignment: 3 alignment: 3
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test/CodeGen/Mips/instverify/ext-pos-size.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position + Size is out of range! # CHECK: Position + Size is out of range!
# Check that the machine verifier checks the pos + size is in the range 1..32 # Check that the machine verifier checks the pos + size is in the range 1..32
--- ---
name: f name: f
alignment: 2 alignment: 2
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test/CodeGen/Mips/instverify/ext-pos.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range! # CHECK: Position operand is out of range!
# Check that the machine verifier checks the position operand is in the range 0..31 # Check that the machine verifier checks the position operand is in the range 0..31
--- ---
name: f name: f
alignment: 2 alignment: 2
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test/CodeGen/Mips/instverify/ext-size.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range! # CHECK: Size operand is out of range!
# Check that the machine verifier checks the size operand is in the range 1..32 # Check that the machine verifier checks the size operand is in the range 1..32
--- ---
name: f name: f
alignment: 2 alignment: 2
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test/CodeGen/Mips/instverify/ins-pos-size.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position + Size is out of range! # CHECK: Position + Size is out of range!
# Check that the machine verifier checks the pos + size is in the range 1..32 # Check that the machine verifier checks the pos + size is in the range 1..32
--- ---
name: f name: f
alignment: 2 alignment: 2
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test/CodeGen/Mips/instverify/ins-pos.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range! # CHECK: Position operand is out of range!
# Check that the machine verifier checks the position operand is in the range 0..31 # Check that the machine verifier checks the position operand is in the range 0..31
--- ---
name: f name: f
alignment: 2 alignment: 2
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test/CodeGen/Mips/instverify/ins-size.mir

# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ # RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range! # CHECK: Size operand is out of range!
# Check that the machine verifier checks the size operand is in the range 1..32 # Check that the machine verifier checks the size operand is in the range 1..32
--- ---
name: f name: f
alignment: 2 alignment: 2
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test/CodeGen/Mips/micromips-eva.mir

# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=expand-isel-pseudos \ # RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=finalize-isel \
# RUN: -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s # RUN: -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s
--- | --- |
@wArray = global [13 x i32] zeroinitializer, align 4 @wArray = global [13 x i32] zeroinitializer, align 4
@hArray = global [13 x i16] zeroinitializer, align 2 @hArray = global [13 x i16] zeroinitializer, align 2
@bArray = global [13 x i8] zeroinitializer, align 1 @bArray = global [13 x i8] zeroinitializer, align 1
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test/CodeGen/Mips/micromips-target-external-symbol-reloc.ll

; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips -stop-after=expand-isel-pseudos < %s | FileCheck %s ; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips -stop-after=finalize-isel < %s | FileCheck %s
; CHECK: JAL_MM ; CHECK: JAL_MM
; CHECK-NOT: JALR16_MM ; CHECK-NOT: JALR16_MM
define dso_local void @foo(i32* nocapture %ar) local_unnamed_addr { define dso_local void @foo(i32* nocapture %ar) local_unnamed_addr {
entry: entry:
%0 = bitcast i32* %ar to i8* %0 = bitcast i32* %ar to i8*
tail call void @llvm.memset.p0i8.i32(i8* align 4 %0, i8 0, i32 100, i1 false) tail call void @llvm.memset.p0i8.i32(i8* align 4 %0, i8 0, i32 100, i1 false)
ret void ret void
} }
declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1) declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1)

test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir

# RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \ # RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \
# RUN: -stop-after=expand-isel-pseudos -relocation-model=pic -mxgot \ # RUN: -stop-after=finalize-isel -relocation-model=pic -mxgot \
# RUN: -o /dev/null %s # RUN: -o /dev/null %s
# A simple test to show that we can parse the target specific flags: gpoff-hi, # A simple test to show that we can parse the target specific flags: gpoff-hi,
# gpoff-lo, tlsgd, tlsldm, dtprel-hi, dtprel-lo, got-hi, got-lo, call-hi, # gpoff-lo, tlsgd, tlsldm, dtprel-hi, dtprel-lo, got-hi, got-lo, call-hi,
# call-lo. # call-lo.
--- | --- |
@v = global i32 0, align 4 @v = global i32 0, align 4
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test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir

# RUN: llc -march=mips -start-before=expand-isel-pseudos \ # RUN: llc -march=mips -start-before=finalize-isel \
# RUN: -stop-after=expand-isel-pseudos -relocation-model=pic \ # RUN: -stop-after=finalize-isel -relocation-model=pic \
# RUN: -o /dev/null %s # RUN: -o /dev/null %s
# A simple test to show that we can parse the target specific flags: got-call, # A simple test to show that we can parse the target specific flags: got-call,
# got. # got.
--- | --- |
@v = global i32 0, align 4 @v = global i32 0, align 4
@j = external global i32, align 4 @j = external global i32, align 4
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test/CodeGen/Mips/mirparser/target-flags-pic.mir

# RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \ # RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \
# RUN: -stop-after=expand-isel-pseudos -relocation-model=pic \ # RUN: -stop-after=finalize-isel -relocation-model=pic \
# RUN: -o /dev/null %s # RUN: -o /dev/null %s
# A simple test to show that we can parse the target specific flags: gpoff-hi, # A simple test to show that we can parse the target specific flags: gpoff-hi,
#!gpoff-lo, got-call, got-disp. #!gpoff-lo, got-call, got-disp.
--- | --- |
@v = global i32 0, align 4 @v = global i32 0, align 4
@j = external global i32, align 4 @j = external global i32, align 4
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test/CodeGen/Mips/mirparser/target-flags-static-tls.mir

# RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \ # RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \
# RUN: -stop-after=expand-isel-pseudos -relocation-model=static -o /dev/null %s # RUN: -stop-after=finalize-isel -relocation-model=static -o /dev/null %s
# A simple test to show that we can parse the target specific flags: highest, # A simple test to show that we can parse the target specific flags: highest,
# higher, hi, lo, tprel-lo, tprel-hi, gpoff-hi, gpoff-lo, gottprel. # higher, hi, lo, tprel-lo, tprel-hi, gpoff-hi, gpoff-lo, gottprel.
--- | --- |
@v = global i32 0, align 4 @v = global i32 0, align 4
@k = thread_local global i32 0, align 4 @k = thread_local global i32 0, align 4
@j = external thread_local global i32, align 4 @j = external thread_local global i32, align 4
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test/CodeGen/Mips/unaligned-memops-mapping.mir

# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=expand-isel-pseudos \ # RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=finalize-isel \
# RUN: -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s # RUN: -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s
# Test that MIPS unaligned load/store instructions can be mapped to their # Test that MIPS unaligned load/store instructions can be mapped to their
# corresponding microMIPS instructions. # corresponding microMIPS instructions.
--- | --- |
define void @g(i32* %a, i32* %b) { define void @g(i32* %a, i32* %b) {
entry: entry:
%0 = load i32, i32* %a, align 1 %0 = load i32, i32* %a, align 1
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test/CodeGen/Mips/unaligned-memops.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -march=mips -mcpu=mips32r2 -stop-before=expand-isel-pseudos < %s | FileCheck %s --check-prefix=MIPS ; RUN: llc -march=mips -mcpu=mips32r2 -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MIPS
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=expand-isel-pseudos < %s | FileCheck %s --check-prefix=MICROMIPS ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MICROMIPS
; Test that the correct ISA version of the unaligned memory operations is ; Test that the correct ISA version of the unaligned memory operations is
; selected up front. ; selected up front.
define void @g2(i32* %a, i32* %b) { define void @g2(i32* %a, i32* %b) {
; MIPS-LABEL: name: g2 ; MIPS-LABEL: name: g2
; MIPS: bb.0.entry: ; MIPS: bb.0.entry:
; MIPS: liveins: $a0, $a1 ; MIPS: liveins: $a0, $a1
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test/CodeGen/PowerPC/debuginfo-split-int.ll

; RUN: llc < %s -stop-before=expand-isel-pseudos -o - | FileCheck %s ; RUN: llc < %s -stop-before=finalize-isel -o - | FileCheck %s
source_filename = "foo.c" source_filename = "foo.c"
target datalayout = "E-m:e-p:32:32-i64:64-n32" target datalayout = "E-m:e-p:32:32-i64:64-n32"
target triple = "ppc32" target triple = "ppc32"
; Verify that, when handling split-up integers, the ; Verify that, when handling split-up integers, the
; transferring of debug info takes the endianness ; transferring of debug info takes the endianness
; into consideration. ; into consideration.
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test/CodeGen/SystemZ/cc-liveness.ll

; Check that the MVCLoop (memcpy) is marked as clobbering CC, so that it will ; Check that the MVCLoop (memcpy) is marked as clobbering CC, so that it will
; not be placed betwen two compare and load-on-condition instructions. ; not be placed betwen two compare and load-on-condition instructions.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -pre-RA-sched=list-ilp \ ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -pre-RA-sched=list-ilp \
; RUN: -print-after=expand-isel-pseudos 2>&1 | FileCheck %s ; RUN: -print-after=finalize-isel 2>&1 | FileCheck %s
; ;
; CHECK-LABEL: bb.0.bb: ; CHECK-LABEL: bb.0.bb:
; CHECK: CLI ; CHECK: CLI
; CHECK: LOCGHI ; CHECK: LOCGHI
; CHECK-LABEL: bb.2.bb: ; CHECK-LABEL: bb.2.bb:
; CHECK: MVC ; CHECK: MVC
@.str.35 = external dso_local unnamed_addr constant [9 x i8], align 2 @.str.35 = external dso_local unnamed_addr constant [9 x i8], align 2
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test/CodeGen/SystemZ/debuginstr-02.mir

# Check that the backend can handle consecutive select instructions also in # Check that the backend can handle consecutive select instructions also in
# the presence of DEBUG_VALUE machine instructions. # the presence of DEBUG_VALUE machine instructions.
# #
# RUN: llc %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z13 \ # RUN: llc %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z13 \
# RUN: -start-before=expand-isel-pseudos -o - 2>&1 | FileCheck %s # RUN: -start-before=finalize-isel -o - 2>&1 | FileCheck %s
# #
# CHECK-LABEL: %bb.1: # CHECK-LABEL: %bb.1:
# CHECK: ldr # CHECK: ldr
# CHECK-NEXT: ldr # CHECK-NEXT: ldr
# CHECK-NEXT: ldr # CHECK-NEXT: ldr
--- | --- |
; ModuleID = 'tc.ll' ; ModuleID = 'tc.ll'
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test/CodeGen/X86/MachineBranchProb.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin -print-after=finalize-isel -o /dev/null 2>&1 | FileCheck %s
;; Make sure a transformation in SelectionDAGBuilder that converts "or + br" to ;; Make sure a transformation in SelectionDAGBuilder that converts "or + br" to
;; two branches correctly updates the branch probability. ;; two branches correctly updates the branch probability.
@max_regno = common global i32 0, align 4 @max_regno = common global i32 0, align 4
define void @test(i32* %old, i32 %final) { define void @test(i32* %old, i32 %final) {
for.cond: for.cond:
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test/CodeGen/X86/O0-pipeline.ll

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; CHECK-NEXT: FunctionPass Manager ; CHECK-NEXT: FunctionPass Manager
; CHECK-NEXT: Dominator Tree Construction ; CHECK-NEXT: Dominator Tree Construction
; CHECK-NEXT: Exception handling preparation ; CHECK-NEXT: Exception handling preparation
; CHECK-NEXT: Safe Stack instrumentation pass ; CHECK-NEXT: Safe Stack instrumentation pass
; CHECK-NEXT: Insert stack protectors ; CHECK-NEXT: Insert stack protectors
; CHECK-NEXT: Module Verifier ; CHECK-NEXT: Module Verifier
; CHECK-NEXT: X86 DAG->DAG Instruction Selection ; CHECK-NEXT: X86 DAG->DAG Instruction Selection
; CHECK-NEXT: X86 PIC Global Base Reg Initialization ; CHECK-NEXT: X86 PIC Global Base Reg Initialization
; CHECK-NEXT: Expand ISel Pseudo-instructions ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
; CHECK-NEXT: Local Stack Slot Allocation ; CHECK-NEXT: Local Stack Slot Allocation
; CHECK-NEXT: X86 speculative load hardening ; CHECK-NEXT: X86 speculative load hardening
; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: X86 EFLAGS copy lowering ; CHECK-NEXT: X86 EFLAGS copy lowering
; CHECK-NEXT: X86 WinAlloca Expander ; CHECK-NEXT: X86 WinAlloca Expander
; CHECK-NEXT: Eliminate PHI nodes for register allocation ; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Two-Address instruction pass ; CHECK-NEXT: Two-Address instruction pass
; CHECK-NEXT: Fast Register Allocator ; CHECK-NEXT: Fast Register Allocator
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test/CodeGen/X86/O3-pipeline.ll

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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Function Alias Analysis Results
; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: Natural Loop Information
; CHECK-NEXT: Branch Probability Analysis ; CHECK-NEXT: Branch Probability Analysis
; CHECK-NEXT: X86 DAG->DAG Instruction Selection ; CHECK-NEXT: X86 DAG->DAG Instruction Selection
; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Local Dynamic TLS Access Clean-up ; CHECK-NEXT: Local Dynamic TLS Access Clean-up
; CHECK-NEXT: X86 PIC Global Base Reg Initialization ; CHECK-NEXT: X86 PIC Global Base Reg Initialization
; CHECK-NEXT: Expand ISel Pseudo-instructions ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
; CHECK-NEXT: X86 Domain Reassignment Pass ; CHECK-NEXT: X86 Domain Reassignment Pass
; CHECK-NEXT: Early Tail Duplication ; CHECK-NEXT: Early Tail Duplication
; CHECK-NEXT: Optimize machine instruction PHIs ; CHECK-NEXT: Optimize machine instruction PHIs
; CHECK-NEXT: Slot index numbering ; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Merge disjoint stack slots ; CHECK-NEXT: Merge disjoint stack slots
; CHECK-NEXT: Local Stack Slot Allocation ; CHECK-NEXT: Local Stack Slot Allocation
; CHECK-NEXT: Remove dead machine instructions ; CHECK-NEXT: Remove dead machine instructions
; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: MachineDominator Tree Construction
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test/CodeGen/X86/catchpad-weight.ll

; RUN: llc -print-machineinstrs=expand-isel-pseudos %s -o /dev/null 2>&1 | FileCheck %s ; RUN: llc -print-after=finalize-isel %s -o /dev/null 2>&1 | FileCheck %s
; Check if the edge weight to the catchpad is calculated correctly. ; Check if the edge weight to the catchpad is calculated correctly.
; CHECK: successors: %bb.2(0x7ffff100), %bb.1(0x00000800), %bb.3(0x00000400), %bb.4(0x00000200), %bb.5(0x00000100) ; CHECK: successors: %bb.2(0x7ffff100), %bb.1(0x00000800), %bb.3(0x00000400), %bb.4(0x00000200), %bb.5(0x00000100)
target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64--windows-msvc18.0.0" target triple = "x86_64--windows-msvc18.0.0"
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test/CodeGen/X86/fast-isel-fneg-kill.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-apple-darwin10 -stop-after=expand-isel-pseudos | FileCheck %s ; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-apple-darwin10 -stop-after=finalize-isel | FileCheck %s
; Make sure we output the right kill flag for the xor conversion. ; Make sure we output the right kill flag for the xor conversion.
define void @goo(double* %x, double* %y) nounwind { define void @goo(double* %x, double* %y) nounwind {
; CHECK: %[[REG2:.*]]:gr64 = COPY $rsi ; CHECK: %[[REG2:.*]]:gr64 = COPY $rsi
; CHECK-NEXT: %[[REG0:.*]]:gr64 = COPY $rdi ; CHECK-NEXT: %[[REG0:.*]]:gr64 = COPY $rdi
; CHECK-NEXT: %[[REG1:.*]]:gr64 = COPY killed %[[REG0]] ; CHECK-NEXT: %[[REG1:.*]]:gr64 = COPY killed %[[REG0]]
; CHECK-NEXT: %[[REG3:.*]]:gr64 = COPY killed %[[REG2]] ; CHECK-NEXT: %[[REG3:.*]]:gr64 = COPY killed %[[REG2]]
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test/CodeGen/X86/fixed-stack-di-mir.ll

; RUN: llc -mtriple=x86_64-apple-unknown -stop-before=expand-isel-pseudos %s -o - -simplify-mir | FileCheck %s ; RUN: llc -mtriple=x86_64-apple-unknown -stop-before=finalize-isel %s -o - -simplify-mir | FileCheck %s
; The byval argument of the function will be allocated a fixed stack slot. Test ; The byval argument of the function will be allocated a fixed stack slot. Test
; that we serialize the fixed slot correctly. ; that we serialize the fixed slot correctly.
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-unknown" target triple = "x86_64-apple-unknown"
declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 declare void @llvm.dbg.declare(metadata, metadata, metadata) #0
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test/CodeGen/X86/i16lshr8pat.ll

; RUN: llc -stop-after expand-isel-pseudos < %s 2>&1 | FileCheck %s ; RUN: llc -stop-after finalize-isel < %s 2>&1 | FileCheck %s
target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
target triple = "i386-unknown-linux-gnu" target triple = "i386-unknown-linux-gnu"
; This test checks to make sure the lshr in %then1 block gets expanded using ; This test checks to make sure the lshr in %then1 block gets expanded using
; GR16_ABCD pattern rather than GR32_ABCD pattern. By using the 16-bit pattern ; GR16_ABCD pattern rather than GR32_ABCD pattern. By using the 16-bit pattern
; this doesn't make the register liveness information look like the whole ; this doesn't make the register liveness information look like the whole
; 32-bit register is a live value, and allows generally better live register ; 32-bit register is a live value, and allows generally better live register
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test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f -stop-after=expand-isel-pseudos | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f -stop-after=finalize-isel | FileCheck %s
; CHECK: %[[REG1:.*]]:vr512_0_15 = COPY %1 ; CHECK: %[[REG1:.*]]:vr512_0_15 = COPY %1
; CHECK: %[[REG2:.*]]:vr512_0_15 = COPY %2 ; CHECK: %[[REG2:.*]]:vr512_0_15 = COPY %2
; CHECK: INLINEASM &"vpaddq\09$3, $2, $0 {$1}", 0, 7340042, def %{{.*}}, 1179657, %{{.*}}, 7340041, %[[REG1]], 7340041, %[[REG2]], 12, implicit-def early-clobber $df, 12, implicit-def early-clobber $fpsw, 12, implicit-def early-clobber $eflags ; CHECK: INLINEASM &"vpaddq\09$3, $2, $0 {$1}", 0, 7340042, def %{{.*}}, 1179657, %{{.*}}, 7340041, %[[REG1]], 7340041, %[[REG2]], 12, implicit-def early-clobber $df, 12, implicit-def early-clobber $fpsw, 12, implicit-def early-clobber $eflags
define <8 x i64> @mask_Yk_i8(i8 signext %msk, <8 x i64> %x, <8 x i64> %y) { define <8 x i64> @mask_Yk_i8(i8 signext %msk, <8 x i64> %x, <8 x i64> %y) {
entry: entry:
%0 = tail call <8 x i64> asm "vpaddq\09$3, $2, $0 {$1}", "=x,^Yk,x,x,~{dirflag},~{fpsr},~{flags}"(i8 %msk, <8 x i64> %x, <8 x i64> %y) %0 = tail call <8 x i64> asm "vpaddq\09$3, $2, $0 {$1}", "=x,^Yk,x,x,~{dirflag},~{fpsr},~{flags}"(i8 %msk, <8 x i64> %x, <8 x i64> %y)
ret <8 x i64> %0 ret <8 x i64> %0
} }

test/CodeGen/X86/inline-asm-default-clobbers.ll

; RUN: llc < %s -mtriple=i686 -stop-after=expand-isel-pseudos | FileCheck %s ; RUN: llc < %s -mtriple=i686 -stop-after=finalize-isel | FileCheck %s
; CHECK: INLINEASM &"", 1, 12, implicit-def early-clobber $df, 12, implicit-def early-clobber $fpsw, 12, implicit-def early-clobber $eflags ; CHECK: INLINEASM &"", 1, 12, implicit-def early-clobber $df, 12, implicit-def early-clobber $fpsw, 12, implicit-def early-clobber $eflags
define void @foo() { define void @foo() {
entry: entry:
call void asm sideeffect "", "~{dirflag},~{fpsr},~{flags}"() call void asm sideeffect "", "~{dirflag},~{fpsr},~{flags}"()
ret void ret void
} }

test/CodeGen/X86/pr39896.ll

; RUN: llc %s -start-after=codegenprepare -stop-after=expand-isel-pseudos -o - | FileCheck %s ; RUN: llc %s -start-after=codegenprepare -stop-after=finalize-isel -o - | FileCheck %s
; PR39896: When code such as %conv below is dropped by SelectionDAG for having ; PR39896: When code such as %conv below is dropped by SelectionDAG for having
; no users, don't just drop the dbg.value record associated with it. Instead, ; no users, don't just drop the dbg.value record associated with it. Instead,
; the corresponding variable should receive a "DBG_VALUE" undef to terminate ; the corresponding variable should receive a "DBG_VALUE" undef to terminate
; earlier variable live ranges. ; earlier variable live ranges.
; ModuleID = 'run.c' ; ModuleID = 'run.c'
source_filename = "run.c" source_filename = "run.c"
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test/CodeGen/X86/sjlj-shadow-stack-liveness.mir

# RUN: llc -mtriple=x86_64-- -run-pass=expand-isel-pseudos -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -mtriple=x86_64-- -run-pass=finalize-isel -verify-machineinstrs -o - %s | FileCheck %s
# Check that we're not copying the kill flags with the operands from the pseudo # Check that we're not copying the kill flags with the operands from the pseudo
# instruction. # instruction.
--- | --- |
define void @bar() { ret void } define void @bar() { ret void }
!llvm.module.flags = !{!0} !llvm.module.flags = !{!0}
!0 = !{i32 4, !"cf-protection-return", i32 1} !0 = !{i32 4, !"cf-protection-return", i32 1}
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test/CodeGen/X86/sqrt-fastmath-mir.ll

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2,fma -stop-after=expand-isel-pseudos 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2,fma -stop-after=finalize-isel 2>&1 | FileCheck %s
declare float @llvm.sqrt.f32(float) #0 declare float @llvm.sqrt.f32(float) #0
define float @foo(float %f) #0 { define float @foo(float %f) #0 {
; CHECK: {{name: *foo}} ; CHECK: {{name: *foo}}
; CHECK: body: ; CHECK: body:
; CHECK: %0:fr32 = COPY $xmm0 ; CHECK: %0:fr32 = COPY $xmm0
; CHECK: %1:fr32 = VRSQRTSSr killed %2, %0 ; CHECK: %1:fr32 = VRSQRTSSr killed %2, %0
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test/CodeGen/X86/stack-protector-weight.ll

; RUN: llc -mtriple=x86_64-apple-darwin -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-SELDAG ; RUN: llc -mtriple=x86_64-apple-darwin -print-after=finalize-isel -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-SELDAG
; RUN: llc -mtriple=x86_64-apple-darwin -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-IR ; RUN: llc -mtriple=x86_64-apple-darwin -print-after=finalize-isel -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-IR
; RUN: llc -mtriple=i386-pc-windows-msvc -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-SELDAG ; RUN: llc -mtriple=i386-pc-windows-msvc -print-after=finalize-isel -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-SELDAG
; RUN: llc -mtriple=i386-pc-windows-msvc -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-IR ; RUN: llc -mtriple=i386-pc-windows-msvc -print-after=finalize-isel -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-IR
; DARWIN-SELDAG: # Machine code for function test_branch_weights: ; DARWIN-SELDAG: # Machine code for function test_branch_weights:
; DARWIN-SELDAG: successors: %bb.[[SUCCESS:[0-9]+]](0x7ffff800), %bb.[[FAILURE:[0-9]+]] ; DARWIN-SELDAG: successors: %bb.[[SUCCESS:[0-9]+]](0x7ffff800), %bb.[[FAILURE:[0-9]+]]
; DARWIN-SELDAG: bb.[[FAILURE]]{{[0-9a-zA-Z_.]+}}: ; DARWIN-SELDAG: bb.[[FAILURE]]{{[0-9a-zA-Z_.]+}}:
; DARWIN-SELDAG: CALL64pcrel32 &__stack_chk_fail ; DARWIN-SELDAG: CALL64pcrel32 &__stack_chk_fail
; DARWIN-SELDAG: bb.[[SUCCESS]]{{[0-9a-zA-Z_.]+}}: ; DARWIN-SELDAG: bb.[[SUCCESS]]{{[0-9a-zA-Z_.]+}}:
; DARWIN-IR: # Machine code for function test_branch_weights: ; DARWIN-IR: # Machine code for function test_branch_weights:
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test/CodeGen/X86/switch-edge-weight.ll

; RUN: llc -mtriple=x86_64-- -print-machineinstrs=expand-isel-pseudos %s -o /dev/null 2>&1 | FileCheck %s ; RUN: llc -mtriple=x86_64-- -print-after=finalize-isel %s -o /dev/null 2>&1 | FileCheck %s
declare void @foo(i32) declare void @foo(i32)
; CHECK-LABEL: test ; CHECK-LABEL: test
define void @test(i32 %x) nounwind { define void @test(i32 %x) nounwind {
entry: entry:
switch i32 %x, label %sw.default [ switch i32 %x, label %sw.default [
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; statement. ; statement.
; ;
; CHECK: bb.0{{[0-9a-zA-Z.]*}}: ; CHECK: bb.0{{[0-9a-zA-Z.]*}}:
; %bb.0 to %bb.6: [10, UINT32_MAX] (15) ; %bb.0 to %bb.6: [10, UINT32_MAX] (15)
; %bb.0 to %bb.8: [4, 20, 28, 36] (jump table) (45) ; %bb.0 to %bb.8: [4, 20, 28, 36] (jump table) (45)
; CHECK: successors: %bb.8(0x20000001), %bb.9(0x5fffffff) ; CHECK: successors: %bb.8(0x20000001), %bb.9(0x5fffffff)
} }
!1 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10} !1 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10}
!2 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10} !2 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10}
!3 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10} !3 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10}

test/CodeGen/X86/switch-jump-table.ll

; RUN: llc -mtriple=i686-pc-gnu-linux < %s | FileCheck %s ; RUN: llc -mtriple=i686-pc-gnu-linux < %s | FileCheck %s
; RUN: llc -mtriple=i686-pc-gnu-linux -print-machineinstrs=expand-isel-pseudos %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=CHECK-JT-PROB ; RUN: llc -mtriple=i686-pc-gnu-linux -print-after=finalize-isel %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=CHECK-JT-PROB
; An unreachable default destination is ignored and no compare and branch ; An unreachable default destination is ignored and no compare and branch
; is generated for the default values. ; is generated for the default values.
define void @foo(i32 %x, i32* %to) { define void @foo(i32 %x, i32* %to) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: movl 4(%esp), [[REG:%e[a-z]{2}]] ; CHECK: movl 4(%esp), [[REG:%e[a-z]{2}]]
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test/CodeGen/X86/switch-lower-peel-top-case.ll

; RUN: llc -mtriple=x86_64-linux-gnu -stop-after=expand-isel-pseudos < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-linux-gnu -stop-after=finalize-isel < %s | FileCheck %s
define i32 @foo(i32 %n) !prof !1 { define i32 @foo(i32 %n) !prof !1 {
entry: entry:
switch i32 %n, label %bb_default [ switch i32 %n, label %bb_default [
i32 8, label %bb1 i32 8, label %bb1
i32 -8826, label %bb2 i32 -8826, label %bb2
i32 18312, label %bb3 i32 18312, label %bb3
i32 18568, label %bb4 i32 18568, label %bb4
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test/CodeGen/X86/vecloadextract.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;RUN: llc < %s -mtriple=i686 -mattr=sse4.1 -stop-after=expand-isel-pseudos 2>&1 | FileCheck %s ;RUN: llc < %s -mtriple=i686 -mattr=sse4.1 -stop-after=finalize-isel 2>&1 | FileCheck %s
; This test makes sure we discard pointer info when we combine a vector load ; This test makes sure we discard pointer info when we combine a vector load
; and a variable extractelement into a scalar load using an index. There's also ; and a variable extractelement into a scalar load using an index. There's also
; a test to ensure we don't discard it for the constant index case. ; a test to ensure we don't discard it for the constant index case.
; CHECK: name: const_index ; CHECK: name: const_index
; CHECK: bb.0 (%ir-block.0): ; CHECK: bb.0 (%ir-block.0):
; CHECK: [[POINTER:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 4 from %fixed-stack.0) ; CHECK: [[POINTER:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 4 from %fixed-stack.0)
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test/CodeGen/X86/vmaskmov-offset.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=core-avx2 -stop-after expand-isel-pseudos -o - %s | FileCheck %s ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=core-avx2 -stop-after finalize-isel -o - %s | FileCheck %s
declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>) declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)
declare <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>) declare <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)
define void @test_v16f() local_unnamed_addr { define void @test_v16f() local_unnamed_addr {
; CHECK-LABEL: name: test_v16f ; CHECK-LABEL: name: test_v16f
; CHECK: bb.0.bb: ; CHECK: bb.0.bb:
; CHECK: [[AVX_SET0_:%[0-9]+]]:vr256 = AVX_SET0 ; CHECK: [[AVX_SET0_:%[0-9]+]]:vr256 = AVX_SET0
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test/CodeGen/X86/xor-combine-debugloc.ll

; RUN: llc -stop-after=expand-isel-pseudos < %s | FileCheck %s ; RUN: llc -stop-after=finalize-isel < %s | FileCheck %s
; ;
; Make sure that when the entry block of IR below is lowered, an instruction ; Make sure that when the entry block of IR below is lowered, an instruction
; that implictly defines $eflags has a same debug location with the icmp ; that implictly defines $eflags has a same debug location with the icmp
; instruction, and the branch instructions have a same debug location with the ; instruction, and the branch instructions have a same debug location with the
; br instruction. ; br instruction.
; ;
; CHECK: [[DLOC1:![0-9]+]] = !DILocation(line: 5, column: 9, scope: !{{[0-9]+}}) ; CHECK: [[DLOC1:![0-9]+]] = !DILocation(line: 5, column: 9, scope: !{{[0-9]+}})
; CHECK: [[DLOC2:![0-9]+]] = !DILocation(line: 5, column: 7, scope: !{{[0-9]+}}) ; CHECK: [[DLOC2:![0-9]+]] = !DILocation(line: 5, column: 7, scope: !{{[0-9]+}})
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test/DebugInfo/ARM/float-stack-arg.ll

; RUN: llc -mtriple=armv4t-unknown-unknown -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - %s | FileCheck %s ; RUN: llc -mtriple=armv4t-unknown-unknown -start-after=codegenprepare -stop-before=finalize-isel -o - %s | FileCheck %s
; Verify that a stack-referencing DBG_VALUE is emitted for p5 at the start of ; Verify that a stack-referencing DBG_VALUE is emitted for p5 at the start of
; the function. ; the function.
; ;
; Reproducer for PR40777. ; Reproducer for PR40777.
; ;
; Based on the following C reproducer: ; Based on the following C reproducer:
; ;
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test/DebugInfo/Generic/linear-dbg-value.ll

; FIXME: Fix machine verifier issues and remove -verify-machineinstrs=0. PR39452. ; FIXME: Fix machine verifier issues and remove -verify-machineinstrs=0. PR39452.
; RUN: llc -stop-before=expand-isel-pseudos -pre-RA-sched=linearize -verify-machineinstrs=0 < %s | FileCheck %s ; RUN: llc -stop-before=finalize-isel -pre-RA-sched=linearize -verify-machineinstrs=0 < %s | FileCheck %s
source_filename = "linear-dbg-value.ll" source_filename = "linear-dbg-value.ll"
; Function Attrs: nounwind readonly uwtable ; Function Attrs: nounwind readonly uwtable
define i32 @foo(i32* nocapture readonly %a, i32 %N) local_unnamed_addr #0 !dbg !6 { define i32 @foo(i32* nocapture readonly %a, i32 %N) local_unnamed_addr #0 !dbg !6 {
entry: entry:
%cmp6 = icmp sgt i32 %N, 0, !dbg !11 %cmp6 = icmp sgt i32 %N, 0, !dbg !11
br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup, !dbg !15 br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup, !dbg !15
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test/DebugInfo/X86/dbg-value-arg-movement.ll

; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before=expand-isel-pseudos %s -o - | FileCheck %s ; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before=finalize-isel %s -o - | FileCheck %s
; Test the movement of dbg.values of arguments. SelectionDAG tries to be ; Test the movement of dbg.values of arguments. SelectionDAG tries to be
; helpful and places DBG_VALUEs of Arguments at the start of functions. ; helpful and places DBG_VALUEs of Arguments at the start of functions.
; Unfortunately, this doesn't necessarily make sense, as one can specify an ; Unfortunately, this doesn't necessarily make sense, as one can specify an
; Argument IR Value as a variable location anywhere in the program. ; Argument IR Value as a variable location anywhere in the program.
; ;
; Distinguish cases where we want to hoist DBG_VALUEs, and those where we ; Distinguish cases where we want to hoist DBG_VALUEs, and those where we
; don't, by whether the referred to variable is a parameter to the current ; don't, by whether the referred to variable is a parameter to the current
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test/DebugInfo/X86/dbg-value-frame-index-2.ll

; RUN: llc -start-after=codegenprepare -stop-before=expand-isel-pseudos < %s -o - | FileCheck %s ; RUN: llc -start-after=codegenprepare -stop-before=finalize-isel < %s -o - | FileCheck %s
; Test that stack frame dbg.values are lowered to DBG_VALUEs, in blocks that ; Test that stack frame dbg.values are lowered to DBG_VALUEs, in blocks that
; are local to the alloca, and elsewhere. Differs from dbg-value-frame-index.ll ; are local to the alloca, and elsewhere. Differs from dbg-value-frame-index.ll
; because this test does not result in the frame-index being in a vreg, ; because this test does not result in the frame-index being in a vreg,
; instead it's exclusively referred to by memory operands of instructions. ; instead it's exclusively referred to by memory operands of instructions.
; ;
; Additionally test that we don't re-order with constant values -- both are ; Additionally test that we don't re-order with constant values -- both are
; independent of the order the instructions get lowered, but should not ; independent of the order the instructions get lowered, but should not
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test/DebugInfo/X86/dbg-value-funcarg.ll

; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - %s | FileCheck %s ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=finalize-isel -o - %s | FileCheck %s
; Input to this test looked like this and was compiled using: clang -g -O1 -mllvm -stop-after=codegenprepare -S ; Input to this test looked like this and was compiled using: clang -g -O1 -mllvm -stop-after=codegenprepare -S
; ;
; extern void bar(int); ; extern void bar(int);
; ;
; void foo_local(int t1a) { ; void foo_local(int t1a) {
; int local = 123; ; int local = 123;
; bar(local); ; bar(local);
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test/DebugInfo/X86/dbg-value-funcarg2.ll

; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - %s | FileCheck %s ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=finalize-isel -o - %s | FileCheck %s
; Test case was generated from the following C code, ; Test case was generated from the following C code,
; using: clang -g -O1 -S -emit-llvm s.c -o s.ll ; using: clang -g -O1 -S -emit-llvm s.c -o s.ll
; ;
; struct s { long long int i, j; }; ; struct s { long long int i, j; };
; ;
; extern void bar(struct s, struct s, struct s); ; extern void bar(struct s, struct s, struct s);
; ;
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test/DebugInfo/X86/pr40427.ll

; RUN: llc -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - < %s | FileCheck %s ; RUN: llc -start-after=codegenprepare -stop-before=finalize-isel -o - < %s | FileCheck %s
; Test for correct placement of DBG_VALUE, which in PR40427 is placed before ; Test for correct placement of DBG_VALUE, which in PR40427 is placed before
; the load instruction it refers to. The circumstance replicated here is where ; the load instruction it refers to. The circumstance replicated here is where
; two instructions in a row, trunc and add, begin with no-op Copy{To,From}Reg ; two instructions in a row, trunc and add, begin with no-op Copy{To,From}Reg
; SDNodes that produce no instructions. ; SDNodes that produce no instructions.
; The DBG_VALUE instruction should come immediately after the load instruction ; The DBG_VALUE instruction should come immediately after the load instruction
; because the truncate is optimised out, and the DBG_VALUE should be placed ; because the truncate is optimised out, and the DBG_VALUE should be placed
; in front of the first instruction that occurs after the dbg.value. ; in front of the first instruction that occurs after the dbg.value.
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test/DebugInfo/X86/safestack-byval.ll

; Test dwarf codegen for DILocalVariable of a byval function argument that ; Test dwarf codegen for DILocalVariable of a byval function argument that
; points to neither an argument nor an alloca. This kind of IR is generated by ; points to neither an argument nor an alloca. This kind of IR is generated by
; SafeStack for unsafe byval arguments. ; SafeStack for unsafe byval arguments.
; RUN: llc -mtriple=x86_64-unknown-unknown -stop-after expand-isel-pseudos %s -o - | FileCheck %s ; RUN: llc -mtriple=x86_64-unknown-unknown -stop-after finalize-isel %s -o - | FileCheck %s
; This was built by compiling the following source with SafeStack and ; This was built by compiling the following source with SafeStack and
; simplifying the result a little. ; simplifying the result a little.
; struct S { ; struct S {
; int a[100]; ; int a[100];
; }; ; };
; ;
; int f(S zzz, unsigned long len) { ; int f(S zzz, unsigned long len) {
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test/DebugInfo/X86/sdag-dangling-dbgvalue.ll

; RUN: llc %s -stop-before expand-isel-pseudos -o - | FileCheck %s ; RUN: llc %s -stop-before finalize-isel -o - | FileCheck %s
;-------------------------------------------------------------------- ;--------------------------------------------------------------------
; This test case is basically generated from the following C code. ; This test case is basically generated from the following C code.
; Compiled with "--target=x86_64-apple-darwin -S -g -O3" to get debug ; Compiled with "--target=x86_64-apple-darwin -S -g -O3" to get debug
; info for optimized code. ; info for optimized code.
; ;
; struct SS { ; struct SS {
; int a; ; int a;
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test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll

; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s ; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s
; This test case was generated from the following debug.c program, ; This test case was generated from the following debug.c program,
; using: clang debug.c -g -O1 -S -o dbg_value_phi_isel1.ll -emit-llvm ; using: clang debug.c -g -O1 -S -o dbg_value_phi_isel1.ll -emit-llvm
; -------------------------------------- ; --------------------------------------
; int end = 10; ; int end = 10;
; ;
; int main() { ; int main() {
; int x = 9; ; int x = 9;
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test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll

; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s ; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s
; This test case is a modified version of dbg_value_phi_isel1.ll ; This test case is a modified version of dbg_value_phi_isel1.ll
; where the llvm.dbg.value nodes in for.body has been moved. ; where the llvm.dbg.value nodes in for.body has been moved.
; ModuleID = 'debug.c' ; ModuleID = 'debug.c'
source_filename = "debug.c" source_filename = "debug.c"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
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test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll

; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s ; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s
; This test case was generated from the following phi-split.c program, ; This test case was generated from the following phi-split.c program,
; using: clang phi-split.c -g -O1 -S -o - --target=i386 -emit-llvm ; using: clang phi-split.c -g -O1 -S -o - --target=i386 -emit-llvm
; -------------------------------------- ; --------------------------------------
; long long end = 10; ; long long end = 10;
; ;
; int main() { ; int main() {
; long long x = 9; ; long long x = 9;
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test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll

; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s ; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s
; This is a reproducer based on the test case from PR37321. ; This is a reproducer based on the test case from PR37321.
; We verify that the fragment for the last DBG_VALUE is limited depending ; We verify that the fragment for the last DBG_VALUE is limited depending
; on the size of the original fragment (and that we do not emit more ; on the size of the original fragment (and that we do not emit more
; DBG_VALUE instructions than needed in case we cover the whole original ; DBG_VALUE instructions than needed in case we cover the whole original
; fragment with just a few DBG_VALUE instructions). ; fragment with just a few DBG_VALUE instructions).
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test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll

; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s ; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s
; Test that dbg.values of an SSA variable that's not used in a basic block, ; Test that dbg.values of an SSA variable that's not used in a basic block,
; is converted to a DBG_VALUE in that same basic block. We know that %1 is ; is converted to a DBG_VALUE in that same basic block. We know that %1 is
; live from the entry bb to the exit bb, is allocated a vreg because it's ; live from the entry bb to the exit bb, is allocated a vreg because it's
; used across basic blocks. We should be able to produce a DBG_VALUE that ; used across basic blocks. We should be able to produce a DBG_VALUE that
; refers to it in the nextbb block. ; refers to it in the nextbb block.
source_filename = "debug.c" source_filename = "debug.c"
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test/DebugInfo/X86/sdag-ir-salvage.ll

; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before expand-isel-pseudos %s -o - | FileCheck %s ; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before finalize-isel %s -o - | FileCheck %s
; Test that the dbg.value for %baz, which doesn't exist in the 'next' bb, ; Test that the dbg.value for %baz, which doesn't exist in the 'next' bb,
; can be salvaged back to the underlying argument vreg. ; can be salvaged back to the underlying argument vreg.
; CHECK: ![[AAAVAR:.*]] = !DILocalVariable(name: "aaa", ; CHECK: ![[AAAVAR:.*]] = !DILocalVariable(name: "aaa",
; CHECK-LABEL: bb.1.next: ; CHECK-LABEL: bb.1.next:
; CHECK: DBG_VALUE %{{[0-9]+}}, $noreg, ![[AAAVAR]] ; CHECK: DBG_VALUE %{{[0-9]+}}, $noreg, ![[AAAVAR]]
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