[aarch64][globalisel] Move getValueMapping/getCopyMapping to AArch64GenRegisterBankInfo. NFC.

[dsanders]

Summary

We did lose a little specificity in the assertion messages for the
PartialMappingIdx enumerators in this change but this was necessary to
avoid unnecessary use of 'public:' and we haven't lost anything that
can't be discovered easily in lldb. Once this is tablegen-erated we could
also safely remove the assertions.

Depends on D27976

[qcolombet]

LGTM.

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

234

80-col

[dsanders]

Rebased onto new D27977

[dsanders]

Refresh before commit

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::ValMappings[]{
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
     // 27: FPR 64-bit value to GPR 64-bit value. <-- This must match
     //                                               LastCrossRegCpyIdx.
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1}
 };
 
-namespace AArch64 {
-/// Get the pointer to the ValueMapping representing the RegisterBank
-/// at \p RBIdx with a size of \p Size.
-///
-/// The returned mapping works for instructions with the same kind of
-/// operands for up to 3 operands.
-///
-/// \pre \p RBIdx != PartialMappingIdx::None
-const RegisterBankInfo::ValueMapping *
-getValueMapping(AArch64GenRegisterBankInfo::PartialMappingIdx RBIdx,
-                unsigned Size) {
-  assert(RBIdx != AArch64GenRegisterBankInfo::PartialMappingIdx::PMI_None &&
-         "No mapping needed for that");
-  unsigned ValMappingIdx =
-      AArch64GenRegisterBankInfo::First3OpsIdx +
-      (RBIdx - AArch64GenRegisterBankInfo::PartialMappingIdx::PMI_Min +
-       AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(RBIdx, Size)) *
-          AArch64GenRegisterBankInfo::ValueMappingIdx::DistanceBetweenRegBanks;
-  assert(ValMappingIdx >= AArch64GenRegisterBankInfo::First3OpsIdx &&
-         ValMappingIdx <= AArch64GenRegisterBankInfo::Last3OpsIdx &&
-         "Mapping out of bound");
-
-  return &AArch64GenRegisterBankInfo::ValMappings[ValMappingIdx];
-}
-
-/// Get the pointer to the ValueMapping of the operands of a copy
-/// instruction from a GPR or FPR register to a GPR or FPR register
-/// with a size of \p Size.
-///
-/// If \p DstIsGPR is true, the destination of the copy is on GPR,
-/// otherwise it is on FPR. Same thing for \p SrcIsGPR.
-const RegisterBankInfo::ValueMapping *
-getCopyMapping(bool DstIsGPR, bool SrcIsGPR, unsigned Size) {
-  AArch64GenRegisterBankInfo::PartialMappingIdx DstRBIdx =
-      DstIsGPR ? AArch64GenRegisterBankInfo::PMI_FirstGPR
-               : AArch64GenRegisterBankInfo::PMI_FirstFPR;
-  AArch64GenRegisterBankInfo::PartialMappingIdx SrcRBIdx =
-      SrcIsGPR ? AArch64GenRegisterBankInfo::PMI_FirstGPR
-               : AArch64GenRegisterBankInfo::PMI_FirstFPR;
-  if (DstRBIdx == SrcRBIdx)
-    return getValueMapping(DstRBIdx, Size);
-  assert(Size <= 64 && "GPR cannot handle that size");
-  unsigned ValMappingIdx =
-      AArch64GenRegisterBankInfo::FirstCrossRegCpyIdx +
-      (DstRBIdx - AArch64GenRegisterBankInfo::PMI_Min +
-       AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(DstRBIdx, Size)) *
-          AArch64GenRegisterBankInfo::ValueMappingIdx::
-              DistanceBetweenCrossRegCpy;
-  assert(ValMappingIdx >= AArch64GenRegisterBankInfo::FirstCrossRegCpyIdx &&
-         ValMappingIdx <= AArch64GenRegisterBankInfo::LastCrossRegCpyIdx &&
-         "Mapping out of bound");
-  return &AArch64GenRegisterBankInfo::ValMappings[ValMappingIdx];
-}
-} // End AArch64 namespace.
-
 bool AArch64GenRegisterBankInfo::checkPartialMap(unsigned Idx,
                                                  unsigned ValStartIdx,
                                                  unsigned ValLength,
                                                  const RegisterBank &RB) {
   const PartialMapping &Map = PartMappings[Idx - PartialMappingIdx::PMI_Min];
   return Map.StartIdx == ValStartIdx && Map.Length == ValLength &&
          Map.RegBank == &RB;
 }
 
 bool AArch64GenRegisterBankInfo::checkValueMapImpl(unsigned Idx,
                                                    unsigned FirstInBank,
                                                    unsigned Size,
                                                    unsigned Offset) {
   unsigned PartialMapBaseIdx = Idx - PartialMappingIdx::PMI_Min;
   const ValueMapping &Map =
-      AArch64::getValueMapping((PartialMappingIdx)FirstInBank, Size)[Offset];
+      AArch64GenRegisterBankInfo::getValueMapping((PartialMappingIdx)FirstInBank, Size)[Offset];
   return Map.BreakDown == &PartMappings[PartialMapBaseIdx] &&
          Map.NumBreakDowns == 1;
 }
 
+bool AArch64GenRegisterBankInfo::checkPartialMappingIdx(
+    PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias,
+    ArrayRef<PartialMappingIdx> Order) {
+  if (Order.front() != FirstAlias)
+    return false;
+  if (Order.back() != LastAlias)
+    return false;
+  if (Order.front() > Order.back())
+    return false;
+
+  PartialMappingIdx Previous = Order.front();
+  bool First = true;
+  for (const auto &Current : Order) {
+    if (First) {
+      First = false;
+      continue;
+    }
+    if (Previous + 1 != Current)
+      return false;
+    Previous = Current;
+  }
+  return true;
+}
+
+unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx,
+                                                             unsigned Size) {
+  if (RBIdx == PMI_FirstGPR) {
+    if (Size <= 32)
+      return 0;
+    if (Size <= 64)
+      return 1;
+    llvm_unreachable("Unexpected size");
+  }
+  if (RBIdx == PMI_FirstFPR) {
+    if (Size <= 32)
+      return 0;
+    if (Size <= 64)
+      return 1;
+    if (Size <= 128)
+      return 2;
+    if (Size <= 256)
+      return 3;
+    if (Size <= 512)
+      return 4;
+    llvm_unreachable("Unexpected size");
+  }
+  llvm_unreachable("Unexpected bank");
+}
+
+const RegisterBankInfo::ValueMapping *
+AArch64GenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx,
+                                            unsigned Size) {
+  assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
+  unsigned ValMappingIdx = First3OpsIdx +
+                           (RBIdx - PartialMappingIdx::PMI_Min +
+                            getRegBankBaseIdxOffset(RBIdx, Size)) *
+                               ValueMappingIdx::DistanceBetweenRegBanks;
+  assert(ValMappingIdx >= First3OpsIdx && ValMappingIdx <= Last3OpsIdx &&
+         "Mapping out of bound");
+
+  return &ValMappings[ValMappingIdx];
+}
+
+const RegisterBankInfo::ValueMapping *
+AArch64GenRegisterBankInfo::getCopyMapping(bool DstIsGPR, bool SrcIsGPR,
+                                           unsigned Size) {
+  PartialMappingIdx DstRBIdx = DstIsGPR ? PMI_FirstGPR : PMI_FirstFPR;
+  PartialMappingIdx SrcRBIdx = SrcIsGPR ? PMI_FirstGPR : PMI_FirstFPR;
+  if (DstRBIdx == SrcRBIdx)
+    return getValueMapping(DstRBIdx, Size);
+  assert(Size <= 64 && "GPR cannot handle that size");
+  unsigned ValMappingIdx =
+      FirstCrossRegCpyIdx +
+      (DstRBIdx - PMI_Min + getRegBankBaseIdxOffset(DstRBIdx, Size)) *
+          ValueMappingIdx::DistanceBetweenCrossRegCpy;
+  assert(ValMappingIdx >= FirstCrossRegCpyIdx &&
+         ValMappingIdx <= LastCrossRegCpyIdx && "Mapping out of bound");
+  return &ValMappings[ValMappingIdx];
+}
 } // End llvm namespace.

lib/Target/AArch64/AArch64RegisterBankInfo.h

enum ValueMappingIdx {
     DistanceBetweenRegBanks = 3,
     FirstCrossRegCpyIdx = 21,
     LastCrossRegCpyIdx = 27,
     DistanceBetweenCrossRegCpy = 2
   };
 
   static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias,
                                      PartialMappingIdx LastAlias,
-                                     ArrayRef<PartialMappingIdx> Order) {
-    if (Order.front() != FirstAlias)
-      return false;
-    if (Order.back() != LastAlias)
-      return false;
-    if (Order.front() > Order.back())
-      return false;
-
-    PartialMappingIdx Previous = Order.front();
-    bool First = true;
-    for (const auto &Current : Order) {
-      if (First) {
-        First = false;
-        continue;
-      }
-      if (Previous + 1 != Current)
-        return false;
-      Previous = Current;
-    }
-    return true;
-  }
-
-  static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size) {
-    if (RBIdx == PMI_FirstGPR) {
-      if (Size <= 32)
-        return 0;
-      if (Size <= 64)
-        return 1;
-      llvm_unreachable("Unexpected size");
-    }
-    if (RBIdx == PMI_FirstFPR) {
-      if (Size <= 32)
-        return 0;
-      if (Size <= 64)
-        return 1;
-      if (Size <= 128)
-        return 2;
-      if (Size <= 256)
-        return 3;
-      if (Size <= 512)
-        return 4;
-      llvm_unreachable("Unexpected size");
-    }
-    llvm_unreachable("Unexpected bank");
-}
+                                     ArrayRef<PartialMappingIdx> Order);
+
+  static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size);
+
+  /// Get the pointer to the ValueMapping representing the RegisterBank
+  /// at \p RBIdx with a size of \p Size.
+  ///
+  /// The returned mapping works for instructions with the same kind of
+  /// operands for up to 3 operands.
+  ///
+  /// \pre \p RBIdx != PartialMappingIdx::None
+  static const RegisterBankInfo::ValueMapping *
+  getValueMapping(PartialMappingIdx RBIdx, unsigned Size);
+
+  /// Get the pointer to the ValueMapping of the operands of a copy
+  /// instruction from a GPR or FPR register to a GPR or FPR register
+  /// with a size of \p Size.
+  ///
+  /// If \p DstIsGPR is true, the destination of the copy is on GPR,
+  /// otherwise it is on FPR. Same thing for \p SrcIsGPR.
+  static const RegisterBankInfo::ValueMapping *
+  getCopyMapping(bool DstIsGPR, bool SrcIsGPR, unsigned Size);
 };
 
 /// This class provides the information for the target register banks.
 class AArch64RegisterBankInfo final : public AArch64GenRegisterBankInfo {
   /// See RegisterBankInfo::applyMapping.
   void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
 
   /// Get an instruction mapping where all the operands map to

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

 
 #define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size)                 \
   do {                                                                         \
     unsigned PartialMapDstIdx = PMI_##RBNameDst##Size - PMI_Min;               \
     unsigned PartialMapSrcIdx = PMI_##RBNameSrc##Size - PMI_Min;               \
     (void)PartialMapDstIdx;                                                    \
     (void)PartialMapSrcIdx;                                                    \
     const ValueMapping *Map =                                                  \
-        AArch64::getCopyMapping(PMI_First##RBNameDst == PMI_FirstGPR,          \
-                                PMI_First##RBNameSrc == PMI_FirstGPR, Size);   \
+        getCopyMapping(PMI_First##RBNameDst == PMI_FirstGPR,                   \
+                       PMI_First##RBNameSrc == PMI_FirstGPR, Size);            \
     (void)Map;                                                                 \
     assert(Map[0].BreakDown ==                                                 \
                &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] &&  \
            Map[0].NumBreakDowns == 1 && #RBNameDst #Size                       \
            " Dst is incorrectly initialized");                                 \
     assert(Map[1].BreakDown ==                                                 \
                &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] &&  \
            Map[1].NumBreakDowns == 1 && #RBNameSrc #Size                       \
if (Size != 32 && Size != 64)
       break;
 
     // If the instruction has any implicit-defs or uses,
     // do not mess with it.
     if (MI.getNumOperands() != 3)
       break;
     InstructionMappings AltMappings;
     InstructionMapping GPRMapping(
-        /*ID*/ 1, /*Cost*/ 1, AArch64::getValueMapping(PMI_FirstGPR, Size),
+        /*ID*/ 1, /*Cost*/ 1, getValueMapping(PMI_FirstGPR, Size),
         /*NumOperands*/ 3);
     InstructionMapping FPRMapping(
-        /*ID*/ 2, /*Cost*/ 1, AArch64::getValueMapping(PMI_FirstFPR, Size),
+        /*ID*/ 2, /*Cost*/ 1, getValueMapping(PMI_FirstFPR, Size),
         /*NumOperands*/ 3);
 
     AltMappings.emplace_back(std::move(GPRMapping));
     AltMappings.emplace_back(std::move(FPRMapping));
     return AltMappings;
   }
   case TargetOpcode::G_BITCAST: {
     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
     if (Size != 32 && Size != 64)
       break;
 
     // If the instruction has any implicit-defs or uses,
     // do not mess with it.
     if (MI.getNumOperands() != 2)
       break;
 
     InstructionMappings AltMappings;
     InstructionMapping GPRMapping(
         /*ID*/ 1, /*Cost*/ 1,
-        AArch64::getCopyMapping(/*DstIsGPR*/ true, /*SrcIsGPR*/ true, Size),
+        getCopyMapping(/*DstIsGPR*/ true, /*SrcIsGPR*/ true, Size),
         /*NumOperands*/ 2);
     InstructionMapping FPRMapping(
         /*ID*/ 2, /*Cost*/ 1,
-        AArch64::getCopyMapping(/*DstIsGPR*/ false, /*SrcIsGPR*/ false, Size),
+        getCopyMapping(/*DstIsGPR*/ false, /*SrcIsGPR*/ false, Size),
         /*NumOperands*/ 2);
     InstructionMapping GPRToFPRMapping(
         /*ID*/ 3,
         /*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
-        AArch64::getCopyMapping(/*DstIsGPR*/ false, /*SrcIsGPR*/ true, Size),
+        getCopyMapping(/*DstIsGPR*/ false, /*SrcIsGPR*/ true, Size),
         /*NumOperands*/ 2);
     InstructionMapping FPRToGPRMapping(
         /*ID*/ 3,
         /*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
-        AArch64::getCopyMapping(/*DstIsGPR*/ true, /*SrcIsGPR*/ false, Size),
+        getCopyMapping(/*DstIsGPR*/ true, /*SrcIsGPR*/ false, Size),
         /*NumOperands*/ 2);
 
     AltMappings.emplace_back(std::move(GPRMapping));
     AltMappings.emplace_back(std::move(FPRMapping));
     AltMappings.emplace_back(std::move(GPRToFPRMapping));
     AltMappings.emplace_back(std::move(FPRToGPRMapping));
     return AltMappings;
   }
   case TargetOpcode::G_LOAD: {
     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
     if (Size != 64)
       break;
 
     // If the instruction has any implicit-defs or uses,
     // do not mess with it.
     if (MI.getNumOperands() != 2)
       break;
 
     InstructionMappings AltMappings;
     InstructionMapping GPRMapping(
         /*ID*/ 1, /*Cost*/ 1,
-        getOperandsMapping({AArch64::getValueMapping(PMI_FirstGPR, Size),
+        getOperandsMapping({getValueMapping(PMI_FirstGPR, Size),
                             // Addresses are GPR 64-bit.
-                            AArch64::getValueMapping(PMI_FirstGPR, 64)}),
+                            getValueMapping(PMI_FirstGPR, 64)}),
         /*NumOperands*/ 2);
     InstructionMapping FPRMapping(
         /*ID*/ 2, /*Cost*/ 1,
-        getOperandsMapping({AArch64::getValueMapping(PMI_FirstFPR, Size),
+        getOperandsMapping({getValueMapping(PMI_FirstFPR, Size),
                             // Addresses are GPR 64-bit.
-                            AArch64::getValueMapping(PMI_FirstGPR, 64)}),
+                            getValueMapping(PMI_FirstGPR, 64)}),
         /*NumOperands*/ 2);
 
     AltMappings.emplace_back(std::move(GPRMapping));
     AltMappings.emplace_back(std::move(FPRMapping));
     return AltMappings;
   }
   default:
     break;
assert(
             AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(RBIdx, Size) &&
         "Operand has incompatible size");
     bool OpIsFPR = OpTy.isVector() || isPreISelGenericFloatingPointOpcode(Opc);
     (void)OpIsFPR;
     assert(IsFPR == OpIsFPR && "Operand has incompatible type");
   }
 #endif // End NDEBUG.
 
-  return InstructionMapping{DefaultMappingID, 1,
-                            AArch64::getValueMapping(RBIdx, Size), NumOperands};
+  return InstructionMapping{DefaultMappingID, 1, getValueMapping(RBIdx, Size),
+                            NumOperands};
 }
 
 RegisterBankInfo::InstructionMapping
 AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   const unsigned Opc = MI.getOpcode();
   const MachineFunction &MF = *MI.getParent()->getParent();
   const MachineRegisterInfo &MRI = MF.getRegInfo();
 
case TargetOpcode::G_BITCAST: {
     unsigned Size = DstTy.getSizeInBits();
     bool DstIsGPR = !DstTy.isVector();
     bool SrcIsGPR = !SrcTy.isVector();
     const RegisterBank &DstRB =
         DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
     const RegisterBank &SrcRB =
         SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
     return InstructionMapping{DefaultMappingID, copyCost(DstRB, SrcRB, Size),
-                              AArch64::getCopyMapping(DstIsGPR, SrcIsGPR, Size),
+                              getCopyMapping(DstIsGPR, SrcIsGPR, Size),
                               /*NumOperands*/ 2};
   }
   case TargetOpcode::G_SEQUENCE:
     // FIXME: support this, but the generic code is really not going to do
     // anything sane.
     return InstructionMapping();
   default:
     break;
AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   }
 
   // Finally construct the computed mapping.
   RegisterBankInfo::InstructionMapping Mapping =
       InstructionMapping{DefaultMappingID, Cost, nullptr, NumOperands};
   SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
   for (unsigned Idx = 0; Idx < NumOperands; ++Idx)
     if (MI.getOperand(Idx).isReg())
-      OpdsMapping[Idx] =
-          AArch64::getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]);
+      OpdsMapping[Idx] = getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]);
 
   Mapping.setOperandsMapping(getOperandsMapping(OpdsMapping));
   return Mapping;
 }