[aarch64][globalisel] Move data into <Target>GenRegisterBankInfo. NFC.

[dsanders]

Summary

Depends on D27809

[qcolombet]

Hi Daniel,

LGTM modulo a couple of nitpicks.

Cheers,
-Quentin

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

99

I would rather have the register banks in the AArch64 namespace. I expect we will use them directly, and having to specify AArch64GenRegisterBankInfo seems painful.

lib/Target/AArch64/AArch64RegisterBankInfo.h

78

I would prefer that we call this checkXXX and return a bool.
The assert is then part of the caller, i.e., assert(checkXXX).

78

const std::vector<...> &

[qcolombet]

lib/Target/AArch64/AArch64RegisterBankInfo.h

32

FWIW, I believe that generating that part could be part of the tablegen switch. I indeed don't think it makes much to have a XXXGen manually written. I.e., could be squashed with the tablegen switch.

But I am fine with the intermediate step if it does not last long.

[dsanders]

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

99

Hmm, I can move it to llvm::AArch64 but I have to either hard-code the number of register classes and eliminate finishInit() or allow these variables to be in a partially-initialized state until the TargetRegisterInfo exists and something (currently <Target>RegisterBankInfo) can finish the initialization. If we do this after the tablegen patch then we can have tablegen emit the correct size.

Which would you prefer?

Also, just so we're on the same page: Which passes do you expect to use them directly?

lib/Target/AArch64/AArch64RegisterBankInfo.h

32

It could be part of the tablegen switch. The reason it isn't is that Ahmed suggested adding the class first and then having a tablegen patch make tablegen emit that same implementation.

78

I would prefer that we call this checkXXX and return a bool.
The assert is then part of the caller, i.e., assert(checkXXX).

Ok.

const std::vector<...> &

Well spotted

[qcolombet]

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

99

If we do this after the tablegen patch then we can have tablegen emit the correct size.

That would be my preference.

Which passes do you expect to use them directly?

I expect some AArch64 specific passes to use them directly like what we do with GPR64RegClass and such. Anyway, it would be strange if the register classes and the register banks are in different namespace IMHO.

lib/Target/AArch64/AArch64RegisterBankInfo.h

32

Up to you.
I would say that either way is fine as long as XXXGenRegisterBankInfo gets generated by TableGen shortly.

[dsanders]

Rebased onto new D27809.

Also, the *RegBank globals are back in the llvm::<Target> namespace and
assertPartialMappingIdx() is now checkPartialMappingIdx() as requested.

[dsanders]

lib/Target/AArch64/AArch64RegisterBankInfo.h

78

I haven't made the change to a const std::vector<...> & because the arguments are initializer_lists and cannot be bound to the reference type. I could fix this but it makes the caller side a bit uglier:

std::vector<PartialMappingIdx> Temp = {PMI_GPR32, PMI_GPR64};
checkPartialMappingIdx(..., Temp);

and only saves us a small constant amount of time in debug builds.

Do you think I should leave it as-is or go with the uglier code?

[ab]

This LGTM, but I'll let Quentin have final say.

lib/Target/AArch64/AArch64RegisterBankInfo.h

32

It could be part of the tablegen switch. The reason it isn't is that Ahmed suggested adding the class first and then having a tablegen patch make tablegen emit that same implementation.

Sorry if I was unclear: I think the tablegen patch should be NFC (the main issue being PartialMapping), but not necessarily that it generates exactly the same code as existed before. So, I'd also say squash this with the tablegen switch, but it's not a big deal either way.

78

What about ArrayRef<PartialMappingIdx> ?

[qcolombet]

LGTM as well.

Ahmed's suggestion to use ArrayRef is probably best.

[dsanders]

lib/Target/AArch64/AArch64RegisterBankInfo.h

78

That worked nicely. Thanks

[dsanders]

Use ArrayRef

[dsanders]

Refresh before commit

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_BUILD_GLOBAL_ISEL
 #error "You shouldn't build this"
 #endif
 
 namespace llvm {
-namespace AArch64 {
-
 const uint32_t GPRCoverageData[] = {
     (1u << AArch64::GPR32allRegClassID) | (1u << AArch64::GPR32RegClassID) |
         (1u << AArch64::GPR32spRegClassID) |
         (1u << AArch64::GPR32commonRegClassID) |
         (1u << AArch64::GPR32sponlyRegClassID) |
         (1u << AArch64::GPR64allRegClassID) | (1u << AArch64::GPR64RegClassID) |
         (1u << AArch64::GPR64spRegClassID) |
         (1u << AArch64::GPR64commonRegClassID) |
(1u << (AArch64::QQRegClassID - 32)) |
         (1u << (AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
         (1u << (AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
         (1u
          << (AArch64::
                  QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID -
              32))};
 const uint32_t CCRCoverageData[] = {1u << AArch64::CCRRegClassID, 0};
 
-const RegisterBank::DataTy RegisterBankData[] = {
+const RegisterBank::DataTy AArch64GenRegisterBankInfo::RegisterBankData[] = {
     {AArch64::GPRRegBankID, "GPR", 64, GPRCoverageData},
     {AArch64::FPRRegBankID, "FPR", 512, FPRCoverageData},
     {AArch64::CCRRegBankID, "CCR", 32, CCRCoverageData},
 };
 
-RegisterBank GPRRegBank(RegisterBankData[GPRRegBankID]);
-RegisterBank FPRRegBank(RegisterBankData[FPRRegBankID]);
-RegisterBank CCRRegBank(RegisterBankData[CCRRegBankID]);
-
-RegisterBank *RegBanks[] = {&GPRRegBank, &FPRRegBank, &CCRRegBank};
-
-// PartialMappings.
-enum PartialMappingIdx {
-  PMI_None = -1,
-  PMI_GPR32 = 1,
-  PMI_GPR64,
-  PMI_FPR32,
-  PMI_FPR64,
-  PMI_FPR128,
-  PMI_FPR256,
-  PMI_FPR512,
-  PMI_FirstGPR = PMI_GPR32,
-  PMI_LastGPR = PMI_GPR64,
-  PMI_FirstFPR = PMI_FPR32,
-  PMI_LastFPR = PMI_FPR512,
-  PMI_Min = PMI_FirstGPR,
-};
+RegisterBank AArch64GenRegisterBankInfo::GPRRegBank(AArch64GenRegisterBankInfo::RegisterBankData[AArch64::GPRRegBankID]);
+RegisterBank AArch64GenRegisterBankInfo::FPRRegBank(AArch64GenRegisterBankInfo::RegisterBankData[AArch64::FPRRegBankID]);
+RegisterBank AArch64GenRegisterBankInfo::CCRRegBank(AArch64GenRegisterBankInfo::RegisterBankData[AArch64::CCRRegBankID]);
+
+RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = {
+    &AArch64GenRegisterBankInfo::GPRRegBank,
+    &AArch64GenRegisterBankInfo::FPRRegBank,
+    &AArch64GenRegisterBankInfo::CCRRegBank};
 
+namespace AArch64 {
 static unsigned getRegBankBaseIdxOffset(unsigned Size) {
   assert(Size && "0-sized type!!");
   // Make anything smaller than 32 gets 32
   Size = ((Size + 31) / 32) * 32;
   // 32 is 0, 64 is 1, 128 is 2, and so on.
   return Log2_32(Size) - /*Log2_32(32)=*/ 5;
 }
+}
 
-RegisterBankInfo::PartialMapping PartMappings[] {
+RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
     /* StartIdx, Length, RegBank */
     // 0: GPR 32-bit value.
-  {0, 32, GPRRegBank},
+    {0, 32, AArch64GenRegisterBankInfo::GPRRegBank},
     // 1: GPR 64-bit value.
-  {0, 64, GPRRegBank},
+    {0, 64, AArch64GenRegisterBankInfo::GPRRegBank},
     // 2: FPR 32-bit value.
-  {0, 32, FPRRegBank},
+    {0, 32, AArch64GenRegisterBankInfo::FPRRegBank},
     // 3: FPR 64-bit value.
-  {0, 64, FPRRegBank},
+    {0, 64, AArch64GenRegisterBankInfo::FPRRegBank},
     // 4: FPR 128-bit value.
-  {0, 128, FPRRegBank},
+    {0, 128, AArch64GenRegisterBankInfo::FPRRegBank},
     // 5: FPR 256-bit value.
-  {0, 256, FPRRegBank},
+    {0, 256, AArch64GenRegisterBankInfo::FPRRegBank},
     // 6: FPR 512-bit value.
-  {0, 512, FPRRegBank}
-};
-
-enum ValueMappingIdx {
-  First3OpsIdx = 0,
-  Last3OpsIdx = 18,
-  DistanceBetweenRegBanks = 3,
-  FirstCrossRegCpyIdx = 21,
-  LastCrossRegCpyIdx = 27,
-  DistanceBetweenCrossRegCpy = 2
-};
+    {0, 512, AArch64GenRegisterBankInfo::FPRRegBank}};
 
 // ValueMappings.
-RegisterBankInfo::ValueMapping ValMappings[]{
+RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::ValMappings[]{
     /* BreakDown, NumBreakDowns */
     // 3-operands instructions (all binary operations should end up with one of
     // those mapping).
     // 0: GPR 32-bit value. <-- This must match First3OpsIdx.
-    {&PartMappings[PMI_GPR32 - PMI_Min], 1},
-    {&PartMappings[PMI_GPR32 - PMI_Min], 1},
-    {&PartMappings[PMI_GPR32 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
     // 3: GPR 64-bit value.
-    {&PartMappings[PMI_GPR64 - PMI_Min], 1},
-    {&PartMappings[PMI_GPR64 - PMI_Min], 1},
-    {&PartMappings[PMI_GPR64 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
     // 6: FPR 32-bit value.
-    {&PartMappings[PMI_FPR32 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR32 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR32 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
     // 9: FPR 64-bit value.
-    {&PartMappings[PMI_FPR64 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR64 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR64 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
     // 12: FPR 128-bit value.
-    {&PartMappings[PMI_FPR128 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR128 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR128 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
     // 15: FPR 256-bit value.
-    {&PartMappings[PMI_FPR256 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR256 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR256 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
     // 18: FPR 512-bit value. <-- This must match Last3OpsIdx.
-    {&PartMappings[PMI_FPR512 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR512 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR512 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
     // Cross register bank copies.
     // 21: GPR 32-bit value to FPR 32-bit value. <-- This must match
     //                                               FirstCrossRegCpyIdx.
-    {&PartMappings[PMI_GPR32 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR32 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
     // 23: GPR 64-bit value to FPR 64-bit value.
-    {&PartMappings[PMI_GPR64 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR64 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
     // 25: FPR 32-bit value to GPR 32-bit value.
-    {&PartMappings[PMI_FPR32 - PMI_Min], 1},
-    {&PartMappings[PMI_GPR32 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
     // 27: FPR 64-bit value to GPR 64-bit value. <-- This must match
     //                                               LastCrossRegCpyIdx.
-    {&PartMappings[PMI_FPR64 - PMI_Min], 1},
-    {&PartMappings[PMI_GPR64 - PMI_Min], 1}
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1}
 };
 
+namespace AArch64 {
 /// Get the pointer to the ValueMapping representing the RegisterBank
 /// at \p RBIdx with a size of \p Size.
 ///
 /// The returned mapping works for instructions with the same kind of
 /// operands for up to 3 operands.
 ///
 /// \pre \p RBIdx != PartialMappingIdx::None
 const RegisterBankInfo::ValueMapping *
-getValueMapping(PartialMappingIdx RBIdx, unsigned Size) {
-  assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
-  unsigned ValMappingIdx = First3OpsIdx +
-                           (RBIdx - AArch64::PartialMappingIdx::PMI_Min +
-                            getRegBankBaseIdxOffset(Size)) *
-                               ValueMappingIdx::DistanceBetweenRegBanks;
-  assert(ValMappingIdx >= AArch64::First3OpsIdx &&
-         ValMappingIdx <= AArch64::Last3OpsIdx && "Mapping out of bound");
+getValueMapping(AArch64GenRegisterBankInfo::PartialMappingIdx RBIdx,
+                unsigned Size) {
+  assert(RBIdx != AArch64GenRegisterBankInfo::PartialMappingIdx::PMI_None &&
+         "No mapping needed for that");
+  unsigned ValMappingIdx =
+      AArch64GenRegisterBankInfo::First3OpsIdx +
+      (RBIdx - AArch64GenRegisterBankInfo::PartialMappingIdx::PMI_Min +
+          AArch64GenRegisterBankInfo::ValueMappingIdx::DistanceBetweenRegBanks;
+  assert(ValMappingIdx >= AArch64GenRegisterBankInfo::First3OpsIdx &&
+         ValMappingIdx <= AArch64GenRegisterBankInfo::Last3OpsIdx &&
+         "Mapping out of bound");
 
-  return &ValMappings[ValMappingIdx];
+  return &AArch64GenRegisterBankInfo::ValMappings[ValMappingIdx];
 }
 
 /// Get the pointer to the ValueMapping of the operands of a copy
 /// instruction from a GPR or FPR register to a GPR or FPR register
 /// with a size of \p Size.
 ///
 /// If \p DstIsGPR is true, the destination of the copy is on GPR,
 /// otherwise it is on FPR. Same thing for \p SrcIsGPR.
 const RegisterBankInfo::ValueMapping *
 getCopyMapping(bool DstIsGPR, bool SrcIsGPR, unsigned Size) {
-  PartialMappingIdx DstRBIdx = DstIsGPR ? PMI_FirstGPR : PMI_FirstFPR;
-  PartialMappingIdx SrcRBIdx = SrcIsGPR ? PMI_FirstGPR : PMI_FirstFPR;
+  AArch64GenRegisterBankInfo::PartialMappingIdx DstRBIdx =
+      DstIsGPR ? AArch64GenRegisterBankInfo::PMI_FirstGPR
+               : AArch64GenRegisterBankInfo::PMI_FirstFPR;
+  AArch64GenRegisterBankInfo::PartialMappingIdx SrcRBIdx =
+      SrcIsGPR ? AArch64GenRegisterBankInfo::PMI_FirstGPR
+               : AArch64GenRegisterBankInfo::PMI_FirstFPR;
   if (DstRBIdx == SrcRBIdx)
     return getValueMapping(DstRBIdx, Size);
   assert(Size <= 64 && "GPR cannot handle that size");
-  unsigned ValMappingIdx =
-      FirstCrossRegCpyIdx +
-      (DstRBIdx - PMI_Min + getRegBankBaseIdxOffset(Size)) *
-          ValueMappingIdx::DistanceBetweenCrossRegCpy;
-  assert(ValMappingIdx >= AArch64::FirstCrossRegCpyIdx &&
-         ValMappingIdx <= AArch64::LastCrossRegCpyIdx &&
+  unsigned ValMappingIdx = AArch64GenRegisterBankInfo::FirstCrossRegCpyIdx +
+                           (DstRBIdx - AArch64GenRegisterBankInfo::PMI_Min +
+                            getRegBankBaseIdxOffset(Size)) *
+                               AArch64GenRegisterBankInfo::ValueMappingIdx::
+                                   DistanceBetweenCrossRegCpy;
+  assert(ValMappingIdx >= AArch64GenRegisterBankInfo::FirstCrossRegCpyIdx &&
+         ValMappingIdx <= AArch64GenRegisterBankInfo::LastCrossRegCpyIdx &&
          "Mapping out of bound");
-  return &ValMappings[ValMappingIdx];
+  return &AArch64GenRegisterBankInfo::ValMappings[ValMappingIdx];
 }
-
 } // End AArch64 namespace.
+
+bool AArch64GenRegisterBankInfo::checkPartialMap(unsigned Idx,
+                                                 unsigned ValStartIdx,
+                                                 unsigned ValLength,
+                                                 const RegisterBank &RB) {
+  const PartialMapping &Map = PartMappings[Idx - PartialMappingIdx::PMI_Min];
+  return Map.StartIdx == ValStartIdx && Map.Length == ValLength &&
+         Map.RegBank == &RB;
+}
+
+bool AArch64GenRegisterBankInfo::checkValueMapImpl(unsigned Idx,
+                                                   unsigned FirstInBank,
+                                                   unsigned Size,
+                                                   unsigned Offset) {
+  unsigned PartialMapBaseIdx = Idx - PartialMappingIdx::PMI_Min;
+  const ValueMapping &Map =
+      AArch64::getValueMapping((PartialMappingIdx)FirstInBank, Size)[Offset];
+  return Map.BreakDown == &PartMappings[PartialMapBaseIdx] &&
+         Map.NumBreakDowns == 1;
+}
+
 } // End llvm namespace.

lib/Target/AArch64/AArch64RegisterBankInfo.h

 
 namespace AArch64 {
 enum {
   GPRRegBankID = 0, /// General Purpose Registers: W, X.
   FPRRegBankID = 1, /// Floating Point/Vector Registers: B, H, S, D, Q.
   CCRRegBankID = 2, /// Conditional register: NZCV.
   NumRegisterBanks
 };
-
-extern RegisterBank GPRRegBank;
-extern RegisterBank FPRRegBank;
-extern RegisterBank CCRRegBank;
 } // End AArch64 namespace.
 
+class AArch64GenRegisterBankInfo : public RegisterBankInfo {
+private:
+  static const RegisterBank::DataTy RegisterBankData[];
+  static RegisterBank *RegBanks[];
+
+protected:
+  AArch64GenRegisterBankInfo();
+
+  static RegisterBank GPRRegBank;
+  static RegisterBank FPRRegBank;
+  static RegisterBank CCRRegBank;
+
+public:
+  static RegisterBankInfo::PartialMapping PartMappings[];
+  static RegisterBankInfo::ValueMapping ValMappings[];
+  static bool checkPartialMap(unsigned Idx, unsigned ValStartIdx,
+                              unsigned ValLength, const RegisterBank &RB);
+  static bool checkValueMapImpl(unsigned Idx, unsigned FirstInBank,
+                                unsigned Size, unsigned Offset);
+  enum PartialMappingIdx {
+    PMI_None = -1,
+    PMI_GPR32 = 1,
+    PMI_GPR64,
+    PMI_FPR32,
+    PMI_FPR64,
+    PMI_FPR128,
+    PMI_FPR256,
+    PMI_FPR512,
+    PMI_FirstGPR = PMI_GPR32,
+    PMI_LastGPR = PMI_GPR64,
+    PMI_FirstFPR = PMI_FPR32,
+    PMI_LastFPR = PMI_FPR512,
+    PMI_Min = PMI_FirstGPR,
+  };
+
+  enum ValueMappingIdx {
+    First3OpsIdx = 0,
+    Last3OpsIdx = 18,
+    DistanceBetweenRegBanks = 3,
+    FirstCrossRegCpyIdx = 21,
+    LastCrossRegCpyIdx = 27,
+    DistanceBetweenCrossRegCpy = 2
+  };
+
+  static void assertPartialMappingIdx(PartialMappingIdx FirstAlias,
+                                      PartialMappingIdx LastAlias,
+                                      std::vector<PartialMappingIdx> Order) {
+    assert(Order.front() == FirstAlias && "First enumerator is not first");
+    assert(Order.back() == LastAlias && "Last enumerator is not last");
+    assert(Order.front() <= Order.back() && "Enumerators are backwards is backward");
+
+    PartialMappingIdx Previous = Order.front();
+    bool First = true;
+    for (const auto &Current : Order) {
+      if (First) {
+        First = false;
+        continue;
+      }
+      assert(Previous + 1 == Current && "Indices are not properly ordered");
+      Previous = Current;
+    }
+  }
+
+};
+
 /// This class provides the information for the target register banks.
-class AArch64RegisterBankInfo final : public RegisterBankInfo {
+class AArch64RegisterBankInfo final : public AArch64GenRegisterBankInfo {
   /// See RegisterBankInfo::applyMapping.
   void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
 
   /// Get an instruction mapping where all the operands map to
   /// the same register bank and have similar size.
   ///
   /// \pre MI.getNumOperands() <= 3
   ///

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

 #include "AArch64GenRegisterBankInfo.def"
 
 using namespace llvm;
 
 #ifndef LLVM_BUILD_GLOBAL_ISEL
 #error "You shouldn't build this"
 #endif
 
+AArch64GenRegisterBankInfo::AArch64GenRegisterBankInfo()
+    : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks) {}
+
 AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
-    : RegisterBankInfo(AArch64::RegBanks, AArch64::NumRegisterBanks) {
+    : AArch64GenRegisterBankInfo() {
   static bool AlreadyInit = false;
   // We have only one set of register banks, whatever the subtarget
   // is. Therefore, the initialization of the RegBanks table should be
   // done only once. Indeed the table of all register banks
   // (AArch64::RegBanks) is unique in the compiler. At some point, it
   // will get tablegen'ed and the whole constructor becomes empty.
   if (AlreadyInit)
     return;
   AlreadyInit = true;
 
   const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
   (void)RBGPR;
-  assert(&AArch64::GPRRegBank == &RBGPR &&
-         "The order in RegBanks is messed up");
+  assert(&GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
 
   const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
   (void)RBFPR;
-  assert(&AArch64::FPRRegBank == &RBFPR &&
-         "The order in RegBanks is messed up");
+  assert(&FPRRegBank == &RBFPR && "The order in RegBanks is messed up");
 
   const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
   (void)RBCCR;
-  assert(&AArch64::CCRRegBank == &RBCCR &&
-         "The order in RegBanks is messed up");
+  assert(&CCRRegBank == &RBCCR && "The order in RegBanks is messed up");
 
   // Finish the initialization of the register banks.
   for (auto &ID : {AArch64::GPRRegBankID, AArch64::FPRRegBankID, AArch64::CCRRegBankID})
     getRegBank(ID).finishInit(TRI);
 
   // The GPR register bank is fully defined by all the registers in
   // GR64all + its subclasses.
   assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
assert(RBFPR.getSize() == 512 &&
          "FPRs should hold up to 512-bit via QQQQ sequence");
 
   assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
          "Class not added?");
   assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
 
   // Check that the TableGen'ed like file is in sync we our expectations.
   // First, the Idx.
-  assert(AArch64::PartialMappingIdx::PMI_GPR32 ==
-             AArch64::PartialMappingIdx::PMI_FirstGPR &&
-         "GPR32 index not first in the GPR list");
-  assert(AArch64::PartialMappingIdx::PMI_GPR64 ==
-             AArch64::PartialMappingIdx::PMI_LastGPR &&
-         "GPR64 index not last in the GPR list");
-  assert(AArch64::PartialMappingIdx::PMI_FirstGPR <=
-             AArch64::PartialMappingIdx::PMI_LastGPR &&
-         "GPR list is backward");
-  assert(AArch64::PartialMappingIdx::PMI_FPR32 ==
-             AArch64::PartialMappingIdx::PMI_FirstFPR &&
-         "FPR32 index not first in the FPR list");
-  assert(AArch64::PartialMappingIdx::PMI_FPR512 ==
-             AArch64::PartialMappingIdx::PMI_LastFPR &&
-         "FPR512 index not last in the FPR list");
-  assert(AArch64::PartialMappingIdx::PMI_FirstFPR <=
-             AArch64::PartialMappingIdx::PMI_LastFPR &&
-         "FPR list is backward");
-  assert(AArch64::PartialMappingIdx::PMI_FPR32 + 1 ==
-             AArch64::PartialMappingIdx::PMI_FPR64 &&
-         AArch64::PartialMappingIdx::PMI_FPR64 + 1 ==
-             AArch64::PartialMappingIdx::PMI_FPR128 &&
-         AArch64::PartialMappingIdx::PMI_FPR128 + 1 ==
-             AArch64::PartialMappingIdx::PMI_FPR256 &&
-         AArch64::PartialMappingIdx::PMI_FPR256 + 1 ==
-             AArch64::PartialMappingIdx::PMI_FPR512 &&
-         "FPR indices not properly ordered");
+  assertPartialMappingIdx(PMI_FirstGPR, PMI_LastGPR, {PMI_GPR32, PMI_GPR64});
+  assertPartialMappingIdx(
+      PMI_FirstFPR, PMI_LastFPR,
+      {PMI_FPR32, PMI_FPR64, PMI_FPR128, PMI_FPR256, PMI_FPR512});
 // Now, the content.
 // Check partial mapping.
 #define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB)                      \
   do {                                                                         \
-    const PartialMapping &Map =                                                \
-        AArch64::PartMappings[AArch64::PartialMappingIdx::Idx -                \
-                              AArch64::PartialMappingIdx::PMI_Min];            \
-    (void)Map;                                                                 \
-    assert(Map.StartIdx == ValStartIdx && Map.Length == ValLength &&           \
-           Map.RegBank == &RB && #Idx " is incorrectly initialized");          \
+    assert(                                                                    \
+        checkPartialMap(PartialMappingIdx::Idx, ValStartIdx, ValLength, RB) && \
+        #Idx " is incorrectly initialized");                                   \
   } while (0)
 
   CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR);
   CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR);
   CHECK_PARTIALMAP(PMI_FPR32, 0, 32, RBFPR);
   CHECK_PARTIALMAP(PMI_FPR64, 0, 64, RBFPR);
   CHECK_PARTIALMAP(PMI_FPR128, 0, 128, RBFPR);
   CHECK_PARTIALMAP(PMI_FPR256, 0, 256, RBFPR);
   CHECK_PARTIALMAP(PMI_FPR512, 0, 512, RBFPR);
 
 // Check value mapping.
 #define CHECK_VALUEMAP_IMPL(RBName, Size, Offset)                              \
   do {                                                                         \
-    unsigned PartialMapBaseIdx =                                               \
-        AArch64::PartialMappingIdx::PMI_##RBName##Size -                       \
-        AArch64::PartialMappingIdx::PMI_Min;                                   \
-    (void)PartialMapBaseIdx;                                                   \
-    const ValueMapping &Map = AArch64::getValueMapping(                        \
-        AArch64::PartialMappingIdx::PMI_First##RBName, Size)[Offset];          \
-    (void)Map;                                                                 \
-    assert(Map.BreakDown == &AArch64::PartMappings[PartialMapBaseIdx] &&       \
-           Map.NumBreakDowns == 1 && #RBName #Size                             \
-           " " #Offset " is incorrectly initialized");                         \
+    assert(checkValueMapImpl(PartialMappingIdx::PMI_##RBName##Size,            \
+                             PartialMappingIdx::PMI_First##RBName, Size,       \
+                             Offset) &&                                        \
+           #RBName #Size " " #Offset " is incorrectly initialized");           \
   } while (0)
 
 #define CHECK_VALUEMAP(RBName, Size) CHECK_VALUEMAP_IMPL(RBName, Size, 0)
 
   CHECK_VALUEMAP(GPR, 32);
   CHECK_VALUEMAP(GPR, 64);
   CHECK_VALUEMAP(FPR, 32);
   CHECK_VALUEMAP(FPR, 64);
#define CHECK_VALUEMAP_3OPS(RBName, Size)                                      \
   CHECK_VALUEMAP_3OPS(FPR, 32);
   CHECK_VALUEMAP_3OPS(FPR, 64);
   CHECK_VALUEMAP_3OPS(FPR, 128);
   CHECK_VALUEMAP_3OPS(FPR, 256);
   CHECK_VALUEMAP_3OPS(FPR, 512);
 
 #define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size)                 \
   do {                                                                         \
-    unsigned PartialMapDstIdx =                                                \
-        AArch64::PMI_##RBNameDst##Size - AArch64::PMI_Min;                     \
-    unsigned PartialMapSrcIdx =                                                \
-        AArch64::PMI_##RBNameSrc##Size - AArch64::PMI_Min;                     \
-    (void) PartialMapDstIdx;                                                   \
-    (void) PartialMapSrcIdx;                                                   \
-    const ValueMapping *Map = AArch64::getCopyMapping(                         \
-        AArch64::PMI_First##RBNameDst == AArch64::PMI_FirstGPR,                \
-        AArch64::PMI_First##RBNameSrc == AArch64::PMI_FirstGPR, Size);         \
-    (void) Map;                                                                \
-    assert(Map[0].BreakDown == &AArch64::PartMappings[PartialMapDstIdx] &&     \
+    unsigned PartialMapDstIdx = PMI_##RBNameDst##Size - PMI_Min;               \
+    unsigned PartialMapSrcIdx = PMI_##RBNameSrc##Size - PMI_Min;               \
+    (void)PartialMapDstIdx;                                                    \
+    (void)PartialMapSrcIdx;                                                    \
+    const ValueMapping *Map =                                                  \
+        AArch64::getCopyMapping(PMI_First##RBNameDst == PMI_FirstGPR,          \
+                                PMI_First##RBNameSrc == PMI_FirstGPR, Size);   \
+    (void)Map;                                                                 \
+    assert(Map[0].BreakDown ==                                                 \
+               &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] &&  \
            Map[0].NumBreakDowns == 1 && #RBNameDst #Size                       \
            " Dst is incorrectly initialized");                                 \
-    assert(Map[1].BreakDown == &AArch64::PartMappings[PartialMapSrcIdx] &&     \
+    assert(Map[1].BreakDown ==                                                 \
+               &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] &&  \
            Map[1].NumBreakDowns == 1 && #RBNameSrc #Size                       \
            " Src is incorrectly initialized");                                 \
                                                                                \
   } while (0)
 
   CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 32);
   CHECK_VALUEMAP_CROSSREGCPY(GPR, FPR, 32);
   CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 64);
unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A,
   // What do we do with different size?
   // copy are same size.
   // Will introduce other hooks for different size:
   // * extract cost.
   // * build_sequence cost.
 
   // Copy from (resp. to) GPR to (resp. from) FPR involves FMOV.
   // FIXME: This should be deduced from the scheduling model.
-  if (&A == &AArch64::GPRRegBank && &B == &AArch64::FPRRegBank)
+  if (&A == &GPRRegBank && &B == &FPRRegBank)
     // FMOVXDr or FMOVWSr.
     return 5;
-  if (&A == &AArch64::FPRRegBank && &B == &AArch64::GPRRegBank)
+  if (&A == &FPRRegBank && &B == &GPRRegBank)
     // FMOVDXr or FMOVSWr.
     return 4;
 
   return RegisterBankInfo::copyCost(A, B, Size);
 }
 
 const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass(
     const TargetRegisterClass &RC) const {
if (Size != 32 && Size != 64)
       break;
 
     // If the instruction has any implicit-defs or uses,
     // do not mess with it.
     if (MI.getNumOperands() != 3)
       break;
     InstructionMappings AltMappings;
     InstructionMapping GPRMapping(
-        /*ID*/ 1, /*Cost*/ 1,
-        AArch64::getValueMapping(AArch64::PMI_FirstGPR, Size),
+        /*ID*/ 1, /*Cost*/ 1, AArch64::getValueMapping(PMI_FirstGPR, Size),
         /*NumOperands*/ 3);
     InstructionMapping FPRMapping(
-        /*ID*/ 2, /*Cost*/ 1,
-        AArch64::getValueMapping(AArch64::PMI_FirstFPR, Size),
+        /*ID*/ 2, /*Cost*/ 1, AArch64::getValueMapping(PMI_FirstFPR, Size),
         /*NumOperands*/ 3);
 
     AltMappings.emplace_back(std::move(GPRMapping));
     AltMappings.emplace_back(std::move(FPRMapping));
     return AltMappings;
   }
   case TargetOpcode::G_BITCAST: {
     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
InstructionMapping GPRMapping(
         AArch64::getCopyMapping(/*DstIsGPR*/ true, /*SrcIsGPR*/ true, Size),
         /*NumOperands*/ 2);
     InstructionMapping FPRMapping(
         /*ID*/ 2, /*Cost*/ 1,
         AArch64::getCopyMapping(/*DstIsGPR*/ false, /*SrcIsGPR*/ false, Size),
         /*NumOperands*/ 2);
     InstructionMapping GPRToFPRMapping(
         /*ID*/ 3,
-        /*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
+        /*Cost*/ copyCost(GPRRegBank, FPRRegBank, Size),
         AArch64::getCopyMapping(/*DstIsGPR*/ false, /*SrcIsGPR*/ true, Size),
         /*NumOperands*/ 2);
     InstructionMapping FPRToGPRMapping(
         /*ID*/ 3,
-        /*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
+        /*Cost*/ copyCost(GPRRegBank, FPRRegBank, Size),
         AArch64::getCopyMapping(/*DstIsGPR*/ true, /*SrcIsGPR*/ false, Size),
         /*NumOperands*/ 2);
 
     AltMappings.emplace_back(std::move(GPRMapping));
     AltMappings.emplace_back(std::move(FPRMapping));
     AltMappings.emplace_back(std::move(GPRToFPRMapping));
     AltMappings.emplace_back(std::move(FPRToGPRMapping));
     return AltMappings;
   }
   case TargetOpcode::G_LOAD: {
     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
     if (Size != 64)
       break;
 
     // If the instruction has any implicit-defs or uses,
     // do not mess with it.
     if (MI.getNumOperands() != 2)
       break;
 
     InstructionMappings AltMappings;
     InstructionMapping GPRMapping(
         /*ID*/ 1, /*Cost*/ 1,
-        getOperandsMapping(
-            {AArch64::getValueMapping(AArch64::PMI_FirstGPR, Size),
+        getOperandsMapping({AArch64::getValueMapping(PMI_FirstGPR, Size),
                             // Addresses are GPR 64-bit.
-             AArch64::getValueMapping(AArch64::PMI_FirstGPR, 64)}),
+                            AArch64::getValueMapping(PMI_FirstGPR, 64)}),
         /*NumOperands*/ 2);
     InstructionMapping FPRMapping(
         /*ID*/ 2, /*Cost*/ 1,
-        getOperandsMapping(
-            {AArch64::getValueMapping(AArch64::PMI_FirstFPR, Size),
+        getOperandsMapping({AArch64::getValueMapping(PMI_FirstFPR, Size),
                             // Addresses are GPR 64-bit.
-             AArch64::getValueMapping(AArch64::PMI_FirstGPR, 64)}),
+                            AArch64::getValueMapping(PMI_FirstGPR, 64)}),
         /*NumOperands*/ 2);
 
     AltMappings.emplace_back(std::move(GPRMapping));
     AltMappings.emplace_back(std::move(FPRMapping));
     return AltMappings;
   }
   default:
     break;
assert(AArch64::getRegBankBaseIdxOffset(OpTy.getSizeInBits()) ==
                AArch64::getRegBankBaseIdxOffset(Size) &&
            "Operand has incompatible size");
     bool OpIsFPR = OpTy.isVector() || isPreISelGenericFloatingPointOpcode(Opc);
     (void)OpIsFPR;
     assert(IsFPR == OpIsFPR && "Operand has incompatible type");
   }
 #endif // End NDEBUG.
 
-  AArch64::PartialMappingIdx RBIdx =
-      IsFPR ? AArch64::PMI_FirstFPR : AArch64::PMI_FirstGPR;
+  PartialMappingIdx RBIdx = IsFPR ? PMI_FirstFPR : PMI_FirstGPR;
 
   return InstructionMapping{DefaultMappingID, 1,
                             AArch64::getValueMapping(RBIdx, Size), NumOperands};
 }
 
 RegisterBankInfo::InstructionMapping
 AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   const unsigned Opc = MI.getOpcode();
AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_FDIV:
     return getSameKindOfOperandsMapping(MI);
   case TargetOpcode::G_BITCAST: {
     LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
     LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
     unsigned Size = DstTy.getSizeInBits();
     bool DstIsGPR = !DstTy.isVector();
     bool SrcIsGPR = !SrcTy.isVector();
-    const RegisterBank &DstRB =
-        DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
-    const RegisterBank &SrcRB =
-        SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
+    const RegisterBank &DstRB = DstIsGPR ? GPRRegBank : FPRRegBank;
+    const RegisterBank &SrcRB = SrcIsGPR ? GPRRegBank : FPRRegBank;
     return InstructionMapping{DefaultMappingID, copyCost(DstRB, SrcRB, Size),
                               AArch64::getCopyMapping(DstIsGPR, SrcIsGPR, Size),
                               /*NumOperands*/ 2};
   }
   case TargetOpcode::G_SEQUENCE:
     // FIXME: support this, but the generic code is really not going to do
     // anything sane.
     return InstructionMapping();
   default:
     break;
   }
 
   unsigned NumOperands = MI.getNumOperands();
 
   // Track the size and bank of each register.  We don't do partial mappings.
   SmallVector<unsigned, 4> OpSize(NumOperands);
-  SmallVector<AArch64::PartialMappingIdx, 4> OpRegBankIdx(NumOperands);
+  SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands);
   for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
     auto &MO = MI.getOperand(Idx);
     if (!MO.isReg())
       continue;
 
     LLT Ty = MRI.getType(MO.getReg());
     OpSize[Idx] = Ty.getSizeInBits();
 
     // As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs.
     // For floating-point instructions, scalars go in FPRs.
     if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc))
-      OpRegBankIdx[Idx] = AArch64::PMI_FirstFPR;
+      OpRegBankIdx[Idx] = PMI_FirstFPR;
     else
-      OpRegBankIdx[Idx] = AArch64::PMI_FirstGPR;
+      OpRegBankIdx[Idx] = PMI_FirstGPR;
   }
 
   unsigned Cost = 1;
   // Some of the floating-point instructions have mixed GPR and FPR operands:
   // fine-tune the computed mapping.
   switch (Opc) {
   case TargetOpcode::G_SITOFP:
   case TargetOpcode::G_UITOFP: {
-    OpRegBankIdx = {AArch64::PMI_FirstFPR, AArch64::PMI_FirstGPR};
+    OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR};
     break;
   }
   case TargetOpcode::G_FPTOSI:
   case TargetOpcode::G_FPTOUI: {
-    OpRegBankIdx = {AArch64::PMI_FirstGPR, AArch64::PMI_FirstFPR};
+    OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
     break;
   }
   case TargetOpcode::G_FCMP: {
-    OpRegBankIdx = {AArch64::PMI_FirstGPR,
-                    /* Predicate */ AArch64::PMI_None, AArch64::PMI_FirstFPR,
-                    AArch64::PMI_FirstFPR};
+    OpRegBankIdx = {PMI_FirstGPR,
+                    /* Predicate */ PMI_None, PMI_FirstFPR, PMI_FirstFPR};
     break;
   }
   case TargetOpcode::G_BITCAST: {
     // This is going to be a cross register bank copy and this is expensive.
     if (OpRegBankIdx[0] != OpRegBankIdx[1])
-      Cost =
-          copyCost(*AArch64::PartMappings[OpRegBankIdx[0]].RegBank,
-                   *AArch64::PartMappings[OpRegBankIdx[1]].RegBank, OpSize[0]);
+      Cost = copyCost(
+          *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[0]].RegBank,
+          *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[1]].RegBank,
+          OpSize[0]);
     break;
   }
   case TargetOpcode::G_LOAD: {
     // Loading in vector unit is slightly more expensive.
     // This is actually only true for the LD1R and co instructions,
     // but anyway for the fast mode this number does not matter and
     // for the greedy mode the cost of the cross bank copy will
     // offset this number.
     // FIXME: Should be derived from the scheduling model.
-    if (OpRegBankIdx[0] >= AArch64::PMI_FirstFPR)
+    if (OpRegBankIdx[0] >= PMI_FirstFPR)
       Cost = 2;
   }
   }
 
   // Finally construct the computed mapping.
   RegisterBankInfo::InstructionMapping Mapping =
       InstructionMapping{DefaultMappingID, Cost, nullptr, NumOperands};
   SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
   for (unsigned Idx = 0; Idx < NumOperands; ++Idx)
     if (MI.getOperand(Idx).isReg())
       OpdsMapping[Idx] =
           AArch64::getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]);
 
   Mapping.setOperandsMapping(getOperandsMapping(OpdsMapping));
   return Mapping;
 }