Target: Replace most PatLeaf patterns that match immediates with ImmLeaf patterns. NFCI.

[pcc]

Summary

This requires that we add two new capabilities to ImmLeaf: the ability to
zero extend the immediate instead of sign extending it, and the ability to
select an immediate of any width. This was done by introducing new classes
that expose those capabilities.

Depends on D25301

[ast]

nice cleanup. bpf bits look fine

[• tstellarAMD]

LGTM.

[jpienaar]

LGTM

llvm/include/llvm/Target/TargetSelectionDAG.td

 
 // PatLeaf's are pattern fragments that have no operands.  This is just a helper
 // to define immediates and other common things concisely.
 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
  : PatFrag<(ops), frag, pred, xform>;
 
 
 // ImmLeaf is a pattern fragment with a constraint on the immediate.  The
-// constraint is a function that is run on the immediate (always with the value
-// sign extended out to an int64_t) as Imm.  For example:
+// constraint is a function that is run on the immediate (which is sign extended
+// to an int64_t if Signed is set, or otherwise zero extended to a uint64_t) as
+// Imm.  For example:
 //
 //  def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>;
 //
 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also
 // is preferred over using PatLeaf because it allows the code generator to
 // reason more about the constraint.
 //
 // If FastIsel should ignore all instructions that have an operand of this type,
 // the FastIselShouldIgnore flag can be set.  This is an optimization to reduce
 // the code size of the generated fast instruction selector.
 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
   : PatFrag<(ops), (vt imm), [{}], xform> {
   let ImmediateCode = pred;
   bit FastIselShouldIgnore = 0;
+  bit Signed = 1;
 }
 
+class ZExtImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
+  : ImmLeaf<vt, pred, xform> {
+  let Signed = 0;
+}
+
+class AnyImmLeaf<code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
+  : PatFrag<(ops), (imm), [{}], xform> {
+  let ImmediateCode = pred;
+  bit FastIselShouldIgnore = 0;
+  bit Signed = 1;
+}
+
+class ZExtAnyImmLeaf<code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
+  : AnyImmLeaf<pred, xform> {
+  let Signed = 0;
+}
 
 // Leaf fragments.
 
 def vtInt      : PatLeaf<(vt),  [{ return N->getVT().isInteger(); }]>;
 def vtFP       : PatLeaf<(vt),  [{ return N->getVT().isFloatingPoint(); }]>;
 
 def immAllOnesV: PatLeaf<(build_vector), [{
   return ISD::isBuildVectorAllOnes(N);

llvm/lib/Target/AArch64/AArch64InstrFormats.td

let DiagnosticType = "LogicalSecondSource" in {
   }
   def LogicalImm32NotOperand : AsmOperandClass {
     let Name = "LogicalImm32Not";
   }
   def LogicalImm64NotOperand : AsmOperandClass {
     let Name = "LogicalImm64Not";
   }
 }
-def logical_imm32 : Operand<i32>, PatLeaf<(imm), [{
-  return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 32);
+def logical_imm32 : Operand<i32>, ZExtImmLeaf<i32, [{
+  return AArch64_AM::isLogicalImmediate(Imm, 32);
 }], logical_imm32_XFORM> {
   let PrintMethod = "printLogicalImm32";
   let ParserMatchClass = LogicalImm32Operand;
 }
-def logical_imm64 : Operand<i64>, PatLeaf<(imm), [{
-  return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 64);
+def logical_imm64 : Operand<i64>, ZExtImmLeaf<i64, [{
+  return AArch64_AM::isLogicalImmediate(Imm, 64);
 }], logical_imm64_XFORM> {
   let PrintMethod = "printLogicalImm64";
   let ParserMatchClass = LogicalImm64Operand;
 }
 def logical_imm32_not : Operand<i32> {
   let ParserMatchClass = LogicalImm32NotOperand;
 }
 def logical_imm64_not : Operand<i64> {

llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

 // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
 class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
   (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
   (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
 >;
 
 // Bitfield extract patterns
 
-def IMMZeroBasedBitfieldMask : PatLeaf <(imm), [{
-  return isMask_32(N->getZExtValue());
+def IMMZeroBasedBitfieldMask : AnyImmLeaf<[{
+  return isMask_32(Imm);
 }]>;
 
 def IMMPopCount : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(countPopulation(N->getZExtValue()), SDLoc(N),
                                    MVT::i32);
 }]>;
 
 class BFEPattern <Instruction BFE, Instruction MOV> : Pat <

llvm/lib/Target/AMDGPU/R600Instructions.td

InstR600 <(outs R600_Reg32:$dst),
           asm,
           pattern,
           itin>;
 
 
 
 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
 
-def TEX_SHADOW : PatLeaf<
-  (imm),
-  [{uint32_t TType = (uint32_t)N->getZExtValue();
-    return (TType >= 6 && TType <= 8) || TType == 13;
+def TEX_SHADOW : AnyImmLeaf<
+  [{
+    return (Imm >= 6 && Imm <= 8) || Imm == 13;
   }]
 >;
 
-def TEX_RECT : PatLeaf<
-  (imm),
-  [{uint32_t TType = (uint32_t)N->getZExtValue();
-    return TType == 5;
+def TEX_RECT : AnyImmLeaf<
+  [{
+    return Imm == 5;
   }]
 >;
 
-def TEX_ARRAY : PatLeaf<
-  (imm),
-  [{uint32_t TType = (uint32_t)N->getZExtValue();
-    return TType == 9 || TType == 10 || TType == 16;
+def TEX_ARRAY : AnyImmLeaf<
+  [{
+    return Imm == 9 || Imm == 10 || Imm == 16;
   }]
 >;
 
-def TEX_SHADOW_ARRAY : PatLeaf<
-  (imm),
-  [{uint32_t TType = (uint32_t)N->getZExtValue();
-    return TType == 11 || TType == 12 || TType == 17;
+def TEX_SHADOW_ARRAY : AnyImmLeaf<
+  [{
+    return Imm == 11 || Imm == 12 || Imm == 17;
   }]
 >;
 
 class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask,
                  dag outs, dag ins, string asm, list<dag> pattern> :
     InstR600ISA <outs, ins, asm, pattern>,
     CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF  {
 

llvm/lib/Target/AMDGPU/SIInstrInfo.td

 }]>;
 
 // Copied from the AArch64 backend:
 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
 return CurDAG->getTargetConstant(
   N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
 }]>;
 
-def SIMM16bit : PatLeaf <(imm),
-  [{return isInt<16>(N->getSExtValue());}]
+def SIMM16bit : AnyImmLeaf<
+  [{return isInt<16>(Imm);}]
 >;
 
-def IMM20bit : PatLeaf <(imm),
-  [{return isUInt<20>(N->getZExtValue());}]
+def IMM20bit : ZExtAnyImmLeaf<
+  [{return isUInt<20>(Imm);}]
 >;
 
 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
   return isInlineImmediate(N);
 }]>;
 
 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
   return isInlineImmediate(N);

llvm/lib/Target/ARM/ARMInstrInfo.td

 }]>;
 
 /// Split a 32-bit immediate into two 16 bit parts.
 def hi16 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
                                    MVT::i32);
 }]>;
 
-def lo16AllZero : PatLeaf<(i32 imm), [{
+def lo16AllZero : ZExtImmLeaf<i32, [{
   // Returns true if all low 16-bits are 0.
-  return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
+  return (Imm & 0xFFFFUL) == 0;
 }], hi16>;
 
 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
 
 // An 'and' node with a single use.
 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
   return N->hasOneUse();
def rot_imm_XFORM: SDNodeXForm<imm, [{
   case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32);
   case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32);
   }
 }]>;
 def RotImmAsmOperand : AsmOperandClass {
   let Name = "RotImm";
   let ParserMethod = "parseRotImm";
 }
-def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
-    int32_t v = N->getZExtValue();
-    return v == 8 || v == 16 || v == 24; }],
+def rot_imm : Operand<i32>, ZExtImmLeaf<i32, [{
+    return Imm == 8 || Imm == 16 || Imm == 24; }],
     rot_imm_XFORM> {
   let PrintMethod = "printRotImmOperand";
   let ParserMatchClass = RotImmAsmOperand;
 }
 
 // shift_imm: An integer that encodes a shift amount and the type of shift
 // (asr or lsl). The 6-bit immediate encodes as:
 //    {5}     0 ==> lsl

 }
 
 // Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
 // method and such, as they are only used on aliases (Pat<> and InstAlias<>).
 // The actual parsing, encoding, decoding are handled by the destination
 // instructions, which use mod_imm.
 
 def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
-def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
-    return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
+def mod_imm_not : Operand<i32>, ZExtImmLeaf<i32, [{
+    return ARM_AM::getSOImmVal(~(uint32_t)Imm) != -1;
   }], imm_not_XFORM> {
   let ParserMatchClass = ModImmNotAsmOperand;
 }
 
 def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
-def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
-    unsigned Value = -(unsigned)N->getZExtValue();
+def mod_imm_neg : Operand<i32>, ZExtImmLeaf<i32, [{
+    unsigned Value = -(unsigned)Imm;
     return Value && ARM_AM::getSOImmVal(Value) != -1;
   }], imm_neg_XFORM> {
   let ParserMatchClass = ModImmNegAsmOperand;
 }
 
 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
-def arm_i32imm : PatLeaf<(imm), [{
+def arm_i32imm : ZExtImmLeaf<i32, [{
   if (Subtarget->useMovt(*MF))
     return true;
-  return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
+  return ARM_AM::isSOImmTwoPartVal((unsigned)Imm);
 }]>;
 
 /// imm0_1 predicate - Immediate in the range [0,1].
 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
 
 /// imm0_3 predicate - Immediate in the range [0,3].
 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }

 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
 /// e.g., 0xf000ffff
 def BitfieldAsmOperand : AsmOperandClass {
   let Name = "Bitfield";
   let ParserMethod = "parseBitfield";
 }
 
 def bf_inv_mask_imm : Operand<i32>,
-                      PatLeaf<(imm), [{
-  return ARM::isBitFieldInvertedMask(N->getZExtValue());
+                      ZExtImmLeaf<i32, [{
+  return ARM::isBitFieldInvertedMask(Imm);
 }] > {
   let EncoderMethod = "getBitfieldInvertedMaskOpValue";
   let PrintMethod = "printBitfieldInvMaskImmOperand";
   let DecoderMethod = "DecodeBitfieldMaskOperand";
   let ParserMatchClass = BitfieldAsmOperand;
 }
 
 def imm1_32_XFORM: SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
                                    MVT::i32);
 }]>;
 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
-def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
-   uint64_t Imm = N->getZExtValue();
-   return Imm > 0 && Imm <= 32;
- }],
+def imm1_32 : Operand<i32>, ZExtImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }],
     imm1_32_XFORM> {
   let PrintMethod = "printImmPlusOneOperand";
   let ParserMatchClass = Imm1_32AsmOperand;
 }
 
 def imm1_16_XFORM: SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
                                    MVT::i32);
 }]>;
 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
-def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
+def imm1_16 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 16; }],
     imm1_16_XFORM> {
   let PrintMethod = "printImmPlusOneOperand";
   let ParserMatchClass = Imm1_16AsmOperand;
 }
 
 // Define ARM specific addressing modes.
 // addrmode_imm12 := reg +/- imm12
 //

llvm/lib/Target/ARM/ARMInstrThumb.td

 // Thumb specific DAG Nodes.
 //
 
 def imm_sr_XFORM: SDNodeXForm<imm, [{
   unsigned Imm = N->getZExtValue();
   return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32);
 }]>;
 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
-def imm_sr : Operand<i32>, PatLeaf<(imm), [{
-  uint64_t Imm = N->getZExtValue();
+def imm_sr : Operand<i32>, ZExtImmLeaf<i32, [{
   return Imm > 0 && Imm <= 32;
 }], imm_sr_XFORM> {
   let PrintMethod = "printThumbSRImm";
   let ParserMatchClass = ThumbSRImmAsmOperand;
 }
 
 def imm_comp_XFORM : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N),
                                    MVT::i32);
 }]>;
 
-def imm0_7_neg : PatLeaf<(i32 imm), [{
-  return (uint32_t)-N->getZExtValue() < 8;
+def imm0_7_neg : ZExtImmLeaf<i32, [{
+  return (uint32_t)-Imm < 8;
 }], imm_neg_XFORM>;
 
-def imm0_255_comp : PatLeaf<(i32 imm), [{
-  return ~((uint32_t)N->getZExtValue()) < 256;
+def imm0_255_comp : ZExtImmLeaf<i32, [{
+  return ~((uint32_t)Imm) < 256;
 }]>;
 
+
 def imm8_255 : ImmLeaf<i32, [{
   return Imm >= 8 && Imm < 256;
 }]>;
-def imm8_255_neg : PatLeaf<(i32 imm), [{
-  unsigned Val = -N->getZExtValue();
+def imm8_255_neg : ZExtImmLeaf<i32, [{
+  unsigned Val = -Imm;
   return Val >= 8 && Val < 256;
 }], imm_neg_XFORM>;
 
 // Break imm's up into two pieces: an immediate + a left shift. This uses
 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
 // to get the val/shift pieces.
-def thumb_immshifted : PatLeaf<(imm), [{
-  return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
+def thumb_immshifted : ZExtImmLeaf<i32, [{
+  return ARM_AM::isThumbImmShiftedVal((unsigned)Imm);
 }]>;
 
 def thumb_immshifted_val : SDNodeXForm<imm, [{
   unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
   return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);
 }]>;
 
 def thumb_immshifted_shamt : SDNodeXForm<imm, [{

llvm/lib/Target/ARM/ARMInstrThumb2.td

 }
 
 // t2_so_imm_not - Match an immediate that is a complement
 // of a t2_so_imm.
 // Note: this pattern doesn't require an encoder method and such, as it's
 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
 // is handled by the destination instructions, which use t2_so_imm.
 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
-def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
-  return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
+def t2_so_imm_not : Operand<i32>, ZExtImmLeaf<i32, [{
+  return ARM_AM::getT2SOImmVal(~((uint32_t)Imm)) != -1;
 }], t2_so_imm_not_XFORM> {
   let ParserMatchClass = t2_so_imm_not_asmoperand;
 }
 
 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
 // if the upper 16 bits are zero.
 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
     APInt apIntN = N->getAPIntValue();
     if (!apIntN.isIntN(16)) return false;
     unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
     return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
   }], t2_so_imm_notSext16_XFORM> {
   let ParserMatchClass = t2_so_imm_not_asmoperand;
 }
 
 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
-def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
-  int64_t Value = -(int)N->getZExtValue();
+def t2_so_imm_neg : Operand<i32>, ZExtImmLeaf<i32, [{
+  int64_t Value = -(int)Imm;
   return Value && ARM_AM::getT2SOImmVal(Value) != -1;
 }], t2_so_imm_neg_XFORM> {
   let ParserMatchClass = t2_so_imm_neg_asmoperand;
 }
 
 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
 def imm0_4095_asmoperand: ImmAsmOperand { let Name = "Imm0_4095"; }
 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
   return Imm >= 0 && Imm < 4096;
 }]> {
   let ParserMatchClass = imm0_4095_asmoperand;
 }
 
 def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
-def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
- return (uint32_t)(-N->getZExtValue()) < 4096;
+def imm0_4095_neg : Operand<i32>, ZExtImmLeaf<i32, [{
+ return (uint32_t)(-Imm) < 4096;
 }], imm_neg_XFORM> {
   let ParserMatchClass = imm0_4095_neg_asmoperand;
 }
 
-def imm1_255_neg : PatLeaf<(i32 imm), [{
-  uint32_t Val = -N->getZExtValue();
+def imm1_255_neg : ZExtImmLeaf<i32, [{
+  uint32_t Val = -Imm;
   return (Val > 0 && Val < 255);
 }], imm_neg_XFORM>;
 
-def imm0_255_not : PatLeaf<(i32 imm), [{
-  return (uint32_t)(~N->getZExtValue()) < 255;
+def imm0_255_not : ZExtImmLeaf<i32, [{
+  return (uint32_t)(~Imm) < 255;
 }], imm_comp_XFORM>;
 
-def lo5AllOne : PatLeaf<(i32 imm), [{
+def lo5AllOne : ZExtImmLeaf<i32, [{
   // Returns true if all low 5-bits are 1.
-  return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
+  return (((uint32_t)Imm) & 0x1FUL) == 0x1FUL;
 }]>;
 
 // Define Thumb2 specific addressing modes.
 
 // t2addrmode_imm12  := reg + imm12
 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
 def t2addrmode_imm12 : MemOperand,
                        ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {

llvm/lib/Target/BPF/BPFInstrInfo.td

 
 def brtarget : Operand<OtherVT>;
 def calltarget : Operand<i64>;
 
 def u64imm   : Operand<i64> {
   let PrintMethod = "printImm64Operand";
 }
 
-def i64immSExt32 : PatLeaf<(imm),
-                [{return isInt<32>(N->getSExtValue()); }]>;
+def i64immSExt32 : ImmLeaf<i64, [{ return isInt<32>(Imm); }]>;
 
 // Addressing modes.
 def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>;
 def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>;
 
 // Address operands
 def MEMri : Operand<i64> {
   let PrintMethod = "printMemOperand";
   let EncoderMethod = "getMemoryOpValue";
   let MIOperandInfo = (ops GPR, i16imm);
 }
 
 // Conditional code predicates - used for pattern matching for jump instructions
-def BPF_CC_EQ  : PatLeaf<(imm),
-                         [{return (N->getZExtValue() == ISD::SETEQ);}]>;
-def BPF_CC_NE  : PatLeaf<(imm),
-                         [{return (N->getZExtValue() == ISD::SETNE);}]>;
-def BPF_CC_GE  : PatLeaf<(imm),
-                         [{return (N->getZExtValue() == ISD::SETGE);}]>;
-def BPF_CC_GT  : PatLeaf<(imm),
-                         [{return (N->getZExtValue() == ISD::SETGT);}]>;
-def BPF_CC_GTU : PatLeaf<(imm),
-                         [{return (N->getZExtValue() == ISD::SETUGT);}]>;
-def BPF_CC_GEU : PatLeaf<(imm),
-                         [{return (N->getZExtValue() == ISD::SETUGE);}]>;
+def BPF_CC_EQ  : ZExtImmLeaf<i64, [{return Imm == ISD::SETEQ;}]>;
+def BPF_CC_NE  : ZExtImmLeaf<i64, [{return Imm == ISD::SETNE;}]>;
+def BPF_CC_GE  : ZExtImmLeaf<i64, [{return Imm == ISD::SETGE;}]>;
+def BPF_CC_GT  : ZExtImmLeaf<i64, [{return Imm == ISD::SETGT;}]>;
+def BPF_CC_GTU : ZExtImmLeaf<i64, [{return Imm == ISD::SETUGT;}]>;
+def BPF_CC_GEU : ZExtImmLeaf<i64, [{return Imm == ISD::SETUGE;}]>;
 
 // jump instructions
-class JMP_RR<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
+class JMP_RR<bits<4> Opc, string OpcodeStr, ImmLeaf Cond>
     : InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
               !strconcat(OpcodeStr, "\t$dst, $src goto $BrDst"),
               [(BPFbrcc i64:$dst, i64:$src, Cond, bb:$BrDst)]> {
   bits<4> op;
   bits<1> BPFSrc;
   bits<4> dst;
   bits<4> src;
   bits<16> BrDst;
 
   let Inst{63-60} = op;
   let Inst{59} = BPFSrc;
   let Inst{55-52} = src;
   let Inst{51-48} = dst;
   let Inst{47-32} = BrDst;
 
   let op = Opc;
   let BPFSrc = 1;
   let BPFClass = 5; // BPF_JMP
 }
 
-class JMP_RI<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
+class JMP_RI<bits<4> Opc, string OpcodeStr, ImmLeaf Cond>
     : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
               !strconcat(OpcodeStr, "i\t$dst, $imm goto $BrDst"),
               [(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> {
   bits<4> op;
   bits<1> BPFSrc;
   bits<4> dst;
   bits<16> BrDst;
   bits<32> imm;
 
   let Inst{63-60} = op;
   let Inst{59} = BPFSrc;
   let Inst{51-48} = dst;
   let Inst{47-32} = BrDst;
   let Inst{31-0} = imm;
 
   let op = Opc;
   let BPFSrc = 0;
   let BPFClass = 5; // BPF_JMP
 }
 
-multiclass J<bits<4> Opc, string OpcodeStr, PatLeaf Cond> {
+multiclass J<bits<4> Opc, string OpcodeStr, ImmLeaf Cond> {
   def _rr : JMP_RR<Opc, OpcodeStr, Cond>;
   def _ri : JMP_RI<Opc, OpcodeStr, Cond>;
 }
 
 let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in {
 // cmp+goto instructions
 defm JEQ  : J<0x1, "jeq",  BPF_CC_EQ>;
 defm JUGT : J<0x2, "jgt", BPF_CC_GTU>;

llvm/lib/Target/Hexagon/HexagonInstrInfo.td

[], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel {
     let Inst{3-2}   = 0b00;
     let Inst{1-0}   = dst;
   }
 
 def C2_cmpeqi   : T_CMP <"cmp.eq",  0b00, 0, s10Ext>;
 def C2_cmpgti   : T_CMP <"cmp.gt",  0b01, 0, s10Ext>;
 def C2_cmpgtui  : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
 
-class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
+class T_CMP_pat <InstHexagon MI, PatFrag OpNode, ImmLeaf ImmPred>
   : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
         (MI IntRegs:$src1, ImmPred:$src2)>;
 
 def : T_CMP_pat <C2_cmpeqi,  seteq,  s10ImmPred>;
 def : T_CMP_pat <C2_cmpgti,  setgt,  s10ImmPred>;
 def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>;
 
 //===----------------------------------------------------------------------===//

 
 let accessSize = HalfWordAccess, opExtentBits = 12, opExtentAlign = 1 in
 def L2_loadalignh_io: T_loadalign_io <"memh_fifo", 0b0010, s11_1Ext>;
 
 let accessSize = ByteAccess, opExtentBits = 11 in
 def L2_loadalignb_io: T_loadalign_io <"memb_fifo", 0b0100, s11_0Ext>;
 
 // Patterns to select load-indexed (i.e. load from base+offset).
-multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
+multiclass Loadx_pat<PatFrag Load, ValueType VT, ImmLeaf ImmPred,
                      InstHexagon MI> {
   def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
   def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))),
            (VT (MI AddrFI:$fi, imm:$Off))>;
   def: Pat<(VT (Load (orisadd (i32 AddrFI:$fi), ImmPred:$Off))),
            (VT (MI AddrFI:$fi, imm:$Off))>;
   def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
            (VT (MI IntRegs:$Rs, imm:$Off))>;

 
 let Itinerary = M_tc_3x_SLOT23 in
 def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>;
 
 def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>;
 def M2_subacc : T_MType_acc_rr <"+= sub",  0b000, 0b011, 1>;
 
 class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp,
-                        PatLeaf ImmPred>
+                        ImmLeaf ImmPred>
   : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
          (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
 
 class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
   : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
          (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
 
 def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
multiclass Storexm_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
   def: Pat<(Store Value:$Rt, (orisadd (i32 IntRegs:$Rs), ImmPred:$Off)),
            (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
 }
 class Storexm_simple_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
                          InstHexagon MI>
   : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
         (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>;
 
-multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
+multiclass Storex_pat<PatFrag Store, PatFrag Value, ImmLeaf ImmPred,
                       InstHexagon MI> {
   def:  Storex_fi_pat     <Store, Value,          MI>;
   defm: Storex_fi_add_pat <Store, Value, ImmPred, MI>;
   defm: Storex_add_pat    <Store, Value, ImmPred, MI>;
 }
 
-multiclass Storexm_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
+multiclass Storexm_pat<PatFrag Store, PatFrag Value, ImmLeaf ImmPred,
                        PatFrag ValueMod, InstHexagon MI> {
   def:  Storexm_fi_pat     <Store, Value,          ValueMod, MI>;
   defm: Storexm_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>;
   defm: Storexm_add_pat    <Store, Value, ImmPred, ValueMod, MI>;
 }
 
 // Regular stores in the DAG have two operands: value and address.
 // Atomic stores also have two, but they are reversed: address, value.

llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td

 def Sext64: OutPatFrag<(ops node:$Rs),
   (i64 (A2_sxtw (i32 $Rs)))>;
 
 // Patterns to generate indexed loads with different forms of the address:
 // - frameindex,
 // - base + offset,
 // - base (without offset).
 multiclass Loadxm_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
-                      PatLeaf ImmPred, InstHexagon MI> {
+                      ImmLeaf ImmPred, InstHexagon MI> {
   def: Pat<(VT (Load AddrFI:$fi)),
            (VT (ValueMod (MI AddrFI:$fi, 0)))>;
   def: Pat<(VT (Load (add AddrFI:$fi, ImmPred:$Off))),
            (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>;
   def: Pat<(VT (Load (add IntRegs:$Rs, ImmPred:$Off))),
            (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
   def: Pat<(VT (Load (i32 IntRegs:$Rs))),
            (VT (ValueMod (MI IntRegs:$Rs, 0)))>;

 
 let AddedComplexity = 40 in {
   def: Storexs_pat<truncstorei8,  I32, S4_storerb_rr>;
   def: Storexs_pat<truncstorei16, I32, S4_storerh_rr>;
   def: Storexs_pat<store,         I32, S4_storeri_rr>;
   def: Storexs_pat<store,         I64, S4_storerd_rr>;
 }
 
-def s30_2ProperPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v);
+def s30_2ProperPred  : ImmLeaf<i32, [{
+  return isShiftedInt<30,2>(Imm) && !isShiftedInt<29,3>(Imm);
 }]>;
 def RoundTo8 : SDNodeXForm<imm, [{
    int32_t Imm = N->getSExtValue();
    return CurDAG->getTargetConstant(Imm & -8, SDLoc(N), MVT::i32);
 }]>;
 
 let AddedComplexity = 40 in
 def: Pat<(store I64:$Ru, (add I32:$Rs, s30_2ProperPred:$Off)),

 // constant extenders in store-immediate instructions. In some cases we can
 // end up will a number of such stores, all of which store the same extended
 // value (e.g. after unrolling a loop that initializes floating point array).
 
 // Predicates to determine if the 16-bit immediate is expressible as a sign-
 // extended 8-bit immediate. Store-immediate-halfword will ignore any bits
 // beyond 0..15, so we don't care what is in there.
 
-def i16in8ImmPred: PatLeaf<(i32 imm), [{
-  int64_t v = (int16_t)N->getSExtValue();
+def i16in8ImmPred: ImmLeaf<i32, [{
+  int64_t v = (int16_t)Imm;
   return v == (int64_t)(int8_t)v;
 }]>;
 
 // Predicates to determine if the 32-bit immediate is expressible as a sign-
 // extended 8-bit immediate.
-def i32in8ImmPred: PatLeaf<(i32 imm), [{
-  int64_t v = (int32_t)N->getSExtValue();
+def i32in8ImmPred: ImmLeaf<i32, [{
+  int64_t v = (int32_t)Imm;
   return v == (int64_t)(int8_t)v;
 }]>;
 
 
 let AddedComplexity = 40 in {
   // Even though the offset is not extendable in the store-immediate, we
   // can still generate the fi# in the base address. If the final offset
   // is not valid for the instruction, we will replace it with a scratch
"", ALU64_tc_3x_SLOT23>, ImmRegRel {
     let Inst{20-16} = Rs;
     let Inst{13}    = u6{3};
     let Inst{12-8}  = Rt;
     let Inst{7-5}   = u6{2-0};
     let Inst{4-0}   = Rd;
   }
 
 let hasNewValue = 1 in
-class T_AddMpy <bit MajOp, PatLeaf ImmPred, dag ins>
+class T_AddMpy <bit MajOp, ImmLeaf ImmPred, dag ins>
   : ALU64Inst <(outs IntRegs:$dst), ins,
   "$dst = add($src1, mpyi("#!if(MajOp,"$src3, #$src2))",
                                       "#$src2, $src3))"),
   [(set (i32 IntRegs:$dst),
         (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), ImmPred:$src2)))],
   "", ALU64_tc_3x_SLOT23> {
     bits<5> dst;
     bits<5> src1;

 //===----------------------------------------------------------------------===//
 // XTYPE/SHIFT -
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // MEMOP
 //===----------------------------------------------------------------------===//
 
-def m5Imm8Pred : PatLeaf<(i32 imm), [{
-  int8_t v = (int8_t)N->getSExtValue();
+def m5Imm8Pred : ImmLeaf<i32, [{
+  int8_t v = (int8_t)Imm;
   return v > -32 && v <= -1;
 }]>;
 
-def m5Imm16Pred : PatLeaf<(i32 imm), [{
-  int16_t v = (int16_t)N->getSExtValue();
+def m5Imm16Pred : ImmLeaf<i32, [{
+  int16_t v = (int16_t)Imm;
   return v > -32 && v <= -1;
 }]>;
 
-def Clr5Imm8Pred : PatLeaf<(i32 imm), [{
-  uint32_t v = (uint8_t)~N->getZExtValue();
+def Clr5Imm8Pred : ZExtImmLeaf<i32, [{
+  uint32_t v = (uint8_t)~Imm;
   return ImmIsSingleBit(v);
 }]>;
 
-def Clr5Imm16Pred : PatLeaf<(i32 imm), [{
-  uint32_t v = (uint16_t)~N->getZExtValue();
+def Clr5Imm16Pred : ZExtImmLeaf<i32, [{
+  uint32_t v = (uint16_t)~Imm;
   return ImmIsSingleBit(v);
 }]>;
 
 def Set5Imm8 : SDNodeXForm<imm, [{
    uint32_t imm = (uint8_t)N->getZExtValue();
    return XformMskToBitPosU5Imm(imm, SDLoc(N));
 }]>;
 

llvm/lib/Target/Hexagon/HexagonIntrinsics.td

class T_P_pat <InstHexagon MI, Intrinsic IntID>
   : Pat <(IntID I64:$Rs),
          (MI I64:$Rs)>;
 
 class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
   : Pat<(IntID Imm1:$Is, Imm2:$It),
         (MI Imm1:$Is, Imm2:$It)>;
 
 class T_RI_pat <InstHexagon MI, Intrinsic IntID,
-                PatLeaf ImmPred = PatLeaf<(i32 imm)>>
+                PatFrag ImmPred = PatLeaf<(i32 imm)>>
   : Pat<(IntID I32:$Rs, ImmPred:$It),
         (MI I32:$Rs, ImmPred:$It)>;
 
 class T_IR_pat <InstHexagon MI, Intrinsic IntID,
                 PatFrag ImmPred = PatLeaf<(i32 imm)>>
   : Pat<(IntID ImmPred:$Is, I32:$Rt),
         (MI ImmPred:$Is, I32:$Rt)>;
 
class T_FFF_pat <InstHexagon MI, Intrinsic IntID>
   : Pat<(IntID F32:$Rs, F32:$Rt, F32:$Ru),
         (MI F32:$Rs, F32:$Rt, F32:$Ru)>;
 
 class T_FFFQ_pat <InstHexagon MI, Intrinsic IntID>
   : Pat <(IntID F32:$Rs, F32:$Rt, F32:$Ru, I32:$Rp),
          (MI F32:$Rs, F32:$Rt, F32:$Ru, (C2_tfrrp I32:$Rp))>;
 
 class T_Q_RI_pat <InstHexagon MI, Intrinsic IntID,
-                  PatLeaf ImmPred = PatLeaf<(i32 imm)>>
+                  PatFrag ImmPred = PatLeaf<(i32 imm)>>
   : Pat<(IntID I32:$Rs, ImmPred:$It),
         (C2_tfrpr (MI I32:$Rs, ImmPred:$It))>;
 
 class T_Q_RR_pat <InstHexagon MI, Intrinsic IntID>
   : Pat <(IntID I32:$Rs, I32:$Rt),
          (C2_tfrpr (MI I32:$Rs, I32:$Rt))>;
 
 class T_Q_RP_pat <InstHexagon MI, Intrinsic IntID>
: Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru),
         (MI I32:$Rs, I32:$Ru, Val:$Rt)>;
 
 def : T_stb_pat <S2_storerh_pbr, int_hexagon_brev_sth,   I32>;
 def : T_stb_pat <S2_storerb_pbr, int_hexagon_brev_stb,   I32>;
 def : T_stb_pat <S2_storeri_pbr, int_hexagon_brev_stw,   I32>;
 def : T_stb_pat <S2_storerf_pbr, int_hexagon_brev_sthhi, I32>;
 def : T_stb_pat <S2_storerd_pbr, int_hexagon_brev_std,   I64>;
 
-class T_stc_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Imm, PatLeaf Val>
+class T_stc_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm, PatLeaf Val>
   : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s),
         (MI I32:$Rs, Imm:$s, I32:$Ru, Val:$Rt)>;
 
 def: T_stc_pat<S2_storerb_pci, int_hexagon_circ_stb,   s4_0ImmPred, I32>;
 def: T_stc_pat<S2_storerh_pci, int_hexagon_circ_sth,   s4_1ImmPred, I32>;
 def: T_stc_pat<S2_storeri_pci, int_hexagon_circ_stw,   s4_2ImmPred, I32>;
 def: T_stc_pat<S2_storerd_pci, int_hexagon_circ_std,   s4_3ImmPred, I64>;
 def: T_stc_pat<S2_storerf_pci, int_hexagon_circ_sthhi, s4_1ImmPred, I32>;
 
 include "HexagonIntrinsicsV3.td"
 include "HexagonIntrinsicsV4.td"
 include "HexagonIntrinsicsV5.td"
 include "HexagonIntrinsicsV60.td"

llvm/lib/Target/Hexagon/HexagonOperands.td

def s3_6Imm : Operand<i32> { let ParserMatchClass = s3_6ImmOperand;
                                let DecoderMethod = "s3_6ImmDecoder";}
   def s3_7Imm : Operand<i32> { let PrintMethod = "prints3_7ImmOperand";
                                let DecoderMethod = "s3_6ImmDecoder";}
 }
 
 //
 // Immediate predicates
 //
-def s32ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isInt<32>(v);
+def s32ImmPred  : ImmLeaf<i32, [{
+  return isInt<32>(Imm);
 }]>;
 
-def s32_0ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isInt<32>(v);
+def s32_0ImmPred  : ImmLeaf<i32, [{
+  return isInt<32>(Imm);
 }]>;
 
-def s31_1ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isShiftedInt<31,1>(v);
+def s31_1ImmPred  : ImmLeaf<i32, [{
+  return isShiftedInt<31,1>(Imm);
 }]>;
 
-def s30_2ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isShiftedInt<30,2>(v);
+def s30_2ImmPred  : ImmLeaf<i32, [{
+  return isShiftedInt<30,2>(Imm);
 }]>;
 
-def s29_3ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isShiftedInt<29,3>(v);
+def s29_3ImmPred  : ImmLeaf<i32, [{
+  return isShiftedInt<29,3>(Imm);
 }]>;
 
-def s10ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isInt<10>(v);
+def s10ImmPred  : ImmLeaf<i32, [{
+  return isInt<10>(Imm);
 }]>;
 
-def s8ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isInt<8>(v);
+def s8ImmPred  : ImmLeaf<i32, [{
+  return isInt<8>(Imm);
 }]>;
 
-def s8Imm64Pred  : PatLeaf<(i64 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isInt<8>(v);
+def s8Imm64Pred  : ImmLeaf<i64, [{
+  return isInt<8>(Imm);
 }]>;
 
-def s6ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isInt<6>(v);
+def s6ImmPred  : ImmLeaf<i32, [{
+  return isInt<6>(Imm);
 }]>;
 
-def s4_0ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isInt<4>(v);
+def s4_0ImmPred  : ImmLeaf<i32, [{
+  return isInt<4>(Imm);
 }]>;
 
-def s4_1ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isShiftedInt<4,1>(v);
+def s4_1ImmPred  : ImmLeaf<i32, [{
+  return isShiftedInt<4,1>(Imm);
 }]>;
 
-def s4_2ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isShiftedInt<4,2>(v);
+def s4_2ImmPred  : ImmLeaf<i32, [{
+  return isShiftedInt<4,2>(Imm);
 }]>;
 
-def s4_3ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isShiftedInt<4,3>(v);
+def s4_3ImmPred  : ImmLeaf<i32, [{
+  return isShiftedInt<4,3>(Imm);
 }]>;
 
-def u32ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isUInt<32>(v);
+def u32ImmPred  : ImmLeaf<i32, [{
+  return isUInt<32>(Imm);
 }]>;
 
-def u16_0ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isUInt<16>(v);
+def u16_0ImmPred  : ImmLeaf<i32, [{
+  return isUInt<16>(Imm);
 }]>;
 
-def u11_3ImmPred : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isShiftedUInt<11,3>(v);
+def u11_3ImmPred : ImmLeaf<i32, [{
+  return isShiftedUInt<11,3>(Imm);
 }]>;
 
-def u9ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isUInt<9>(v);
+def u9ImmPred  : ImmLeaf<i32, [{
+  return isUInt<9>(Imm);
 }]>;
 
-def u8ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isUInt<8>(v);
+def u8ImmPred  : ImmLeaf<i32, [{
+  return isUInt<8>(Imm);
 }]>;
 
 def u7StrictPosImmPred : ImmLeaf<i32, [{
   // u7StrictPosImmPred predicate - True if the immediate fits in an 7-bit
   // unsigned field and is strictly greater than 0.
   return isUInt<7>(Imm) && Imm > 0;
 }]>;
 
-def u6ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isUInt<6>(v);
+def u6ImmPred  : ImmLeaf<i32, [{
+  return isUInt<6>(Imm);
 }]>;
 
-def u6_0ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isUInt<6>(v);
+def u6_0ImmPred  : ImmLeaf<i32, [{
+  return isUInt<6>(Imm);
 }]>;
 
-def u6_1ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isShiftedUInt<6,1>(v);
+def u6_1ImmPred  : ImmLeaf<i32, [{
+  return isShiftedUInt<6,1>(Imm);
 }]>;
 
-def u6_2ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isShiftedUInt<6,2>(v);
+def u6_2ImmPred  : ImmLeaf<i32, [{
+  return isShiftedUInt<6,2>(Imm);
 }]>;
 
-def u5ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isUInt<5>(v);
+def u5ImmPred  : ImmLeaf<i32, [{
+  return isUInt<5>(Imm);
 }]>;
 
-def u4ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isUInt<4>(v);
+def u4ImmPred  : ImmLeaf<i32, [{
+  return isUInt<4>(Imm);
 }]>;
 
-def u3ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isUInt<3>(v);
+def u3ImmPred  : ImmLeaf<i32, [{
+  return isUInt<3>(Imm);
 }]>;
 
-def u2ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  return isUInt<2>(v);
+def u2ImmPred  : ImmLeaf<i32, [{
+  return isUInt<2>(Imm);
 }]>;
 
-def m5ImmPred  : PatLeaf<(i32 imm), [{
+def m5ImmPred  : ImmLeaf<i32, [{
   // m5ImmPred predicate - True if the number is in range -1 .. -31
   // and will fit in a 5 bit field when made positive, for use in memops.
-  int64_t v = (int64_t)N->getSExtValue();
-  return (-31 <= v && v <= -1);
+  return (-31 <= Imm && Imm <= -1);
 }]>;
 
 //InN means negative integers in [-(2^N - 1), 0]
-def n8ImmPred  : PatLeaf<(i32 imm), [{
+def n8ImmPred  : ImmLeaf<i32, [{
   // n8ImmPred predicate - True if the immediate fits in a 8-bit signed
   // field.
-  int64_t v = (int64_t)N->getSExtValue();
-  return (-255 <= v && v <= 0);
+  return (-255 <= Imm && Imm <= 0);
 }]>;
 
-def nOneImmPred  : PatLeaf<(i32 imm), [{
-  // nOneImmPred predicate - True if the immediate is -1.
-  int64_t v = (int64_t)N->getSExtValue();
-  return (-1 == v);
-}]>;
-
-def Set5ImmPred : PatLeaf<(i32 imm), [{
+def Set5ImmPred : ImmLeaf<i32, [{
   // Set5ImmPred predicate - True if the number is in the series of values.
   // [ 2^0, 2^1, ... 2^31 ]
   // For use in setbit immediate.
-  uint32_t v = (int32_t)N->getSExtValue();
+  uint32_t v = (int32_t)Imm;
   // Constrain to 32 bits, and then check for single bit.
   return ImmIsSingleBit(v);
 }]>;
 
-def Clr5ImmPred : PatLeaf<(i32 imm), [{
+def Clr5ImmPred : ImmLeaf<i32, [{
   // Clr5ImmPred predicate - True if the number is in the series of
   // bit negated values.
   // [ 2^0, 2^1, ... 2^31 ]
   // For use in clrbit immediate.
   // Note: we are bit NOTing the value.
-  uint32_t v = ~ (int32_t)N->getSExtValue();
+  uint32_t v = ~ (int32_t)Imm;
   // Constrain to 32 bits, and then check for single bit.
   return ImmIsSingleBit(v);
 }]>;
 
 // Extendable immediate operands.
 def f32ExtOperand : AsmOperandClass { let Name = "f32Ext"; }
 def s16ExtOperand : AsmOperandClass { let Name = "s16Ext"; }
 def s12ExtOperand : AsmOperandClass { let Name = "s12Ext"; }
let OperandType = "OPERAND_IMMEDIATE", PrintMethod = "printExtOperand",
   def u6_0Ext : Operand<i32> { let ParserMatchClass = u6_0ExtOperand; }
   def u6_1Ext : Operand<i32> { let ParserMatchClass = u6_1ExtOperand; }
   def u6_2Ext : Operand<i32> { let ParserMatchClass = u6_2ExtOperand; }
   def u6_3Ext : Operand<i32> { let ParserMatchClass = u6_3ExtOperand; }
   def u32MustExt : Operand<i32> { let ParserMatchClass = u32MustExtOperand; }
 }
 
 
-def s4_7ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
+def s4_7ImmPred  : ImmLeaf<i32, [{
   if (HST->hasV60TOps())
     // Return true if the immediate can fit in a 10-bit sign extended field and
     // is 128-byte aligned.
-    return isShiftedInt<4,7>(v);
+    return isShiftedInt<4,7>(Imm);
   return false;
 }]>;
 
-def s4_6ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
+def s4_6ImmPred  : ImmLeaf<i32, [{
   if (HST->hasV60TOps())
     // Return true if the immediate can fit in a 10-bit sign extended field and
     // is 64-byte aligned.
-    return isShiftedInt<4,6>(v);
+    return isShiftedInt<4,6>(Imm);
   return false;
 }]>;
 
 
 // This complex pattern exists only to create a machine instruction operand
 // of type "frame index". There doesn't seem to be a way to do that directly
 // in the patterns.
 def AddrFI : ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>;

llvm/lib/Target/Lanai/LanaiInstrInfo.td

 }
 def CallTarget : Operand<i32> {
   let ParserMatchClass = CallTargetAsmOperand;
   let EncoderMethod = "getBranchTargetOpValue";
   let DecoderMethod = "decodeBranch";
 }
 
 def ImmShiftAsmOperand : AsmOperandClass { let Name = "ImmShift"; }
-def immShift : Operand<i32>, PatLeaf<(imm), [{
-    int Imm = N->getSExtValue();
+def immShift : Operand<i32>, ImmLeaf<i32, [{
     return Imm >= -31 && Imm <= 31;}]> {
   let ParserMatchClass = ImmShiftAsmOperand;
   let DecoderMethod = "decodeShiftImm";
 }
 
 def Imm10AsmOperand : AsmOperandClass { let Name = "Imm10"; }
-def imm10 : Operand<i32>, PatLeaf<(imm), [{
-    return isInt<10>(N->getSExtValue()); }]> {
+def imm10 : Operand<i32>, ImmLeaf<i32, [{
+    return isInt<10>(Imm); }]> {
   let ParserMatchClass = Imm10AsmOperand;
 }
 
 def LoImm16AsmOperand : AsmOperandClass { let Name = "LoImm16"; }
-def i32lo16z : Operand<i32>, PatLeaf<(i32 imm), [{
+def i32lo16z : Operand<i32>, ZExtImmLeaf<i32, [{
     // i32lo16 predicate - true if the 32-bit immediate has only rightmost 16
     // bits set.
-    return ((N->getZExtValue() & 0xFFFFUL) == N->getZExtValue());}], LO16> {
+    return ((Imm & 0xFFFFUL) == Imm);}], LO16> {
   let ParserMatchClass = LoImm16AsmOperand;
 }
-def i32neg16 : Operand<i32>, PatLeaf<(i32 imm), [{
+def i32neg16 : Operand<i32>, ImmLeaf<i32, [{
     // i32neg16 predicate - true if the 32-bit immediate is negative and can
     // be represented by a 16 bit integer.
-    int Imm = N->getSExtValue();
     return (Imm < 0) && (isInt<16>(Imm));}], LO16> {
   let ParserMatchClass = LoImm16AsmOperand;
 }
-def i32lo16s : Operand<i32>, PatLeaf<(i32 imm), [{
+def i32lo16s : Operand<i32>, ImmLeaf<i32, [{
     // i32lo16 predicate - true if the 32-bit immediate has only rightmost 16
     // bits set.
-    return ((int64_t)(N->getSExtValue() & 0xFFFFUL) == N->getSExtValue());}], LO16> {
+    return ((int64_t)(Imm & 0xFFFFUL) == Imm));}], LO16> {
   let ParserMatchClass = LoImm16AsmOperand;
 }
 
 def LoImm16AndAsmOperand : AsmOperandClass { let Name = "LoImm16And"; }
-def i32lo16and : Operand<i32>, PatLeaf<(i32 imm), [{
+def i32lo16and : Operand<i32>, ZExtImmLeaf<i32, [{
     // i32lo16 predicate - true if the 32-bit immediate has the rightmost 16
     // bits set and the leftmost 16 bits 1's.
-    return (N->getZExtValue() >= 0xFFFF0000UL);}], LO16> {
+    return (Imm >= 0xFFFF0000UL);}], LO16> {
   let ParserMatchClass = LoImm16AndAsmOperand;
   let PrintMethod = "printLo16AndImmOperand";
 }
 
 def HiImm16AsmOperand : AsmOperandClass { let Name = "HiImm16"; }
-def i32hi16 : Operand<i32>, PatLeaf<(i32 imm), [{
+def i32hi16 : Operand<i32>, ZExtImmLeaf<i32, [{
     // i32hi16 predicate - true if the 32-bit immediate has only leftmost 16
     // bits set.
-    return ((N->getZExtValue() & 0xFFFF0000UL) == N->getZExtValue());}], HI16> {
+    return ((Imm & 0xFFFF0000UL) == Imm);}], HI16> {
   let ParserMatchClass = HiImm16AsmOperand;
   let PrintMethod = "printHi16ImmOperand";
 }
 
 def HiImm16AndAsmOperand : AsmOperandClass { let Name = "HiImm16And"; }
-def i32hi16and : Operand<i32>, PatLeaf<(i32 imm), [{
+def i32hi16and : Operand<i32>, ZExtImmLeaf<i32, [{
     // i32lo16 predicate - true if the 32-bit immediate has the leftmost 16
     // bits set and the rightmost 16 bits 1's.
-    return ((N->getZExtValue() & 0xFFFFUL) == 0xFFFFUL);}], HI16> {
+    return ((Imm & 0xFFFFUL) == 0xFFFFUL);}], HI16> {
   let ParserMatchClass = HiImm16AndAsmOperand;
   let PrintMethod = "printHi16AndImmOperand";
 }
 
 def LoImm21AsmOperand : AsmOperandClass { let Name = "LoImm21"; }
-def i32lo21 : Operand<i32>, PatLeaf<(i32 imm), [{
+def i32lo21 : Operand<i32>, ZExtImmLeaf<i32, [{
     // i32lo21 predicate - true if the 32-bit immediate has only rightmost 21
     // bits set.
-    return ((N->getZExtValue() & 0x1FFFFFUL) == N->getZExtValue());}], LO21> {
+    return ((Imm & 0x1FFFFFUL) == Imm);}], LO21> {
   let ParserMatchClass = LoImm21AsmOperand;
 }
 
 def AluOp : Operand<i32> {
   let PrintMethod = "printAluOperand";
 }
 
 // Addressing modes.
def splsIdempotent : InstrMapping {
   let KeyCol = ["adjustPqBitsSpls"];
   let ValueCols = [["adjustPqBitsSpls"]];
 }
 
 // -------------------------------------------------- //
 // ALU instructions
 // -------------------------------------------------- //
 multiclass ALUbase<bits<3> subOp, string AsmStr, SDNode OpNode,
-                   PatLeaf LoExt, PatLeaf HiExt,
+                   ImmLeaf LoExt, ImmLeaf HiExt,
                    list<dag> loPattern, list<dag> hiPattern> {
   // Register Immediate
   let H = 0 in
     def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
                     !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
                     loPattern>;
   let H = 1 in
     def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
                     !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
                     hiPattern>;
 
 }
 
 multiclass ALUarith<bits<3> subOp, string AsmStr, SDNode OpNode,
-                    PatLeaf LoExt, PatLeaf HiExt> {
+                    ImmLeaf LoExt, ImmLeaf HiExt> {
   defm I_ : ALUbase<subOp, AsmStr, OpNode, LoExt, HiExt, [], []>;
 
   // Register Register
   let JJJJJ = 0 in
     def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
                    !strconcat(AsmStr, "$DDDI\t$Rs1, $Rs2, $Rd"),
                    [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
 }
 
 multiclass ALUlogic<bits<3> subOp, string AsmStr, SDNode OpNode,
-                    PatLeaf LoExt, PatLeaf HiExt> {
+                    ImmLeaf LoExt, ImmLeaf HiExt> {
   defm I_ : ALUbase<subOp, AsmStr, OpNode, LoExt, HiExt,
                     [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
                     [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
 
   // Register Register
   let JJJJJ = 0 in
     def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
                    !strconcat(AsmStr, "$DDDI\t$Rs1, $Rs2, $Rd"),

llvm/lib/Target/Mips/Mips16InstrInfo.td

 
 
 // setcc patterns
 
 class SetCC_R16<PatFrag cond_op, Instruction I>:
   Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
             (I CPU16Regs:$rx, CPU16Regs:$ry)>;
 
-class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
+class SetCC_I16<PatFrag cond_op, PatFrag imm_type, Instruction I>:
   Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
             (I CPU16Regs:$rx, imm_type:$imm16)>;
 
 
 def: Mips16Pat<(i32 addr16sp:$addr), (AddiuRxRyOffMemX16 addr16sp:$addr)>;
 
 
 // Large (>16 bit) immediate loads

llvm/lib/Target/Mips/Mips64InstrInfo.td

 // Mips Operand, Complex Patterns and Transformations Definitions.
 //===----------------------------------------------------------------------===//
 
 // shamt must fit in 6 bits.
 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
 
 // Node immediate fits as 10-bit sign extended on target immediate.
 // e.g. seqi, snei
-def immSExt10_64 : PatLeaf<(i64 imm),
-                           [{ return isInt<10>(N->getSExtValue()); }]>;
+def immSExt10_64 : ImmLeaf<i64, [{ return isInt<10>(Imm); }]>;
 
-def immZExt16_64 : PatLeaf<(i64 imm),
-                           [{ return isUInt<16>(N->getZExtValue()); }]>;
+def immZExt16_64 : ZExtImmLeaf<i64, [{ return isUInt<16>(Imm); }]>;
 
 def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>;
 
 // Transformation function: get log2 of low 32 bits of immediate
 def Log2LO : SDNodeXForm<imm, [{
   return getImm(N, Log2_64((unsigned) N->getZExtValue()));
 }]>;
 
 // Transformation function: get log2 of high 32 bits of immediate
 def Log2HI : SDNodeXForm<imm, [{
   return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32)));
 }]>;
 
 // Predicate: True if immediate is a power of 2 and fits 32 bits
-def PowerOf2LO : PatLeaf<(imm), [{
-  if (N->getValueType(0) == MVT::i64) {
-    uint64_t Imm = N->getZExtValue();
-    return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm;
-  }
-  else
-    return false;
+def PowerOf2LO : ZExtImmLeaf<i64, [{
 }]>;
 
 // Predicate: True if immediate is a power of 2 and exceeds 32 bits
-def PowerOf2HI : PatLeaf<(imm), [{
-  if (N->getValueType(0) == MVT::i64) {
-    uint64_t Imm = N->getZExtValue();
-    return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm;
-  }
-  else
-    return false;
+def PowerOf2HI : ZExtImmLeaf<i64, [{
 }]>;
 
 def assertzext_lt_i32 : PatFrag<(ops node:$src), (assertzext node:$src), [{
   return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32);
 }]>;
 
 //===----------------------------------------------------------------------===//
 // Instructions specific format

llvm/lib/Target/Mips/MipsInstrInfo.td

 def HI16 : SDNodeXForm<imm, [{
   return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
 }]>;
 
 // Plus 1.
 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
 
 // Node immediate is zero (e.g. insve.d)
-def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
+def immz : AnyImmLeaf<[{ return Imm == 0; }]>;
 
 // Node immediate fits as 16-bit sign extended on target immediate.
 // e.g. addi, andi
-def immSExt8  : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
+def immSExt8  : AnyImmLeaf<[{ return isInt<8>(Imm); }]>;
 
 // Node immediate fits as 16-bit sign extended on target immediate.
 // e.g. addi, andi
-def immSExt16  : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
+def immSExt16  : AnyImmLeaf<[{ return isInt<16>(Imm); }]>;
 
 // Node immediate fits as 7-bit zero extended on target immediate.
-def immZExt7 : PatLeaf<(imm), [{ return isUInt<7>(N->getZExtValue()); }]>;
+def immZExt7 : ZExtAnyImmLeaf<[{ return isUInt<7>(Imm); }]>;
 
 // Node immediate fits as 16-bit zero extended on target immediate.
 // The LO16 param means that only the lower 16 bits of the node
 // immediate are caught.
 // e.g. addiu, sltiu
 def immZExt16  : PatLeaf<(imm), [{
   if (N->getValueType(0) == MVT::i32)
     return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
   else
     return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
 }], LO16>;
 
 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
-def immSExt32Low16Zero : PatLeaf<(imm), [{
-  int64_t Val = N->getSExtValue();
-  return isInt<32>(Val) && !(Val & 0xffff);
+def immSExt32Low16Zero : AnyImmLeaf<[{
+  return isInt<32>(Imm) && !(Imm & 0xffff);
 }]>;
 
 // Zero-extended 32-bit unsigned int with lower 16-bit cleared.
-def immZExt32Low16Zero : PatLeaf<(imm), [{
-  uint64_t Val = N->getZExtValue();
-  return isUInt<32>(Val) && !(Val & 0xffff);
+def immZExt32Low16Zero : ZExtAnyImmLeaf<[{
+  return isUInt<32>(Imm) && !(Imm & 0xffff);
 }]>;
 
 // Note immediate fits as a 32 bit signed extended on target immediate.
-def immSExt32  : PatLeaf<(imm), [{ return isInt<32>(N->getSExtValue()); }]>;
+def immSExt32  : AnyImmLeaf<[{ return isInt<32>(Imm); }]>;
 
 // Note immediate fits as a 32 bit zero extended on target immediate.
-def immZExt32  : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;
+def immZExt32  : ZExtAnyImmLeaf<[{ return isUInt<32>(Imm); }]>;
 
 // shamt field must fit in 5 bits.
 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
 
-def immZExt5Plus1 : PatLeaf<(imm), [{
-  return isUInt<5>(N->getZExtValue() - 1);
+def immZExt5Plus1 : ZExtAnyImmLeaf<[{
+  return isUInt<5>(Imm - 1);
 }]>;
-def immZExt5Plus32 : PatLeaf<(imm), [{
-  return isUInt<5>(N->getZExtValue() - 32);
+def immZExt5Plus32 : ZExtAnyImmLeaf<[{
+  return isUInt<5>(Imm - 32);
 }]>;
-def immZExt5Plus33 : PatLeaf<(imm), [{
-  return isUInt<5>(N->getZExtValue() - 33);
+def immZExt5Plus33 : ZExtAnyImmLeaf<[{
+  return isUInt<5>(Imm - 33);
 }]>;
 
 // True if (N + 1) fits in 16-bit field.
-def immSExt16Plus1 : PatLeaf<(imm), [{
-  return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
+def immSExt16Plus1 : AnyImmLeaf<[{
+  return isInt<17>(Imm) && isInt<16>(Imm + 1);
 }]>;
 
 // Mips Address Mode! SDNode frameindex could possibily be a match
 // since load and store instructions from stack used it.
 def addr :
   ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
 
 def addrRegImm :

 
 // SetCC
 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
   InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
          !strconcat(opstr, "\t$rd, $rs, $rt"),
          [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
          II_SLT_SLTU, FrmR, opstr>;
 
-class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
+class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatFrag imm_type,
               RegisterOperand RO>:
   InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
          !strconcat(opstr, "\t$rt, $rs, $imm16"),
          [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
          II_SLTI_SLTIU, FrmI, opstr>;
 
 // Jump
 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 }]>;
 
 def ME : SDNodeXForm<imm, [{
   // Transformation function: get the end bit of a mask
   unsigned mb, me = 0;
   (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
   return getI32Imm(me, SDLoc(N));
 }]>;
-def maskimm32 : PatLeaf<(imm), [{
+def maskimm32 : ZExtImmLeaf<i32, [{
   // maskImm predicate - True if immediate is a run of ones.
   unsigned mb, me;
-  if (N->getValueType(0) == MVT::i32)
-    return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
-  else
-    return false;
+  return isRunOfOnes(Imm, mb, me);
 }]>;
 
 def imm32SExt16  : Operand<i32>, ImmLeaf<i32, [{
   // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
   // sign extended field.  Used by instructions like 'addi'.
   return (int32_t)Imm == (short)Imm;
 }]>;
 def imm64SExt16  : Operand<i64>, ImmLeaf<i64, [{
   // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
   // sign extended field.  Used by instructions like 'addi'.
   return (int64_t)Imm == (short)Imm;
 }]>;
-def immZExt16  : PatLeaf<(imm), [{
+def immZExt16  : ZExtAnyImmLeaf<[{
   // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
   // field.  Used by instructions like 'ori'.
-  return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
+  return (uint64_t)Imm == (unsigned short)Imm;
 }], LO16>;
 def immSExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>;
 
 // imm16Shifted* - These match immediates where the low 16-bits are zero.  There
 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt.  These two forms are
 // identical in 32-bit mode, but in 64-bit mode, they return true if the
 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
 // clear).
-def imm16ShiftedZExt : PatLeaf<(imm), [{
+def imm16ShiftedZExt : ZExtAnyImmLeaf<[{
   // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
   // immediate are set.  Used by instructions like 'xoris'.
-  return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
+  return (Imm & ~uint64_t(0xFFFF0000)) == 0;
 }], HI16>;
 
 def imm16ShiftedSExt : PatLeaf<(imm), [{
   // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
   // immediate are set.  Used by instructions like 'addis'.  Identical to 
   // imm16ShiftedZExt in 32-bit mode.
   if (N->getZExtValue() & 0xFFFF) return false;
   if (N->getValueType(0) == MVT::i32)

llvm/lib/Target/Sparc/SparcInstr64Bit.td

 // microarchitecture.
 
 // Single-instruction patterns.
 
 // The ALU instructions want their simm13 operands as i32 immediates.
 def as_i32imm : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
 }]>;
+
 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
 def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
 
 // Double-instruction patterns.
 
 // All unsigned i32 immediates can be handled by sethi+or.
-def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;
+def uimm32 : ZExtImmLeaf<i64, [{ return isUInt<32>(Imm); }]>;
 def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>,
       Requires<[Is64Bit]>;
 
 // All negative i33 immediates can be handled by sethi+xor.
-def nimm33 : PatLeaf<(imm), [{
-  int64_t Imm = N->getSExtValue();
+def nimm33 : ImmLeaf<i64, [{
   return Imm < 0 && isInt<33>(Imm);
 }]>;
 // Bits 10-31 inverted. Same as assembler's %hix.
 def HIX22 : SDNodeXForm<imm, [{
   uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1);
   return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32);
 }]>;
 // Bits 0-9 with ones in bits 10-31. Same as assembler's %lox.

llvm/lib/Target/Sparc/SparcInstrInfo.td

 // to use when appropriate.  In either of these cases, the instruction selector
 // will pick deprecated instructions.
 def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">;
 
 //===----------------------------------------------------------------------===//
 // Instruction Pattern Stuff
 //===----------------------------------------------------------------------===//
 
-def simm11  : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
+def simm11  : AnyImmLeaf<[{ return isInt<11>(Imm); }]>;
 
-def simm13  : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
+def simm13  : AnyImmLeaf<[{ return isInt<13>(Imm); }]>;
 
 def LO10 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N),
                                    MVT::i32);
 }]>;
 
 def HI22 : SDNodeXForm<imm, [{
   // Transformation function: shift the immediate value down into the low bits.
   return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N),
                                    MVT::i32);
 }]>;
 
-def SETHIimm : PatLeaf<(imm), [{
-  return isShiftedUInt<22, 10>(N->getZExtValue());
+def SETHIimm : AnyImmLeaf<[{
+  return isShiftedUInt<22, 10>(Imm);
 }], HI22>;
 
 // Addressing modes.
 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
 
 // Address operands
 def SparcMEMrrAsmOperand : AsmOperandClass {

llvm/lib/Target/SystemZ/SystemZOperands.td

class ImmediateTLSAsmOperand<string name>
   let Name = name;
   let RenderMethod = "addImmTLSOperands";
 }
 
 // Constructs both a DAG pattern and instruction operand for an immediate
 // of type VT.  PRED returns true if a node is acceptable and XFORM returns
 // the operand value associated with the node.  ASMOP is the name of the
 // associated asm operand, and also forms the basis of the asm print method.
-class Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop>
-  : PatLeaf<(vt imm), pred, xform>, Operand<vt> {
+class Immediate<ValueType vt, bit signed, code pred, SDNodeXForm xform, string asmop>
+  : ImmLeaf<vt, pred, xform>, Operand<vt> {
   let PrintMethod = "print"##asmop##"Operand";
   let DecoderMethod = "decode"##asmop##"Operand";
   let ParserMatchClass = !cast<AsmOperandClass>(asmop);
+  let Signed = signed;
 }
 
 // Constructs an asm operand for a PC-relative address.  SIZE says how
 // many bits there are.
 class PCRelAsmOperand<string size> : ImmediateAsmOperand<"PCRel"##size> {
   let PredicateMethod = "isImm";
   let ParserMethod = "parsePCRel"##size;
 }

 def U48Imm : ImmediateAsmOperand<"U48Imm">;
 
 //===----------------------------------------------------------------------===//
 // i32 immediates
 //===----------------------------------------------------------------------===//
 
 // Immediates for the lower and upper 16 bits of an i32, with the other
 // bits of the i32 being zero.
-def imm32ll16 : Immediate<i32, [{
-  return SystemZ::isImmLL(N->getZExtValue());
+def imm32ll16 : Immediate<i32, 0, [{
+  return SystemZ::isImmLL(Imm);
 }], LL16, "U16Imm">;
 
-def imm32lh16 : Immediate<i32, [{
-  return SystemZ::isImmLH(N->getZExtValue());
+def imm32lh16 : Immediate<i32, 0, [{
+  return SystemZ::isImmLH(Imm);
 }], LH16, "U16Imm">;
 
 // Immediates for the lower and upper 16 bits of an i32, with the other
 // bits of the i32 being one.
-def imm32ll16c : Immediate<i32, [{
-  return SystemZ::isImmLL(uint32_t(~N->getZExtValue()));
+def imm32ll16c : Immediate<i32, 0, [{
+  return SystemZ::isImmLL(uint32_t(~Imm));
 }], LL16, "U16Imm">;
 
-def imm32lh16c : Immediate<i32, [{
-  return SystemZ::isImmLH(uint32_t(~N->getZExtValue()));
+def imm32lh16c : Immediate<i32, 0, [{
+  return SystemZ::isImmLH(uint32_t(~Imm));
 }], LH16, "U16Imm">;
 
 // Short immediates
-def imm32zx1 : Immediate<i32, [{
-  return isUInt<1>(N->getZExtValue());
+def imm32zx1 : Immediate<i32, 0, [{
+  return isUInt<1>(Imm);
 }], NOOP_SDNodeXForm, "U1Imm">;
 
-def imm32zx2 : Immediate<i32, [{
-  return isUInt<2>(N->getZExtValue());
+def imm32zx2 : Immediate<i32, 0, [{
+  return isUInt<2>(Imm);
 }], NOOP_SDNodeXForm, "U2Imm">;
 
-def imm32zx3 : Immediate<i32, [{
-  return isUInt<3>(N->getZExtValue());
+def imm32zx3 : Immediate<i32, 0, [{
+  return isUInt<3>(Imm);
 }], NOOP_SDNodeXForm, "U3Imm">;
 
-def imm32zx4 : Immediate<i32, [{
-  return isUInt<4>(N->getZExtValue());
+def imm32zx4 : Immediate<i32, 0, [{
+  return isUInt<4>(Imm);
 }], NOOP_SDNodeXForm, "U4Imm">;
 
 // Note: this enforces an even value during code generation only.
 // When used from the assembler, any 4-bit value is allowed.
-def imm32zx4even : Immediate<i32, [{
-  return isUInt<4>(N->getZExtValue());
+def imm32zx4even : Immediate<i32, 0, [{
+  return isUInt<4>(Imm);
 }], UIMM8EVEN, "U4Imm">;
 
-def imm32zx6 : Immediate<i32, [{
-  return isUInt<6>(N->getZExtValue());
+def imm32zx6 : Immediate<i32, 0, [{
+  return isUInt<6>(Imm);
 }], NOOP_SDNodeXForm, "U6Imm">;
 
-def imm32sx8 : Immediate<i32, [{
-  return isInt<8>(N->getSExtValue());
+def imm32sx8 : Immediate<i32, 1, [{
+  return isInt<8>(Imm);
 }], SIMM8, "S8Imm">;
 
-def imm32zx8 : Immediate<i32, [{
-  return isUInt<8>(N->getZExtValue());
+def imm32zx8 : Immediate<i32, 0, [{
+  return isUInt<8>(Imm);
 }], UIMM8, "U8Imm">;
 
-def imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">;
+def imm32zx8trunc : Immediate<i32, 0, [{}], UIMM8, "U8Imm">;
 
-def imm32zx12 : Immediate<i32, [{
-  return isUInt<12>(N->getZExtValue());
+def imm32zx12 : Immediate<i32, 0, [{
+  return isUInt<12>(Imm);
 }], UIMM12, "U12Imm">;
 
-def imm32sx16 : Immediate<i32, [{
-  return isInt<16>(N->getSExtValue());
+def imm32sx16 : Immediate<i32, 1, [{
+  return isInt<16>(Imm);
 }], SIMM16, "S16Imm">;
 
-def imm32zx16 : Immediate<i32, [{
-  return isUInt<16>(N->getZExtValue());
+def imm32zx16 : Immediate<i32, 0, [{
+  return isUInt<16>(Imm);
 }], UIMM16, "U16Imm">;
 
-def imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">;
+def imm32sx16trunc : Immediate<i32, 1, [{}], SIMM16, "S16Imm">;
 
 // Full 32-bit immediates.  we need both signed and unsigned versions
 // because the assembler is picky.  E.g. AFI requires signed operands
 // while NILF requires unsigned ones.
-def simm32 : Immediate<i32, [{}], SIMM32, "S32Imm">;
-def uimm32 : Immediate<i32, [{}], UIMM32, "U32Imm">;
+def simm32 : Immediate<i32, 1, [{}], SIMM32, "S32Imm">;
+def uimm32 : Immediate<i32, 0, [{}], UIMM32, "U32Imm">;
 
 def imm32 : ImmLeaf<i32, [{}]>;
 
 //===----------------------------------------------------------------------===//
 // 64-bit immediates
 //===----------------------------------------------------------------------===//
 
 // Immediates for 16-bit chunks of an i64, with the other bits of the
 // i32 being zero.
-def imm64ll16 : Immediate<i64, [{
-  return SystemZ::isImmLL(N->getZExtValue());
+def imm64ll16 : Immediate<i64, 0, [{
+  return SystemZ::isImmLL(Imm);
 }], LL16, "U16Imm">;
 
-def imm64lh16 : Immediate<i64, [{
-  return SystemZ::isImmLH(N->getZExtValue());
+def imm64lh16 : Immediate<i64, 0, [{
+  return SystemZ::isImmLH(Imm);
 }], LH16, "U16Imm">;
 
-def imm64hl16 : Immediate<i64, [{
-  return SystemZ::isImmHL(N->getZExtValue());
+def imm64hl16 : Immediate<i64, 0, [{
+  return SystemZ::isImmHL(Imm);
 }], HL16, "U16Imm">;
 
-def imm64hh16 : Immediate<i64, [{
-  return SystemZ::isImmHH(N->getZExtValue());
+def imm64hh16 : Immediate<i64, 0, [{
+  return SystemZ::isImmHH(Imm);
 }], HH16, "U16Imm">;
 
 // Immediates for 16-bit chunks of an i64, with the other bits of the
 // i32 being one.
-def imm64ll16c : Immediate<i64, [{
-  return SystemZ::isImmLL(uint64_t(~N->getZExtValue()));
+def imm64ll16c : Immediate<i64, 0, [{
+  return SystemZ::isImmLL(uint64_t(~Imm));
 }], LL16, "U16Imm">;
 
-def imm64lh16c : Immediate<i64, [{
-  return SystemZ::isImmLH(uint64_t(~N->getZExtValue()));
+def imm64lh16c : Immediate<i64, 0, [{
+  return SystemZ::isImmLH(uint64_t(~Imm));
 }], LH16, "U16Imm">;
 
-def imm64hl16c : Immediate<i64, [{
-  return SystemZ::isImmHL(uint64_t(~N->getZExtValue()));
+def imm64hl16c : Immediate<i64, 0, [{
+  return SystemZ::isImmHL(uint64_t(~Imm));
 }], HL16, "U16Imm">;
 
-def imm64hh16c : Immediate<i64, [{
-  return SystemZ::isImmHH(uint64_t(~N->getZExtValue()));
+def imm64hh16c : Immediate<i64, 0, [{
+  return SystemZ::isImmHH(uint64_t(~Imm));
 }], HH16, "U16Imm">;
 
 // Immediates for the lower and upper 32 bits of an i64, with the other
 // bits of the i32 being zero.
-def imm64lf32 : Immediate<i64, [{
-  return SystemZ::isImmLF(N->getZExtValue());
+def imm64lf32 : Immediate<i64, 0, [{
+  return SystemZ::isImmLF(Imm);
 }], LF32, "U32Imm">;
 
-def imm64hf32 : Immediate<i64, [{
-  return SystemZ::isImmHF(N->getZExtValue());
+def imm64hf32 : Immediate<i64, 0, [{
+  return SystemZ::isImmHF(Imm);
 }], HF32, "U32Imm">;
 
 // Immediates for the lower and upper 32 bits of an i64, with the other
 // bits of the i32 being one.
-def imm64lf32c : Immediate<i64, [{
-  return SystemZ::isImmLF(uint64_t(~N->getZExtValue()));
+def imm64lf32c : Immediate<i64, 0, [{
+  return SystemZ::isImmLF(uint64_t(~Imm));
 }], LF32, "U32Imm">;
 
-def imm64hf32c : Immediate<i64, [{
-  return SystemZ::isImmHF(uint64_t(~N->getZExtValue()));
+def imm64hf32c : Immediate<i64, 0, [{
+  return SystemZ::isImmHF(uint64_t(~Imm));
 }], HF32, "U32Imm">;
 
 // Short immediates.
-def imm64sx8 : Immediate<i64, [{
-  return isInt<8>(N->getSExtValue());
+def imm64sx8 : Immediate<i64, 1, [{
+  return isInt<8>(Imm);
 }], SIMM8, "S8Imm">;
 
-def imm64zx8 : Immediate<i64, [{
-  return isUInt<8>(N->getSExtValue());
+def imm64zx8 : Immediate<i64, 1, [{
+  return isUInt<8>(Imm);
 }], UIMM8, "U8Imm">;
 
-def imm64sx16 : Immediate<i64, [{
-  return isInt<16>(N->getSExtValue());
+def imm64sx16 : Immediate<i64, 1, [{
+  return isInt<16>(Imm);
 }], SIMM16, "S16Imm">;
 
-def imm64zx16 : Immediate<i64, [{
-  return isUInt<16>(N->getZExtValue());
+def imm64zx16 : Immediate<i64, 0, [{
+  return isUInt<16>(Imm);
 }], UIMM16, "U16Imm">;
 
-def imm64sx32 : Immediate<i64, [{
-  return isInt<32>(N->getSExtValue());
+def imm64sx32 : Immediate<i64, 1, [{
+  return isInt<32>(Imm);
 }], SIMM32, "S32Imm">;
 
-def imm64zx32 : Immediate<i64, [{
-  return isUInt<32>(N->getZExtValue());
+def imm64zx32 : Immediate<i64, 0, [{
+  return isUInt<32>(Imm);
 }], UIMM32, "U32Imm">;
 
-def imm64zx32n : Immediate<i64, [{
-  return isUInt<32>(-N->getSExtValue());
+def imm64zx32n : Immediate<i64, 1, [{
+  return isUInt<32>(-Imm);
 }], NEGIMM32, "U32Imm">;
 
-def imm64zx48 : Immediate<i64, [{
-  return isUInt<64>(N->getZExtValue());
+def imm64zx48 : Immediate<i64, 0, [{
+  return isUInt<64>(Imm);
 }], UIMM48, "U48Imm">;
 
 def imm64 : ImmLeaf<i64, [{}]>, Operand<i64>;
 
 //===----------------------------------------------------------------------===//
 // Floating-point immediates
 //===----------------------------------------------------------------------===//
 

 //===----------------------------------------------------------------------===//
 
 // Access registers.  At present we just use them for accessing the thread
 // pointer, so we don't expose them as register to LLVM.
 def AccessReg : AsmOperandClass {
   let Name = "AccessReg";
   let ParserMethod = "parseAccessReg";
 }
-def access_reg : Immediate<i32, [{ return N->getZExtValue() < 16; }],
+def access_reg : Immediate<i32, 0, [{ return Imm < 16; }],
                            NOOP_SDNodeXForm, "AccessReg"> {
   let ParserMatchClass = AccessReg;
 }
 
 // A 4-bit condition-code mask.
-def cond4 : PatLeaf<(i32 imm), [{ return (N->getZExtValue() < 16); }]>,
+def cond4 : ZExtImmLeaf<i32, [{ return (Imm < 16); }]>,
             Operand<i32> {
   let PrintMethod = "printCond4Operand";
 }

llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp

public:
     bool tryBRIND(SDNode *N);
 
     /// getI32Imm - Return a target constant with the specified value, of type
     /// i32.
     inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) {
       return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
     }
 
-    inline bool immMskBitp(SDNode *inN) const {
-      ConstantSDNode *N = cast<ConstantSDNode>(inN);
-      uint32_t value = (uint32_t)N->getZExtValue();
+    inline bool immMskBitp(uint32_t value) const {
       if (!isMask_32(value)) {
         return false;
       }
       int msksize = 32 - countLeadingZeros(value);
       return (msksize >= 1 && msksize <= 8) ||
               msksize == 16 || msksize == 24 || msksize == 32;
     }
 

 }
 
 void XCoreDAGToDAGISel::Select(SDNode *N) {
   SDLoc dl(N);
   switch (N->getOpcode()) {
   default: break;
   case ISD::Constant: {
     uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
-    if (immMskBitp(N)) {
+    if (immMskBitp(Val)) {
       // Transformation function: get the size of a mask
       // Look for the first non-zero bit
       SDValue MskSize = getI32Imm(32 - countLeadingZeros((uint32_t)Val), dl);
       ReplaceNode(N, CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
                                             MVT::i32, MskSize));
       return;
     }
     else if (!isUInt<16>(Val)) {

llvm/lib/Target/XCore/XCoreInstrInfo.td

 
 def div4neg_xform : SDNodeXForm<imm, [{
   // Transformation function: -imm/4
   uint32_t value = N->getZExtValue();
   assert(-value % 4 == 0);
   return getI32Imm(-value/4, SDLoc(N));
 }]>;
 
-def immUs4Neg : PatLeaf<(imm), [{
-  uint32_t value = (uint32_t)N->getZExtValue();
+def immUs4Neg : ZExtImmLeaf<i32, [{
+  uint32_t value = (uint32_t)Imm;
   return (-value)%4 == 0 && (-value)/4 <= 11;
 }]>;
 
-def immUs4 : PatLeaf<(imm), [{
-  uint32_t value = (uint32_t)N->getZExtValue();
+def immUs4 : ZExtImmLeaf<i32, [{
+  uint32_t value = (uint32_t)Imm;
   return value%4 == 0 && value/4 <= 11;
 }]>;
 
-def immUsNeg : PatLeaf<(imm), [{
-  return -((uint32_t)N->getZExtValue()) <= 11;
+def immUsNeg : ZExtImmLeaf<i32, [{
+  return -((uint32_t)Imm) <= 11;
 }]>;
 
-def immUs : PatLeaf<(imm), [{
-  return (uint32_t)N->getZExtValue() <= 11;
+def immUs : ZExtImmLeaf<i32, [{
+  return (uint32_t)Imm <= 11;
 }]>;
 
-def immU6 : PatLeaf<(imm), [{
-  return (uint32_t)N->getZExtValue() < (1 << 6);
+def immU6 : ZExtImmLeaf<i32, [{
+  return (uint32_t)Imm < (1 << 6);
 }]>;
 
-def immU16 : PatLeaf<(imm), [{
-  return (uint32_t)N->getZExtValue() < (1 << 16);
+def immU16 : ZExtImmLeaf<i32, [{
+  return (uint32_t)Imm < (1 << 16);
 }]>;
 
-def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;
+def immMskBitp : ZExtImmLeaf<i32, [{ return immMskBitp(Imm); }]>;
 
-def immBitp : PatLeaf<(imm), [{
-  uint32_t value = (uint32_t)N->getZExtValue();
+def immBitp : ZExtImmLeaf<i32, [{
+  uint32_t value = (uint32_t)Imm;
   return (value >= 1 && value <= 8)
           || value == 16
           || value == 24
           || value == 32;
 }]>;
 
-def immBpwSubBitp : PatLeaf<(imm), [{
-  uint32_t value = (uint32_t)N->getZExtValue();
+def immBpwSubBitp : ZExtImmLeaf<i32, [{
+  uint32_t value = (uint32_t)Imm;
   return (value >= 24 && value <= 31)
           || value == 16
           || value == 8
           || value == 0;
 }]>;
 
 def lda16f : PatFrag<(ops node:$addr, node:$offset),
                      (add node:$addr, (shl node:$offset, 1))>;

llvm/utils/TableGen/CodeGenDAGPatterns.cpp

 /// getCodeToRunOnSDNode - Return the code for the function body that
 /// evaluates this predicate.  The argument is expected to be in "Node",
 /// not N.  This handles casting and conversion to a concrete node type as
 /// appropriate.
 std::string TreePredicateFn::getCodeToRunOnSDNode() const {
   // Handle immediate predicates first.
   std::string ImmCode = getImmCode();
   if (!ImmCode.empty()) {
-    std::string Result =
+    std::string Result;
+    if (PatFragRec->getRecord()->getValueAsBit("Signed"))
+      Result =
         "    int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();\n";
+    else
+      Result =
+        "    uint64_t Imm = cast<ConstantSDNode>(Node)->getZExtValue();\n";
     return Result + ImmCode;
   }
   
   // Handle arbitrary node predicates.
   assert(!getPredCode().empty() && "Don't have any predicate code!");
   std::string ClassName;
   if (PatFragRec->getOnlyTree()->isLeaf())
     ClassName = "SDNode";

llvm/utils/TableGen/FastISelEmitter.cpp

for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
       if (Code == 0) continue;
 
       if (EmittedAnything)
         OS << " &&\n        ";
 
       TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1);
 
       // Emit the type check.
-      OS << "VT == "
-         << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0))
-         << " && ";
-
+      TreePatternNode *Tree = PredFn.getOrigPatFragRecord()->getTree(0);
+      if (Tree->hasTypeSet(0))
+        OS << "VT == " << getEnumName(Tree->getType(0)) << " && ";
 
       OS << PredFn.getFnName() << "(imm" << i <<')';
       EmittedAnything = true;
     }
   }
 
   /// initialize - Examine the given pattern and initialize the contents
   /// of the Operands array accordingly. Return true if all the operands
for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
           // immediates anyway.
           if (Op->getPredicateFns().size() > 1 ||
               !PredFn.isImmediatePattern())
             return false;
           // Ignore any instruction with 'FastIselShouldIgnore', these are
           // not needed and just bloat the fast instruction selector.  For
           // example, X86 doesn't need to generate code to match ADD16ri8 since
           // ADD16ri will do just fine.
+          // Also ignore instructions with Signed == 0, as the operand we
+          // receive is sign extended.
           Record *Rec = PredFn.getOrigPatFragRecord()->getRecord();
-          if (Rec->getValueAsBit("FastIselShouldIgnore"))
+          if (Rec->getValueAsBit("FastIselShouldIgnore") ||
+              !Rec->getValueAsBit("Signed"))
             return false;
 
           PredNo = ImmediatePredicates.getIDFor(PredFn)+1;
         }
 
         // Handle unmatched immediate sizes here.
         //if (Op->getType(0) != VT)
         //  return false;