CodeGen: Sign extend immediates passed to FastISel entry points instead of zero extending them.

[pcc]

Summary

The purpose of this change is to ensure that ImmLeaf predicates are evaluated
consistently between SelectionDAG and FastISel. This is necessary for an
upcoming change that will allow ImmLeaf predicates to take a zero extended
immediate.

The test case change is benign; the high bits of the value being loaded into
the register are masked off by a later instruction.

llvm/include/llvm/CodeGen/FastISel.h

protected:
   /// instruction with the given type, opcode, and register operands be emitted.
   virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
                                bool Op0IsKill, unsigned Op1, bool Op1IsKill);
 
   /// \brief This method is called by target-independent code to request that an
   /// instruction with the given type, opcode, and register and immediate
   // operands be emitted.
   virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
-                               bool Op0IsKill, uint64_t Imm);
+                               bool Op0IsKill, int64_t Imm);
 
   /// \brief This method is a wrapper of fastEmit_ri.
   ///
   /// It first tries to emit an instruction with an immediate operand using
   /// fastEmit_ri.  If that fails, it materializes the immediate into a register
   /// and try fastEmit_rr instead.
   unsigned fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill,
-                        uint64_t Imm, MVT ImmType);
+                        int64_t Imm, MVT ImmType);
 
   /// \brief This method is called by target-independent code to request that an
   /// instruction with the given type, opcode, and immediate operand be emitted.
-  virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
+  virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, int64_t Imm);
 
   /// \brief This method is called by target-independent code to request that an
   /// instruction with the given type, opcode, and floating-point immediate
   /// operand be emitted.
   virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
                               const ConstantFP *FPImm);
 
   /// \brief Emit a MachineInstr with no operands and a result register in the

llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

unsigned FastISel::getRegForValue(const Value *V) {
 
   return Reg;
 }
 
 unsigned FastISel::materializeConstant(const Value *V, MVT VT) {
   unsigned Reg = 0;
   if (const auto *CI = dyn_cast<ConstantInt>(V)) {
     if (CI->getValue().getActiveBits() <= 64)
-      Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
+      Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getSExtValue());
   } else if (isa<AllocaInst>(V))
     Reg = fastMaterializeAlloca(cast<AllocaInst>(V));
   else if (isa<ConstantPointerNull>(V))
     // Translate this as an integer zero so that it can be
     // local-CSE'd with actual integer zeros.
     Reg = getRegForValue(
         Constant::getNullValue(DL.getIntPtrType(V->getContext())));
   else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
     if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
       unsigned Op1 = getRegForValue(I->getOperand(1));
       if (!Op1)
         return false;
       bool Op1IsKill = hasTrivialKill(I->getOperand(1));
 
       unsigned ResultReg =
           fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, Op1IsKill,
-                       CI->getZExtValue(), VT.getSimpleVT());
+                       CI->getSExtValue(), VT.getSimpleVT());
       if (!ResultReg)
         return false;
 
       // We successfully emitted code for the given LLVM Instruction.
       updateValueMap(I, ResultReg);
       return true;
     }
 
   unsigned Op0 = getRegForValue(I->getOperand(0));
   if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
     return false;
   bool Op0IsKill = hasTrivialKill(I->getOperand(0));
 
   // Check if the second operand is a constant and handle it appropriately.
   if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
-    uint64_t Imm = CI->getSExtValue();
+    int64_t Imm = CI->getSExtValue();
 
     // Transform "sdiv exact X, 8" -> "sra X, 3".
     if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
         cast<BinaryOperator>(I)->isExact() && isPowerOf2_64(Imm)) {
       Imm = Log2_64(Imm);
       ISDOpcode = ISD::SRA;
     }
 

 }
 
 unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, unsigned /*Op0*/,
                                bool /*Op0IsKill*/, unsigned /*Op1*/,
                                bool /*Op1IsKill*/) {
   return 0;
 }
 
-unsigned FastISel::fastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
+unsigned FastISel::fastEmit_i(MVT, MVT, unsigned, int64_t /*Imm*/) {
   return 0;
 }
 
 unsigned FastISel::fastEmit_f(MVT, MVT, unsigned,
                               const ConstantFP * /*FPImm*/) {
   return 0;
 }
 
 unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
-                               bool /*Op0IsKill*/, uint64_t /*Imm*/) {
+                               bool /*Op0IsKill*/, int64_t /*Imm*/) {
   return 0;
 }
 
 /// This method is a wrapper of fastEmit_ri. It first tries to emit an
 /// instruction with an immediate operand using fastEmit_ri.
 /// If that fails, it materializes the immediate into a register and try
 /// fastEmit_rr instead.
 unsigned FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,
-                                bool Op0IsKill, uint64_t Imm, MVT ImmType) {
+                                bool Op0IsKill, int64_t Imm, MVT ImmType) {
   // If this is a multiply by a power of two, emit this as a shift left.
   if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
     Opcode = ISD::SHL;
     Imm = Log2_64(Imm);
   } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
     // div x, 8 -> srl x, 3
     Opcode = ISD::SRL;
     Imm = Log2_64(Imm);
   }
 
   // Horrible hack (to be removed), check to make sure shift amounts are
   // in-range.
   if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
-      Imm >= VT.getSizeInBits())
+      ((uint64_t)Imm) >= VT.getSizeInBits())
     return 0;
 
   // First check if immediate type is legal. If not, we can't use the ri form.
   unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
   if (ResultReg)
     return ResultReg;
   unsigned MaterialReg = fastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
   bool IsImmKill = true;

llvm/lib/Target/PowerPC/PPCFastISel.cpp

class PPCFastISel final : public FastISel {
   // Backend specific FastISel code.
   private:
     bool fastSelectInstruction(const Instruction *I) override;
     unsigned fastMaterializeConstant(const Constant *C) override;
     unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
     bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
                              const LoadInst *LI) override;
     bool fastLowerArguments() override;
-    unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
+    unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, int64_t Imm) override;
     unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
                              const TargetRegisterClass *RC,
                              unsigned Op0, bool Op0IsKill,
                              uint64_t Imm);
     unsigned fastEmitInst_r(unsigned MachineInstOpcode,
                             const TargetRegisterClass *RC,
                             unsigned Op0, bool Op0IsKill);
     unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
bool PPCFastISel::fastLowerArguments() {
   // efficient.  Consider doing something like ARM to handle the
   // case where all args fit in registers, no varargs, no float
   // or vector args.
   return false;
 }
 
 // Handle materializing integer constants into a register.  This is not
 // automatically generated for PowerPC, so must be explicitly created here.
-unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
+unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, int64_t Imm) {
 
   if (Opc != ISD::Constant)
     return 0;
 
   // If we're using CR bit registers for i1 values, handle that as a special
   // case first.
   if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
     unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);

llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll

 define i32 @t2() {
 entry:
 ; CHECK-LABEL: t2
 ; CHECK:       mov [[REG1:x[0-9]+]], xzr
 ; CHECK:       orr w1, wzr, #0xfffffff8
 ; CHECK:       orr [[REG2:w[0-9]+]], wzr, #0x3ff
 ; CHECK:       orr [[REG3:w[0-9]+]], wzr, #0x2
 ; CHECK:       mov [[REG4:w[0-9]+]], wzr
-; CHECK:       orr [[REG5:w[0-9]+]], wzr, #0x1
+; CHECK:       mov [[REG5:w[0-9]+]], #-1
 ; CHECK:       mov x0, [[REG1]]
 ; CHECK:       uxth w2, [[REG2]]
 ; CHECK:       sxtb w3, [[REG3]]
 ; CHECK:       and w4, [[REG4]], #0x1
 ; CHECK:       and w5, [[REG5]], #0x1
 ; CHECK:       bl _func2
   %call = call i32 @func2(i64 zeroext 0, i32 signext -8, i16 zeroext 1023, i8 signext -254, i1 zeroext 0, i1 zeroext 1)
   ret i32 0

llvm/utils/TableGen/FastISelEmitter.cpp

bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target,
     return true;
   }
 
   void PrintParameters(raw_ostream &OS) const {
     for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
       if (Operands[i].isReg()) {
         OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
       } else if (Operands[i].isImm()) {
-        OS << "uint64_t imm" << i;
+        OS << "int64_t imm" << i;
       } else if (Operands[i].isFP()) {
         OS << "const ConstantFP *f" << i;
       } else {
         llvm_unreachable("Unknown operand kind!");
       }
       if (i + 1 != e)
         OS << ", ";
     }