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Differential D16

Big test
AbandonedPublic

Authored by klimek on Aug 2 2012, 11:19 PM.

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klimek abandoned this revision.Aug 22 2012, 11:00 AM
compnerd mentioned this in rL227603: ARM: further correct .fpu directive handling.Jan 30 2015, 11:37 AM
hans mentioned this in rL227854: Merging r227603:.Feb 2 2015, 12:47 PM
nhaehnle mentioned this in D13894: AMDGPU: buffer.load.format intrinsic and si-load-shrink pass.Oct 20 2015, 6:32 AM
cfang mentioned this in D23286: AMDGPU/SI: Propose to redefine image load/store intrinsics.Aug 11 2016, 3:24 PM
cfang mentioned this in D38906: AMDGPU/SI: Implement d16 support for buffer intrinsics.Nov 3 2017, 3:38 PM
cfang mentioned this in D39912: AMDGPU/SI: Implement d16 support for image intrinsics.Nov 16 2017, 11:03 AM
cfang mentioned this in D42596: AMDGPU/SI: Add decoding in the GFX80_UNPACKED decoding namespace..Jan 29 2018, 12:06 PM
Diffusion mentioned this in rL323988: AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the….Feb 1 2018, 10:45 AM
kzhuravl mentioned this in D46366: AMDGPU: Add D16 instructions preserve unused bits feature.May 3 2018, 8:38 PM
kzhuravl mentioned this in rL331551: AMDGPU: Add D16 instructions preserve unused bits feature.May 4 2018, 1:11 PM
nhaehnle mentioned this in D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand.May 27 2018, 1:55 PM
nhaehnle mentioned this in D48017: AMDGPU: Select MIMG instructions manually in SITargetLowering.Jun 11 2018, 5:50 AM
nhaehnle mentioned this in D48165: InstCombine/AMDGPU: Add dimension-aware image intrinsics to SimplifyDemanded.Jun 14 2018, 6:18 AM
Diffusion mentioned this in rL335222: AMDGPU: Turn D16 for MIMG instructions into a regular operand.Jun 21 2018, 6:40 AM
Diffusion mentioned this in rL335228: AMDGPU: Select MIMG instructions manually in SITargetLowering.
Diffusion mentioned this in rL335230: InstCombine/AMDGPU: Add dimension-aware image intrinsics to SimplifyDemanded.
nhaehnle mentioned this in D48826: [AMDGPU] Add support for TFE/LWE in image intrinsics.Jul 27 2018, 7:13 AM
efriedma mentioned this in D67375: [ARM] VFPv2 only supports 16 D registers..Sep 9 2019, 3:30 PM
efriedma mentioned this in rL372186: [ARM] VFPv2 only supports 16 D registers..Sep 17 2019, 2:44 PM
efriedma mentioned this in rGddf5e86c222c: [ARM] VFPv2 only supports 16 D registers..
rdomingu mentioned this in D81172: [AMDGPU] Implement hardware bug workaround for image instructions.Jun 4 2020, 8:57 AM
t-tye mentioned this in D85882: [AMDGPU] Update subtarget features for new target ID support.Aug 13 2020, 8:14 AM
rdomingu mentioned this in rGf71f5f39f670: [AMDGPU] Implement hardware bug workaround for image instructions.Oct 7 2020, 5:04 AM
cfang mentioned this in D130537: AMDGPU: Take care of "tied" operand when removeOperand.Jul 25 2022, 7:06 PM
arsenm mentioned this in D140537: AMDGPU/SIInsertWait: Skip dummy tied source.Dec 22 2022, 4:08 AM
ruiling mentioned this in rG9119d9bfcef4: AMDGPU/SIInsertWait: Skip dummy tied source.Jan 10 2023, 6:00 PM
Petar.Avramovic mentioned this in D145081: AMDGPU: Add more flat scratch load and store tests for 8 and 16-bit types.Mar 1 2023, 10:04 AM
Petar.Avramovic mentioned this in rGc77bd1fe15fe: AMDGPU: Add more flat scratch load and store tests for 8 and 16-bit types.Mar 2 2023, 4:22 AM

Revision Contents

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Diff 39

www/builtins.py

#!/usr/bin/env python #!/usr/bin/env python
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import sys, fileinput import sys, fileinput
err=0 err=0
# Giant associative set of builtin->intrinsic mappings where clang doesn't # Giant associative set of builtin->intrinsic mappings where clang doesn't
# implement the builtin since the vector operation works by default. # implement the builtin since the vector operation works by default.
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repl_map = { repl_map = {
'__builtin_ia32_addps': '_mm_add_ps', '__builtin_ia32_addps': '_mm_add_ps',
'__builtin_ia32_addsd': '_mm_add_sd', '__builtin_ia32_addsd': '_mm_add_sd',
'__builtin_ia32_addpd': '_mm_add_pd', '__builtin_ia32_addpd': '_mm_add_pd',
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'__builtin_ia32_addss': '_mm_add_ss', '__builtin_ia32_addss': '_mm_add_ss',
'__builtin_ia32_paddb128': '_mm_add_epi8', '__builtin_ia32_paddb128': '_mm_add_epi8',
'__builtin_ia32_paddw128': '_mm_add_epi16', '__builtin_ia32_paddw128': '_mm_add_epi16',
'__builtin_ia32_paddd128': '_mm_add_epi32', '__builtin_ia32_paddd128': '_mm_add_epi32',
'__builtin_ia32_paddq128': '_mm_add_epi64', '__builtin_ia32_paddq128': '_mm_add_epi64',
'__builtin_ia32_subps': '_mm_sub_ps', '__builtin_ia32_subps': '_mm_sub_ps',
'__builtin_ia32_subsd': '_mm_sub_sd', '__builtin_ia32_subsd': '_mm_sub_sd',
'__builtin_ia32_subpd': '_mm_sub_pd', '__builtin_ia32_subpd': '_mm_sub_pd',
'__builtin_ia32_subss': '_mm_sub_ss', '__builtin_ia32_subss': '_mm_sub_ss',
'__builtin_ia32_psubb128': '_mm_sub_epi8', '__builtin_ia32_psubb128': '_mm_sub_epi8',
'__builtin_ia32_psubw128': '_mm_sub_epi16', '__builtin_ia32_psubw128': '_mm_sub_epi16',
'__builtin_ia32_psubd128': '_mm_sub_epi32', '__builtin_ia32_psubd128': '_mm_sub_epi32',
'__builtin_ia32_psubq128': '_mm_sub_epi64', '__builtin_ia32_psubq128': '_mm_sub_epi64',
'__builtin_ia32_mulsd': '_mm_mul_sd', '__builtin_ia32_mulsd': '_mm_mul_sd',
'__builtin_ia32_mulpd': '_mm_mul_pd', '__builtin_ia32_mulpd': '_mm_mul_pd',
'__builtin_ia32_mulps': '_mm_mul_ps', '__builtin_ia32_mulps': '_mm_mul_ps',
'__builtin_ia32_mulss': '_mm_mul_ss', '__builtin_ia32_mulss': '_mm_mul_ss',
'__builtin_ia32_pmullw128': '_mm_mullo_epi16', '__builtin_ia32_pmullw128': '_mm_mullo_epi16',
'__builtin_ia32_divsd': '_mm_div_sd', '__builtin_ia32_divsd': '_mm_div_sd',
'__builtin_ia32_divpd': '_mm_div_pd', '__builtin_ia32_divpd': '_mm_div_pd',
'__builtin_ia32_divps': '_mm_div_ps', '__builtin_ia32_divps': '_mm_div_ps',
'__builtin_ia32_subss': '_mm_div_ss', '__builtin_ia32_subss': '_mm_div_ss',
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test

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'__builtin_ia32_andpd': '_mm_and_pd', '__builtin_ia32_andpd': '_mm_and_pd',
'__builtin_ia32_andps': '_mm_and_ps', '__builtin_ia32_andps': '_mm_and_ps',
'__builtin_ia32_pand128': '_mm_and_si128', '__builtin_ia32_pand128': '_mm_and_si128',
'__builtin_ia32_andnpd': '_mm_andnot_pd', '__builtin_ia32_andnpd': '_mm_andnot_pd',
'__builtin_ia32_andnps': '_mm_andnot_ps', '__builtin_ia32_andnps': '_mm_andnot_ps',
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sdf

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'__builtin_ia32_pandn128': '_mm_andnot_si128', '__builtin_ia32_pandn128': '_mm_andnot_si128',
'__builtin_ia32_orpd': '_mm_or_pd', '__builtin_ia32_orpd': '_mm_or_pd',
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test

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'__builtin_ia32_orps': '_mm_or_ps', '__builtin_ia32_orps': '_mm_or_ps',
'__builtin_ia32_por128': '_mm_or_si128', '__builtin_ia32_por128': '_mm_or_si128',
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d

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'__builtin_ia32_xorpd': '_mm_xor_pd', '__builtin_ia32_xorpd': '_mm_xor_pd',
'__builtin_ia32_xorps': '_mm_xor_ps', '__builtin_ia32_xorps': '_mm_xor_ps',
'__builtin_ia32_pxor128': '_mm_xor_si128', '__builtin_ia32_pxor128': '_mm_xor_si128',
'__builtin_ia32_cvtps2dq': '_mm_cvtps_epi32',
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'__builtin_ia32_cvtsd2ss': '_mm_cvtsd_ss', '__builtin_ia32_cvtsd2ss': '_mm_cvtsd_ss',
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'__builtin_ia32_cvtsi2sd': '_mm_cvtsi32_sd', '__builtin_ia32_cvtsi2sd': '_mm_cvtsi32_sd',
'__builtin_ia32_cvtss2sd': '_mm_cvtss_sd', '__builtin_ia32_cvtss2sd': '_mm_cvtss_sd',
'__builtin_ia32_cvttsd2si': '_mm_cvttsd_si32', '__builtin_ia32_cvttsd2si': '_mm_cvttsd_si32',
'__builtin_ia32_vec_ext_v2df': '_mm_cvtsd_f64', '__builtin_ia32_vec_ext_v2df': '_mm_cvtsd_f64',
'__builtin_ia32_loadhpd': '_mm_loadh_pd', '__builtin_ia32_loadhpd': '_mm_loadh_pd',
'__builtin_ia32_loadlpd': '_mm_loadl_pd', '__builtin_ia32_loadlpd': '_mm_loadl_pd',
'__builtin_ia32_loadlv4si': '_mm_loadl_epi64', '__builtin_ia32_loadlv4si': '_mm_loadl_epi64',
'__builtin_ia32_cmpeqps': '_mm_cmpeq_ps', '__builtin_ia32_cmpeqps': '_mm_cmpeq_ps',
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'__builtin_ia32_cmpneqpd': '_mm_cmpneq_pd', '__builtin_ia32_cmpneqpd': '_mm_cmpneq_pd',
'__builtin_ia32_cmpnltpd': '_mm_cmpnlt_pd', '__builtin_ia32_cmpnltpd': '_mm_cmpnlt_pd',
'__builtin_ia32_cmpnlepd': '_mm_cmpnle_pd', '__builtin_ia32_cmpnlepd': '_mm_cmpnle_pd',
'__builtin_ia32_cmpngtpd': '_mm_cmpngt_pd', '__builtin_ia32_cmpngtpd': '_mm_cmpngt_pd',
'__builtin_ia32_cmpngepd': '_mm_cmpnge_pd', '__builtin_ia32_cmpngepd': '_mm_cmpnge_pd',
'__builtin_ia32_cmpordpd': '_mm_cmpord_pd', '__builtin_ia32_cmpordpd': '_mm_cmpord_pd',
'__builtin_ia32_cmpeqsd': '_mm_cmpeq_sd', '__builtin_ia32_cmpeqsd': '_mm_cmpeq_sd',
'__builtin_ia32_cmpltsd': '_mm_cmplt_sd', '__builtin_ia32_cmpltsd': '_mm_cmplt_sd',
'__builtin_ia32_cmplesd': '_mm_cmple_sd', '__builtin_ia32_cmplesd': '_mm_cmple_sd',
'__builtin_ia32_cmpunordsd': '_mm_cmpunord_sd', '__builtin_ia32_cmpunordsd': '_mm_cmpunord_sd',
'__builtin_ia32_cmpneqsd': '_mm_cmpneq_sd', '__builtin_ia32_cmpneqsd': '_mm_cmpneq_sd',
'__builtin_ia32_cmpnltsd': '_mm_cmpnlt_sd', '__builtin_ia32_cmpnltsd': '_mm_cmpnlt_sd',
'__builtin_ia32_cmpnlesd': '_mm_cmpnle_sd', '__builtin_ia32_cmpnlesd': '_mm_cmpnle_sd',
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sdf

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'__builtin_ia32_cmpordsd': '_mm_cmpord_sd', '__builtin_ia32_cmpordsd': '_mm_cmpord_sd',
'__builtin_ia32_cvtsi642ss': '_mm_cvtsi64_ss', '__builtin_ia32_cvtsi642ss': '_mm_cvtsi64_ss',
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asdf

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'__builtin_ia32_cvttss2si64': '_mm_cvtss_si64', '__builtin_ia32_cvttss2si64': '_mm_cvtss_si64',
'__builtin_ia32_shufps': '_mm_shuffle_ps', '__builtin_ia32_shufps': '_mm_shuffle_ps',
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asdf

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'__builtin_ia32_shufpd': '_mm_shuffle_pd', '__builtin_ia32_shufpd': '_mm_shuffle_pd',
'__builtin_ia32_pshufhw': '_mm_shufflehi_epi16', '__builtin_ia32_pshufhw': '_mm_shufflehi_epi16',
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t2

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t3

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'__builtin_ia32_pshuflw': '_mm_shufflelo_epi16', '__builtin_ia32_pshuflw': '_mm_shufflelo_epi16',
'__builtin_ia32_pshufd': '_mm_shuffle_epi32', '__builtin_ia32_pshufd': '_mm_shuffle_epi32',
'__builtin_ia32_movshdup': '_mm_movehdup_ps', '__builtin_ia32_movshdup': '_mm_movehdup_ps',
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sdf

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'__builtin_ia32_movsldup': '_mm_moveldup_ps', '__builtin_ia32_movsldup': '_mm_moveldup_ps',
'__builtin_ia32_maxps': '_mm_max_ps',
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comment

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'__builtin_ia32_pslldi128': '_mm_slli_epi32',
'__builtin_ia32_vec_set_v16qi': '_mm_insert_epi8', '__builtin_ia32_vec_set_v16qi': '_mm_insert_epi8',
'__builtin_ia32_vec_set_v8hi': '_mm_insert_epi16', '__builtin_ia32_vec_set_v8hi': '_mm_insert_epi16',
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test

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'__builtin_ia32_vec_set_v4si': '_mm_insert_epi32', '__builtin_ia32_vec_set_v4si': '_mm_insert_epi32',
'__builtin_ia32_vec_set_v2di': '_mm_insert_epi64', '__builtin_ia32_vec_set_v2di': '_mm_insert_epi64',
'__builtin_ia32_vec_set_v4hi': '_mm_insert_pi16', '__builtin_ia32_vec_set_v4hi': '_mm_insert_pi16',
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sdf

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'__builtin_ia32_vec_ext_v16qi': '_mm_extract_epi8', '__builtin_ia32_vec_ext_v16qi': '_mm_extract_epi8',
'__builtin_ia32_vec_ext_v8hi': '_mm_extract_epi16', '__builtin_ia32_vec_ext_v8hi': '_mm_extract_epi16',
'__builtin_ia32_vec_ext_v4si': '_mm_extract_epi32', '__builtin_ia32_vec_ext_v4si': '_mm_extract_epi32',
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test

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'__builtin_ia32_vec_ext_v2di': '_mm_extract_epi64', '__builtin_ia32_vec_ext_v2di': '_mm_extract_epi64',
'__builtin_ia32_vec_ext_v4hi': '_mm_extract_pi16', '__builtin_ia32_vec_ext_v4hi': '_mm_extract_pi16',
'__builtin_ia32_vec_ext_v4sf': '_mm_extract_ps' '__builtin_ia32_vec_ext_v4sf': '_mm_extract_ps'
} }
# Special unhandled cases: # Special unhandled cases:
# __builtin_ia32_vec_ext_*(__P, idx) -> _mm_store_sd/_mm_storeh_pd # __builtin_ia32_vec_ext_*(__P, idx) -> _mm_store_sd/_mm_storeh_pd
# depending on index. No abstract insert/extract for these oddly. # depending on index. No abstract insert/extract for these oddly.
unhandled = [ unhandled = [
'__builtin_ia32_vec_ext_v2df', '__builtin_ia32_vec_ext_v2df',
'__builtin_ia32_vec_ext_v2si', '__builtin_ia32_vec_ext_v2si',
] ]
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f

klimek: f
def report_repl(builtin, repl): def report_repl(builtin, repl):
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asdf

klimek: asdf
sys.stderr.write("%s:%d: x86 builtin %s used, replaced with %s\n" % (fileinput.filename(), fileinput.filelineno(), builtin, repl)) sys.stderr.write("%s:%d: x86 builtin %s used, replaced with %s\n" % (fileinput.filename(), fileinput.filelineno(), builtin, repl))
def report_cant(builtin): def report_cant(builtin):
sys.stderr.write("%s:%d: x86 builtin %s used, too many replacements\n" % (fileinput.filename(), fileinput.filelineno(), builtin)) sys.stderr.write("%s:%d: x86 builtin %s used, too many replacements\n" % (fileinput.filename(), fileinput.filelineno(), builtin))
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as

klimek: as
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151

klimek: 151
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test

klimek: test
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last

klimek: last
for line in fileinput.input(inplace=1): for line in fileinput.input(inplace=1):
for builtin, repl in repl_map.iteritems(): for builtin, repl in repl_map.iteritems():
if builtin in line: if builtin in line:
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sss

klimek: sss
line = line.replace(builtin, repl) line = line.replace(builtin, repl)
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line =

klimek: line =
report_repl(builtin, repl) report_repl(builtin, repl)
for unh in unhandled: for unh in unhandled:
if unh in line: if unh in line:
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if

klimek: if
report_cant(unh) report_cant(unh)
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asdf

klimek: asdf
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asdf

klimek: asdf
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report_cant

klimek: report_cant
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cant

klimek: cant
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d

klimek: d
sys.stdout.write(line) sys.stdout.write(line)
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sdf

klimek: sdf
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d

klimek: d
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Wuh?

klimek: Wuh?
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asdf

klimek: asdf
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Wah?

klimek: Wah?
sys.exit(err) sys.exit(err)
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Old

klimek: Old
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Old

klimek: Old
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4

klimek: 4
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asdf

klimek: asdf
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asdf

klimek: asdf
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1234

klimek: 1234
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asdf

klimek: asdf
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asdf

klimek: asdf
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asdf

klimek: asdf
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asdf

klimek: asdf
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sdf

klimek: sdf
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159-161

klimek: 159-161
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New

klimek: New
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New

klimek: New
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New2

klimek: New2
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3

klimek: 3
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adsf

klimek: adsf
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2 lines

klimek: 2 lines
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3

klimek: 3
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234

klimek: 234
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asdf

klimek: asdf
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2

klimek: 2
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22

klimek: 22
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222

klimek: 222
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asdf

klimek: asdf
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asdf

klimek: asdf
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From 161 to 163

klimek: From 161 to 163
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d

klimek: d
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last

klimek: last
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42

klimek: 42
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x

klimek: x
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d

klimek: d
No newline at end of file
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asdf

klimek: asdf
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er

klimek: er
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Debug

klimek: Debug
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yay

klimek: yay
Via Old World