Calls on RISC-V are typically compiled to auipc/jalr pairs to allow
a maximum target range (32-bit pc-relative). In order to optimize calls
to near targets, linker relaxation may replace those pairs with, for
example, single jal instructions.
To allow BOLT to freely reassign function addresses in relaxed binaries,
this patch proposes the following approach:
- Expand all relaxed calls back to auipc/jalr;
- Rely on JITLink to relax those back to shorter forms where possible.
This is implemented by detecting all possible call instructions and
replacing them with PseudoCALL (or PseudoTAIL) instructions. The
RISC-V backend then expands those and adds the necessary relocations for
Since BOLT generally ignores pseudo instruction, this patch makes
MCPlusBuilder::isPseudo virtual so that RISCVMCPlusBuilder can
override it to exclude PseudoCALL and PseudoTAIL.
To ensure JITLink knows about the correct section addresses while
relaxing, reassignment of addresses has been moved to a post-allocation
pass. Note that this is probably the time it had to be done in the
first place since in notifyResolved (where it was done before), all
symbols are supposed to be resolved already.
Depends on D159082