[GlobalISel][Mips] Correct corner case in G_UADDE legalization.

[craig.topper]

Summary

If carryin was 1, and RHS is 0xffffffff we were not giving a carry
out.

In that case Res would be equal to LHS, so Res <u LHS would be false.
But there should be a carry out since carryin+RHS wraps around to 0.

[arsenm]

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

3448

Should probably use an and here, that's more canonical for booleans plus that seems to be what the DAG does

[craig.topper]

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

3448

Are you refering to the code in LegalizeDAG?

I based my implementation off what we get from ExpandIntRes for an ADD in SelectionDAG for RISC-V. That path creates a wide setcc ult that gets legalized to select like the one I used.

You can see this in uaddo.i64 test case in test/CodeGen/RISCV/xaluo.ll for RV32.

[craig.topper]

Use AND+OR.

[craig.topper]

clang-format

[arsenm]

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

3448

Yes, I think it's weird that we're inventing new bugs in code that could be more or less directly ported. In the starter case introducing select of i1 feels wrong

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

case G_UADDO: {
     MIRBuilder.buildAdd(Res, LHS, RHS);
     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
 
     MI.eraseFromParent();
     return Legalized;
   }
   case G_UADDE: {
     auto [Res, CarryOut, LHS, RHS, CarryIn] = MI.getFirst5Regs();
-    LLT Ty = MRI.getType(Res);
+    const LLT CondTy = MRI.getType(CarryOut);
+    const LLT Ty = MRI.getType(Res);
 
     auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS);
     auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn);
     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
-    MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
+
+    auto Res_EQ_LHS = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, CondTy, Res, LHS);
+    auto Res_ULT_LHS =
+        MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CondTy, Res, LHS);
+    auto And = MIRBuilder.buildAnd(CondTy, Res_EQ_LHS, CarryIn);
+    auto Or = MIRBuilder.buildOr(CarryOut, And, Res_ULT_LHS);
 
     MI.eraseFromParent();
     return Legalized;
   }
   case G_USUBO: {
     auto [Res, BorrowOut, LHS, RHS] = MI.getFirst4Regs();
 
     MIRBuilder.buildSub(Res, LHS, RHS);

llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir

bb.1.entry:
     ; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
     ; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.3)
     ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[COPY]]
     ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY]]
     ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[COPY1]]
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
     ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
-    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD2]](s32), [[LOAD1]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD2]](s32), [[LOAD1]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD2]](s32), [[LOAD1]]
+    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[ICMP]]
+    ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[ICMP2]]
     ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[COPY2]]
-    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
-    ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[AND1]]
-    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[LOAD2]]
+    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C]]
+    ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[AND2]]
+    ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD4]](s32), [[LOAD2]]
+    ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[LOAD2]]
+    ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[OR]]
+    ; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[ICMP4]]
     ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[COPY3]]
-    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C]]
-    ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND2]]
+    ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C]]
+    ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]]
     ; MIPS32: $v0 = COPY [[ADD]](s32)
     ; MIPS32: $v1 = COPY [[ADD2]](s32)
     ; MIPS32: $a0 = COPY [[ADD4]](s32)
     ; MIPS32: $a1 = COPY [[ADD6]](s32)
     ; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
     %2:_(s32) = COPY $a0
     %3:_(s32) = COPY $a1
     %4:_(s32) = COPY $a2

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll

 entry:
   %add = add i64 %b, %a
   ret i64 %add
 }
 
 define i128 @add_i128(i128 %a, i128 %b) {
 ; MIPS32-LABEL: add_i128:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    move $8, $4
-; MIPS32-NEXT:    move $3, $5
+; MIPS32-NEXT:    move $3, $4
 ; MIPS32-NEXT:    move $4, $6
 ; MIPS32-NEXT:    addiu $1, $sp, 16
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    addiu $1, $sp, 20
-; MIPS32-NEXT:    lw $6, 0($1)
+; MIPS32-NEXT:    lw $8, 0($1)
 ; MIPS32-NEXT:    addiu $1, $sp, 24
-; MIPS32-NEXT:    lw $5, 0($1)
+; MIPS32-NEXT:    lw $6, 0($1)
 ; MIPS32-NEXT:    addiu $1, $sp, 28
 ; MIPS32-NEXT:    lw $1, 0($1)
-; MIPS32-NEXT:    addu $2, $2, $8
-; MIPS32-NEXT:    sltu $8, $2, $8
-; MIPS32-NEXT:    addu $3, $6, $3
-; MIPS32-NEXT:    andi $8, $8, 1
-; MIPS32-NEXT:    addu $3, $3, $8
-; MIPS32-NEXT:    sltu $6, $3, $6
-; MIPS32-NEXT:    addu $4, $5, $4
-; MIPS32-NEXT:    andi $6, $6, 1
-; MIPS32-NEXT:    addu $4, $4, $6
-; MIPS32-NEXT:    sltu $5, $4, $5
+; MIPS32-NEXT:    addu $2, $2, $3
+; MIPS32-NEXT:    sltu $9, $2, $3
+; MIPS32-NEXT:    addu $3, $8, $5
+; MIPS32-NEXT:    andi $5, $9, 1
+; MIPS32-NEXT:    addu $3, $3, $5
+; MIPS32-NEXT:    xor $5, $3, $8
+; MIPS32-NEXT:    sltiu $5, $5, 1
+; MIPS32-NEXT:    sltu $8, $3, $8
+; MIPS32-NEXT:    and $5, $5, $9
+; MIPS32-NEXT:    or $8, $5, $8
+; MIPS32-NEXT:    addu $4, $6, $4
+; MIPS32-NEXT:    andi $5, $8, 1
+; MIPS32-NEXT:    addu $4, $4, $5
+; MIPS32-NEXT:    xor $5, $4, $6
+; MIPS32-NEXT:    sltiu $5, $5, 1
+; MIPS32-NEXT:    sltu $6, $4, $6
+; MIPS32-NEXT:    and $5, $5, $8
+; MIPS32-NEXT:    or $5, $5, $6
 ; MIPS32-NEXT:    addu $1, $1, $7
 ; MIPS32-NEXT:    andi $5, $5, 1
 ; MIPS32-NEXT:    addu $5, $1, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %add = add i128 %b, %a
   ret i128 %add