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Differential D157772

[RISCV][GISel] Lower G_UADDE, G_UADDO, G_USUBE, and G_USUBO
ClosedPublic

Authored by craig.topper on Aug 11 2023, 11:12 PM.

Details

Reviewers
nitinjohnraj
arsenm
Commits
rG3e569883fa7d: [RISCV][GISel] Lower G_UADDE, G_UADDO, G_USUBE, and G_USUBO
Summary

RISC-V doesn't have flag registers, we need to implement these
with add/sub and compares.

Remove the untested legalization for the signed versions. We can
add it back when we write tests.

Diff Detail

Event Timeline

craig.topper created this revision.Aug 11 2023, 11:12 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 11 2023, 11:12 PM
Herald added subscribers: jobnoorman, luke, VincentWu and 28 others. · View Herald Transcript
craig.topper requested review of this revision.Aug 11 2023, 11:12 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 11 2023, 11:12 PM
Herald added subscribers: wangpc, eopXD, MaskRay, wdng. · View Herald Transcript
Harbormaster completed remote builds in B252085: Diff 549576.Aug 11 2023, 11:53 PM
craig.topper added inline comments.Aug 11 2023, 11:54 PM
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir
110–112

@arsenm Can you check this expansion? It doesn't look correct to me.

Here's the code from LegalizerHelper.

auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS);                             
auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn);                        
MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);                               
MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);

If LHS is 0 and RHS is all ones, and CarryIn is 1. TmpRes will be all ones and Res will be 0. Res will be 0. The ICMP_ULT will be false, but we there was an overflow.

craig.topper marked an inline comment as not done.Aug 14 2023, 6:30 PM
craig.topper added inline comments.
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir
110–112

Patch to fix G_UADDE legalization https://reviews.llvm.org/D157943

craig.topper updated this revision to Diff 551294.Aug 17 2023, 3:24 PM
craig.topper marked an inline comment as not done.

Rebase

Herald added a subscriber: sunshaoce. · View Herald TranscriptAug 17 2023, 3:24 PM
Harbormaster completed remote builds in B253329: Diff 551294.Aug 17 2023, 4:35 PM
nitinjohnraj accepted this revision.Aug 18 2023, 3:58 PM

Thank you for the patch, LGTM

This revision is now accepted and ready to land.Aug 18 2023, 3:58 PM
This revision was landed with ongoing or failed builds.Aug 18 2023, 5:29 PM
Closed by commit rG3e569883fa7d: [RISCV][GISel] Lower G_UADDE, G_UADDO, G_USUBE, and G_USUBO (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG3e569883fa7d: [RISCV][GISel] Lower G_UADDE, G_UADDO, G_USUBE, and G_USUBO.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
GISel/
8 lines
test/
CodeGen/
RISCV/
GlobalISel/
legalizer/
rv32/
50 lines
26 lines
50 lines
rv64/
50 lines
26 lines
50 lines

Diff 551679

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

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using namespace llvm; using namespace llvm;
RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) { RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
const unsigned XLen = ST.getXLen(); const unsigned XLen = ST.getXLen();
const LLT XLenLLT = LLT::scalar(XLen); const LLT XLenLLT = LLT::scalar(XLen);
const LLT DoubleXLenLLT = LLT::scalar(2 * XLen); const LLT DoubleXLenLLT = LLT::scalar(2 * XLen);
const LLT p0 = LLT::pointer(0, XLen); const LLT p0 = LLT::pointer(0, XLen);
const LLT s1 = LLT::scalar(1);
using namespace TargetOpcode; using namespace TargetOpcode;
getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR}) getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR})
.legalFor({XLenLLT}) .legalFor({XLenLLT})
.widenScalarToNextPow2(0) .widenScalarToNextPow2(0)
.clampScalar(0, XLenLLT, XLenLLT); .clampScalar(0, XLenLLT, XLenLLT);
getActionDefinitionsBuilder( getActionDefinitionsBuilder(
{G_UADDE, G_UADDO, G_USUBE, G_USUBO, G_SADDE, G_SADDO, G_SSUBE, G_SSUBO}) {G_UADDE, G_UADDO, G_USUBE, G_USUBO})
.legalFor({{XLenLLT, XLenLLT}}) .lowerFor({{XLenLLT, s1}});
.clampScalar(0, XLenLLT, XLenLLT)
.clampScalar(1, XLenLLT, XLenLLT)
.widenScalarToNextPow2(0);
getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}) getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
.legalFor({{XLenLLT, XLenLLT}}) .legalFor({{XLenLLT, XLenLLT}})
.widenScalarToNextPow2(0) .widenScalarToNextPow2(0)
.clampScalar(1, XLenLLT, XLenLLT) .clampScalar(1, XLenLLT, XLenLLT)
.clampScalar(0, XLenLLT, XLenLLT); .clampScalar(0, XLenLLT, XLenLLT);
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT}) getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
▲ Show 20 Lines • Show All 82 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-add.mir

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name: add_i48 name: add_i48
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: add_i48 ; CHECK-LABEL: name: add_i48
; CHECK: %xlo:_(s32) = COPY $x10 ; CHECK: %xlo:_(s32) = COPY $x10
; CHECK-NEXT: %xhi:_(s32) = COPY $x11 ; CHECK-NEXT: %xhi:_(s32) = COPY $x11
; CHECK-NEXT: %ylo:_(s32) = COPY $x12 ; CHECK-NEXT: %ylo:_(s32) = COPY $x12
; CHECK-NEXT: %yhi:_(s32) = COPY $x13 ; CHECK-NEXT: %yhi:_(s32) = COPY $x13
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO %xlo, %ylo ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD %xlo, %ylo
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), %ylo
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD %xhi, %yhi
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE %xhi, %yhi, [[AND]] ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[UADDO]](s32) ; CHECK-NEXT: $x10 = COPY [[ADD]](s32)
; CHECK-NEXT: $x11 = COPY [[UADDE]](s32) ; CHECK-NEXT: $x11 = COPY [[ADD2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
%xlo:_(s32) = COPY $x10 %xlo:_(s32) = COPY $x10
%xhi:_(s32) = COPY $x11 %xhi:_(s32) = COPY $x11
%ylo:_(s32) = COPY $x12 %ylo:_(s32) = COPY $x12
%yhi:_(s32) = COPY $x13 %yhi:_(s32) = COPY $x13
%x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32) %x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32)
%y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32) %y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32)
%x:_(s48) = G_TRUNC %x0(s64) %x:_(s48) = G_TRUNC %x0(s64)
Show All 10 Lines
name: add_i64 name: add_i64
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: add_i64 ; CHECK-LABEL: name: add_i64
; CHECK: %lo1:_(s32) = COPY $x10 ; CHECK: %lo1:_(s32) = COPY $x10
; CHECK-NEXT: %hi1:_(s32) = COPY $x11 ; CHECK-NEXT: %hi1:_(s32) = COPY $x11
; CHECK-NEXT: %lo2:_(s32) = COPY $x12 ; CHECK-NEXT: %lo2:_(s32) = COPY $x12
; CHECK-NEXT: %hi2:_(s32) = COPY $x13 ; CHECK-NEXT: %hi2:_(s32) = COPY $x13
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO %lo1, %lo2 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD %lo1, %lo2
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), %lo2
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD %hi1, %hi2
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE %hi1, %hi2, [[AND]] ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[UADDO]](s32) ; CHECK-NEXT: $x10 = COPY [[ADD]](s32)
; CHECK-NEXT: $x11 = COPY [[UADDE]](s32) ; CHECK-NEXT: $x11 = COPY [[ADD2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
%lo1:_(s32) = COPY $x10 %lo1:_(s32) = COPY $x10
%hi1:_(s32) = COPY $x11 %hi1:_(s32) = COPY $x11
%lo2:_(s32) = COPY $x12 %lo2:_(s32) = COPY $x12
%hi2:_(s32) = COPY $x13 %hi2:_(s32) = COPY $x13
%x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32)
%x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32)
%y:_(s64) = G_ADD %x1, %x2 %y:_(s64) = G_ADD %x1, %x2
Show All 9 Linesbody: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: add_i96 ; CHECK-LABEL: name: add_i96
; CHECK: %lo1:_(s32) = COPY $x10 ; CHECK: %lo1:_(s32) = COPY $x10
; CHECK-NEXT: %mid1:_(s32) = COPY $x11 ; CHECK-NEXT: %mid1:_(s32) = COPY $x11
; CHECK-NEXT: %hi1:_(s32) = COPY $x12 ; CHECK-NEXT: %hi1:_(s32) = COPY $x12
; CHECK-NEXT: %lo2:_(s32) = COPY $x13 ; CHECK-NEXT: %lo2:_(s32) = COPY $x13
; CHECK-NEXT: %mid2:_(s32) = COPY $x14 ; CHECK-NEXT: %mid2:_(s32) = COPY $x14
; CHECK-NEXT: %hi2:_(s32) = COPY $x15 ; CHECK-NEXT: %hi2:_(s32) = COPY $x15
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO %lo1, %lo2 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD %lo1, %lo2
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), %lo2
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD %mid1, %mid2
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), %mid1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE %mid1, %mid2, [[AND]] ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDE1]], [[C1]] ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD2]](s32), [[C1]]
; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE %hi1, %hi2, [[AND1]] ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[UADDO]](s32) ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[AND1]]
; CHECK-NEXT: $x11 = COPY [[UADDE]](s32) ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD %hi1, %hi2
; CHECK-NEXT: $x12 = COPY [[UADDE2]](s32) ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C2]]
; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[AND2]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s32)
; CHECK-NEXT: $x11 = COPY [[ADD2]](s32)
; CHECK-NEXT: $x12 = COPY [[ADD4]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12
%lo1:_(s32) = COPY $x10 %lo1:_(s32) = COPY $x10
%mid1:_(s32) = COPY $x11 %mid1:_(s32) = COPY $x11
%hi1:_(s32) = COPY $x12 %hi1:_(s32) = COPY $x12
%lo2:_(s32) = COPY $x13 %lo2:_(s32) = COPY $x13
%mid2:_(s32) = COPY $x14 %mid2:_(s32) = COPY $x14
%hi2:_(s32) = COPY $x15 %hi2:_(s32) = COPY $x15
%x1:_(s96) = G_MERGE_VALUES %lo1(s32), %mid1(s32), %hi1(s32) %x1:_(s96) = G_MERGE_VALUES %lo1(s32), %mid1(s32), %hi1(s32)
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llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul-ext.mir

Show First 20 Lines • Show All 154 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK-NEXT: %hi1:_(s32) = COPY $x12 ; CHECK-NEXT: %hi1:_(s32) = COPY $x12
; CHECK-NEXT: %lo2:_(s32) = COPY $x13 ; CHECK-NEXT: %lo2:_(s32) = COPY $x13
; CHECK-NEXT: %mid2:_(s32) = COPY $x14 ; CHECK-NEXT: %mid2:_(s32) = COPY $x14
; CHECK-NEXT: %hi2:_(s32) = COPY $x15 ; CHECK-NEXT: %hi2:_(s32) = COPY $x15
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL %lo1, %lo2 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL %lo1, %lo2
; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL %mid1, %lo2 ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL %mid1, %lo2
; CHECK-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL %lo1, %mid2 ; CHECK-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL %lo1, %mid2
; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH %lo1, %lo2 ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH %lo1, %lo2
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[MUL1]], [[MUL2]] ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL2]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[UADDO2:%[0-9]+]]:_(s32), [[UADDO3:%[0-9]+]]:_(s32) = G_UADDO [[UADDO]], [[UMULH]] ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDO3]], [[C1]] ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C1]]
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]] ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL %hi1, %lo2 ; CHECK-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL %hi1, %lo2
; CHECK-NEXT: [[MUL4:%[0-9]+]]:_(s32) = G_MUL %mid1, %mid2 ; CHECK-NEXT: [[MUL4:%[0-9]+]]:_(s32) = G_MUL %mid1, %mid2
; CHECK-NEXT: [[MUL5:%[0-9]+]]:_(s32) = G_MUL %lo1, %hi2 ; CHECK-NEXT: [[MUL5:%[0-9]+]]:_(s32) = G_MUL %lo1, %hi2
; CHECK-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH %mid1, %lo2 ; CHECK-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH %mid1, %lo2
; CHECK-NEXT: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH %lo1, %mid2 ; CHECK-NEXT: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH %lo1, %mid2
; CHECK-NEXT: [[UADDO4:%[0-9]+]]:_(s32), [[UADDO5:%[0-9]+]]:_(s32) = G_UADDO [[MUL3]], [[MUL4]] ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL3]], [[MUL4]]
; CHECK-NEXT: [[UADDO6:%[0-9]+]]:_(s32), [[UADDO7:%[0-9]+]]:_(s32) = G_UADDO [[UADDO4]], [[MUL5]] ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[MUL5]]
; CHECK-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s32) = G_UADDO [[UADDO6]], [[UMULH1]] ; CHECK-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[UMULH1]]
; CHECK-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s32) = G_UADDO [[UADDO8]], [[UMULH2]] ; CHECK-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[UMULH2]]
; CHECK-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s32) = G_UADDO [[UADDO10]], [[ADD]] ; CHECK-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[ADD2]]
; CHECK-NEXT: $x10 = COPY [[MUL]](s32) ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
; CHECK-NEXT: $x11 = COPY [[UADDO2]](s32) ; CHECK-NEXT: $x11 = COPY [[ADD1]](s32)
; CHECK-NEXT: $x12 = COPY [[UADDO12]](s32) ; CHECK-NEXT: $x12 = COPY [[ADD7]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12
%lo1:_(s32) = COPY $x10 %lo1:_(s32) = COPY $x10
%mid1:_(s32) = COPY $x11 %mid1:_(s32) = COPY $x11
%hi1:_(s32) = COPY $x12 %hi1:_(s32) = COPY $x12
%lo2:_(s32) = COPY $x13 %lo2:_(s32) = COPY $x13
%mid2:_(s32) = COPY $x14 %mid2:_(s32) = COPY $x14
%hi2:_(s32) = COPY $x15 %hi2:_(s32) = COPY $x15
%x1:_(s96) = G_MERGE_VALUES %lo1(s32), %mid1(s32), %hi1(s32) %x1:_(s96) = G_MERGE_VALUES %lo1(s32), %mid1(s32), %hi1(s32)
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llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-sub.mir

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
name: sub_i48 name: sub_i48
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: sub_i48 ; CHECK-LABEL: name: sub_i48
; CHECK: %xlo:_(s32) = COPY $x10 ; CHECK: %xlo:_(s32) = COPY $x10
; CHECK-NEXT: %xhi:_(s32) = COPY $x11 ; CHECK-NEXT: %xhi:_(s32) = COPY $x11
; CHECK-NEXT: %ylo:_(s32) = COPY $x12 ; CHECK-NEXT: %ylo:_(s32) = COPY $x12
; CHECK-NEXT: %yhi:_(s32) = COPY $x13 ; CHECK-NEXT: %yhi:_(s32) = COPY $x13
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO %xlo, %ylo ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %xlo, %ylo
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %xlo(s32), %ylo
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB %xhi, %yhi
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE %xhi, %yhi, [[AND]] ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[USUBO]](s32) ; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
; CHECK-NEXT: $x11 = COPY [[USUBE]](s32) ; CHECK-NEXT: $x11 = COPY [[SUB2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
%xlo:_(s32) = COPY $x10 %xlo:_(s32) = COPY $x10
%xhi:_(s32) = COPY $x11 %xhi:_(s32) = COPY $x11
%ylo:_(s32) = COPY $x12 %ylo:_(s32) = COPY $x12
%yhi:_(s32) = COPY $x13 %yhi:_(s32) = COPY $x13
%x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32) %x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32)
%y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32) %y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32)
%x:_(s48) = G_TRUNC %x0(s64) %x:_(s48) = G_TRUNC %x0(s64)
Show All 10 Lines
name: sub_i64 name: sub_i64
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: sub_i64 ; CHECK-LABEL: name: sub_i64
; CHECK: %lo1:_(s32) = COPY $x10 ; CHECK: %lo1:_(s32) = COPY $x10
; CHECK-NEXT: %hi1:_(s32) = COPY $x11 ; CHECK-NEXT: %hi1:_(s32) = COPY $x11
; CHECK-NEXT: %lo2:_(s32) = COPY $x12 ; CHECK-NEXT: %lo2:_(s32) = COPY $x12
; CHECK-NEXT: %hi2:_(s32) = COPY $x13 ; CHECK-NEXT: %hi2:_(s32) = COPY $x13
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO %lo1, %lo2 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %lo1, %lo2
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo1(s32), %lo2
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB %hi1, %hi2
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE %hi1, %hi2, [[AND]] ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[USUBO]](s32) ; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
; CHECK-NEXT: $x11 = COPY [[USUBE]](s32) ; CHECK-NEXT: $x11 = COPY [[SUB2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
%lo1:_(s32) = COPY $x10 %lo1:_(s32) = COPY $x10
%hi1:_(s32) = COPY $x11 %hi1:_(s32) = COPY $x11
%lo2:_(s32) = COPY $x12 %lo2:_(s32) = COPY $x12
%hi2:_(s32) = COPY $x13 %hi2:_(s32) = COPY $x13
%x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32)
%x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32)
%y:_(s64) = G_SUB %x1, %x2 %y:_(s64) = G_SUB %x1, %x2
Show All 9 Linesbody: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: sub_i96 ; CHECK-LABEL: name: sub_i96
; CHECK: %lo1:_(s32) = COPY $x10 ; CHECK: %lo1:_(s32) = COPY $x10
; CHECK-NEXT: %mid1:_(s32) = COPY $x11 ; CHECK-NEXT: %mid1:_(s32) = COPY $x11
; CHECK-NEXT: %hi1:_(s32) = COPY $x12 ; CHECK-NEXT: %hi1:_(s32) = COPY $x12
; CHECK-NEXT: %lo2:_(s32) = COPY $x13 ; CHECK-NEXT: %lo2:_(s32) = COPY $x13
; CHECK-NEXT: %mid2:_(s32) = COPY $x14 ; CHECK-NEXT: %mid2:_(s32) = COPY $x14
; CHECK-NEXT: %hi2:_(s32) = COPY $x15 ; CHECK-NEXT: %hi2:_(s32) = COPY $x15
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO %lo1, %lo2 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %lo1, %lo2
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo1(s32), %lo2
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB %mid1, %mid2
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[SUB1]](s32), %mid1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE %mid1, %mid2, [[AND]] ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[USUBE1]], [[C1]] ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE %hi1, %hi2, [[AND1]] ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[USUBO]](s32) ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[AND1]]
; CHECK-NEXT: $x11 = COPY [[USUBE]](s32) ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB %hi1, %hi2
; CHECK-NEXT: $x12 = COPY [[USUBE2]](s32) ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C2]]
; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[AND2]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
; CHECK-NEXT: $x11 = COPY [[SUB2]](s32)
; CHECK-NEXT: $x12 = COPY [[SUB4]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12
%lo1:_(s32) = COPY $x10 %lo1:_(s32) = COPY $x10
%mid1:_(s32) = COPY $x11 %mid1:_(s32) = COPY $x11
%hi1:_(s32) = COPY $x12 %hi1:_(s32) = COPY $x12
%lo2:_(s32) = COPY $x13 %lo2:_(s32) = COPY $x13
%mid2:_(s32) = COPY $x14 %mid2:_(s32) = COPY $x14
%hi2:_(s32) = COPY $x15 %hi2:_(s32) = COPY $x15
%x1:_(s96) = G_MERGE_VALUES %lo1(s32), %mid1(s32), %hi1(s32) %x1:_(s96) = G_MERGE_VALUES %lo1(s32), %mid1(s32), %hi1(s32)
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llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
name: add_i72 name: add_i72
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: add_i72 ; CHECK-LABEL: name: add_i72
; CHECK: %x00:_(s64) = COPY $x10 ; CHECK: %x00:_(s64) = COPY $x10
; CHECK-NEXT: %x01:_(s64) = COPY $x11 ; CHECK-NEXT: %x01:_(s64) = COPY $x11
; CHECK-NEXT: %y00:_(s64) = COPY $x12 ; CHECK-NEXT: %y00:_(s64) = COPY $x12
; CHECK-NEXT: %y01:_(s64) = COPY $x13 ; CHECK-NEXT: %y01:_(s64) = COPY $x13
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s64) = G_UADDO %x00, %y00 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD %x00, %y00
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), %y00
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD %x01, %y01
craig.topperAuthorUnsubmitted
Not Done
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@arsenm Can you check this expansion? It doesn't look correct to me.

Here's the code from LegalizerHelper.

auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS);                             
auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn);                        
MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);                               
MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);

If LHS is 0 and RHS is all ones, and CarryIn is 1. TmpRes will be all ones and Res will be 0. Res will be 0. The ICMP_ULT will be false, but we there was an overflow.

craig.topper: @arsenm Can you check this expansion? It doesn't look correct to me. Here's the code from…
craig.topperAuthorUnsubmitted
Not Done
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Patch to fix G_UADDE legalization https://reviews.llvm.org/D157943

craig.topper: Patch to fix G_UADDE legalization https://reviews.llvm.org/D157943
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UADDO1]], [[C]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s64) = G_UADDE %x01, %y01, [[AND]] ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ADD1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[UADDO]](s64) ; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
; CHECK-NEXT: $x11 = COPY [[UADDE]](s64) ; CHECK-NEXT: $x11 = COPY [[ADD2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
%x00:_(s64) = COPY $x10 %x00:_(s64) = COPY $x10
%x01:_(s64) = COPY $x11 %x01:_(s64) = COPY $x11
%y00:_(s64) = COPY $x12 %y00:_(s64) = COPY $x12
%y01:_(s64) = COPY $x13 %y01:_(s64) = COPY $x13
%x0:_(s128) = G_MERGE_VALUES %x00(s64), %x01 %x0:_(s128) = G_MERGE_VALUES %x00(s64), %x01
%y0:_(s128) = G_MERGE_VALUES %y00(s64), %y01 %y0:_(s128) = G_MERGE_VALUES %y00(s64), %y01
%x:_(s72) = G_TRUNC %x0(s128) %x:_(s72) = G_TRUNC %x0(s128)
Show All 10 Lines
name: add_i128 name: add_i128
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: add_i128 ; CHECK-LABEL: name: add_i128
; CHECK: %lo1:_(s64) = COPY $x10 ; CHECK: %lo1:_(s64) = COPY $x10
; CHECK-NEXT: %hi1:_(s64) = COPY $x11 ; CHECK-NEXT: %hi1:_(s64) = COPY $x11
; CHECK-NEXT: %lo2:_(s64) = COPY $x12 ; CHECK-NEXT: %lo2:_(s64) = COPY $x12
; CHECK-NEXT: %hi2:_(s64) = COPY $x13 ; CHECK-NEXT: %hi2:_(s64) = COPY $x13
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s64) = G_UADDO %lo1, %lo2 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD %lo1, %lo2
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), %lo2
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD %hi1, %hi2
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UADDO1]], [[C]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s64) = G_UADDE %hi1, %hi2, [[AND]] ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ADD1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[UADDO]](s64) ; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
; CHECK-NEXT: $x11 = COPY [[UADDE]](s64) ; CHECK-NEXT: $x11 = COPY [[ADD2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
%lo1:_(s64) = COPY $x10 %lo1:_(s64) = COPY $x10
%hi1:_(s64) = COPY $x11 %hi1:_(s64) = COPY $x11
%lo2:_(s64) = COPY $x12 %lo2:_(s64) = COPY $x12
%hi2:_(s64) = COPY $x13 %hi2:_(s64) = COPY $x13
%x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64)
%x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64)
%y:_(s128) = G_ADD %x1, %x2 %y:_(s128) = G_ADD %x1, %x2
Show All 9 Linesbody: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: add_i192 ; CHECK-LABEL: name: add_i192
; CHECK: %lo1:_(s64) = COPY $x10 ; CHECK: %lo1:_(s64) = COPY $x10
; CHECK-NEXT: %mid1:_(s64) = COPY $x11 ; CHECK-NEXT: %mid1:_(s64) = COPY $x11
; CHECK-NEXT: %hi1:_(s64) = COPY $x12 ; CHECK-NEXT: %hi1:_(s64) = COPY $x12
; CHECK-NEXT: %lo2:_(s64) = COPY $x13 ; CHECK-NEXT: %lo2:_(s64) = COPY $x13
; CHECK-NEXT: %mid2:_(s64) = COPY $x14 ; CHECK-NEXT: %mid2:_(s64) = COPY $x14
; CHECK-NEXT: %hi2:_(s64) = COPY $x15 ; CHECK-NEXT: %hi2:_(s64) = COPY $x15
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s64) = G_UADDO %lo1, %lo2 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD %lo1, %lo2
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), %lo2
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD %mid1, %mid2
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD1]](s64), %mid1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UADDO1]], [[C]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s64) = G_UADDE %mid1, %mid2, [[AND]] ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ADD1]], [[AND]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UADDE1]], [[C1]] ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ADD2]](s64), [[C1]]
; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s64) = G_UADDE %hi1, %hi2, [[AND1]] ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[UADDO]](s64) ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ICMP1]], [[AND1]]
; CHECK-NEXT: $x11 = COPY [[UADDE]](s64) ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s64) = G_ADD %hi1, %hi2
; CHECK-NEXT: $x12 = COPY [[UADDE2]](s64) ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C2]]
; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s64) = G_ADD [[ADD3]], [[AND2]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
; CHECK-NEXT: $x11 = COPY [[ADD2]](s64)
; CHECK-NEXT: $x12 = COPY [[ADD4]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12
%lo1:_(s64) = COPY $x10 %lo1:_(s64) = COPY $x10
%mid1:_(s64) = COPY $x11 %mid1:_(s64) = COPY $x11
%hi1:_(s64) = COPY $x12 %hi1:_(s64) = COPY $x12
%lo2:_(s64) = COPY $x13 %lo2:_(s64) = COPY $x13
%mid2:_(s64) = COPY $x14 %mid2:_(s64) = COPY $x14
%hi2:_(s64) = COPY $x15 %hi2:_(s64) = COPY $x15
%x1:_(s192) = G_MERGE_VALUES %lo1(s64), %mid1(s64), %hi1(s64) %x1:_(s192) = G_MERGE_VALUES %lo1(s64), %mid1(s64), %hi1(s64)
Show All 9 Lines

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul-ext.mir

Show First 20 Lines • Show All 174 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK-NEXT: %hi1:_(s64) = COPY $x12 ; CHECK-NEXT: %hi1:_(s64) = COPY $x12
; CHECK-NEXT: %lo2:_(s64) = COPY $x13 ; CHECK-NEXT: %lo2:_(s64) = COPY $x13
; CHECK-NEXT: %mid2:_(s64) = COPY $x14 ; CHECK-NEXT: %mid2:_(s64) = COPY $x14
; CHECK-NEXT: %hi2:_(s64) = COPY $x15 ; CHECK-NEXT: %hi2:_(s64) = COPY $x15
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL %lo1, %lo2 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL %lo1, %lo2
; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL %mid1, %lo2 ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL %mid1, %lo2
; CHECK-NEXT: [[MUL2:%[0-9]+]]:_(s64) = G_MUL %lo1, %mid2 ; CHECK-NEXT: [[MUL2:%[0-9]+]]:_(s64) = G_MUL %lo1, %mid2
; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s64) = G_UMULH %lo1, %lo2 ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s64) = G_UMULH %lo1, %lo2
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s64) = G_UADDO [[MUL1]], [[MUL2]] ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[MUL1]], [[MUL2]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), [[MUL2]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UADDO1]], [[C]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[UADDO2:%[0-9]+]]:_(s64), [[UADDO3:%[0-9]+]]:_(s64) = G_UADDO [[UADDO]], [[UMULH]] ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[UMULH]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD1]](s64), [[UMULH]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UADDO3]], [[C1]] ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C1]]
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND]], [[AND1]] ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[AND]], [[AND1]]
; CHECK-NEXT: [[MUL3:%[0-9]+]]:_(s64) = G_MUL %hi1, %lo2 ; CHECK-NEXT: [[MUL3:%[0-9]+]]:_(s64) = G_MUL %hi1, %lo2
; CHECK-NEXT: [[MUL4:%[0-9]+]]:_(s64) = G_MUL %mid1, %mid2 ; CHECK-NEXT: [[MUL4:%[0-9]+]]:_(s64) = G_MUL %mid1, %mid2
; CHECK-NEXT: [[MUL5:%[0-9]+]]:_(s64) = G_MUL %lo1, %hi2 ; CHECK-NEXT: [[MUL5:%[0-9]+]]:_(s64) = G_MUL %lo1, %hi2
; CHECK-NEXT: [[UMULH1:%[0-9]+]]:_(s64) = G_UMULH %mid1, %lo2 ; CHECK-NEXT: [[UMULH1:%[0-9]+]]:_(s64) = G_UMULH %mid1, %lo2
; CHECK-NEXT: [[UMULH2:%[0-9]+]]:_(s64) = G_UMULH %lo1, %mid2 ; CHECK-NEXT: [[UMULH2:%[0-9]+]]:_(s64) = G_UMULH %lo1, %mid2
; CHECK-NEXT: [[UADDO4:%[0-9]+]]:_(s64), [[UADDO5:%[0-9]+]]:_(s64) = G_UADDO [[MUL3]], [[MUL4]] ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s64) = G_ADD [[MUL3]], [[MUL4]]
; CHECK-NEXT: [[UADDO6:%[0-9]+]]:_(s64), [[UADDO7:%[0-9]+]]:_(s64) = G_UADDO [[UADDO4]], [[MUL5]] ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s64) = G_ADD [[ADD3]], [[MUL5]]
; CHECK-NEXT: [[UADDO8:%[0-9]+]]:_(s64), [[UADDO9:%[0-9]+]]:_(s64) = G_UADDO [[UADDO6]], [[UMULH1]] ; CHECK-NEXT: [[ADD5:%[0-9]+]]:_(s64) = G_ADD [[ADD4]], [[UMULH1]]
; CHECK-NEXT: [[UADDO10:%[0-9]+]]:_(s64), [[UADDO11:%[0-9]+]]:_(s64) = G_UADDO [[UADDO8]], [[UMULH2]] ; CHECK-NEXT: [[ADD6:%[0-9]+]]:_(s64) = G_ADD [[ADD5]], [[UMULH2]]
; CHECK-NEXT: [[UADDO12:%[0-9]+]]:_(s64), [[UADDO13:%[0-9]+]]:_(s64) = G_UADDO [[UADDO10]], [[ADD]] ; CHECK-NEXT: [[ADD7:%[0-9]+]]:_(s64) = G_ADD [[ADD6]], [[ADD2]]
; CHECK-NEXT: $x10 = COPY [[MUL]](s64) ; CHECK-NEXT: $x10 = COPY [[MUL]](s64)
; CHECK-NEXT: $x11 = COPY [[UADDO2]](s64) ; CHECK-NEXT: $x11 = COPY [[ADD1]](s64)
; CHECK-NEXT: $x12 = COPY [[UADDO12]](s64) ; CHECK-NEXT: $x12 = COPY [[ADD7]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12
%lo1:_(s64) = COPY $x10 %lo1:_(s64) = COPY $x10
%mid1:_(s64) = COPY $x11 %mid1:_(s64) = COPY $x11
%hi1:_(s64) = COPY $x12 %hi1:_(s64) = COPY $x12
%lo2:_(s64) = COPY $x13 %lo2:_(s64) = COPY $x13
%mid2:_(s64) = COPY $x14 %mid2:_(s64) = COPY $x14
%hi2:_(s64) = COPY $x15 %hi2:_(s64) = COPY $x15
%x1:_(s192) = G_MERGE_VALUES %lo1(s64), %mid1(s64), %hi1(s64) %x1:_(s192) = G_MERGE_VALUES %lo1(s64), %mid1(s64), %hi1(s64)
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llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir

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name: sub_i72 name: sub_i72
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: sub_i72 ; CHECK-LABEL: name: sub_i72
; CHECK: %x00:_(s64) = COPY $x10 ; CHECK: %x00:_(s64) = COPY $x10
; CHECK-NEXT: %x01:_(s64) = COPY $x11 ; CHECK-NEXT: %x01:_(s64) = COPY $x11
; CHECK-NEXT: %y00:_(s64) = COPY $x12 ; CHECK-NEXT: %y00:_(s64) = COPY $x12
; CHECK-NEXT: %y01:_(s64) = COPY $x13 ; CHECK-NEXT: %y01:_(s64) = COPY $x13
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s64) = G_USUBO %x00, %y00 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %x00, %y00
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %x00(s64), %y00
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB %x01, %y01
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[USUBO1]], [[C]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s64) = G_USUBE %x01, %y01, [[AND]] ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[USUBO]](s64) ; CHECK-NEXT: $x10 = COPY [[SUB]](s64)
; CHECK-NEXT: $x11 = COPY [[USUBE]](s64) ; CHECK-NEXT: $x11 = COPY [[SUB2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
%x00:_(s64) = COPY $x10 %x00:_(s64) = COPY $x10
%x01:_(s64) = COPY $x11 %x01:_(s64) = COPY $x11
%y00:_(s64) = COPY $x12 %y00:_(s64) = COPY $x12
%y01:_(s64) = COPY $x13 %y01:_(s64) = COPY $x13
%x0:_(s128) = G_MERGE_VALUES %x00(s64), %x01 %x0:_(s128) = G_MERGE_VALUES %x00(s64), %x01
%y0:_(s128) = G_MERGE_VALUES %y00(s64), %y01 %y0:_(s128) = G_MERGE_VALUES %y00(s64), %y01
%x:_(s72) = G_TRUNC %x0(s128) %x:_(s72) = G_TRUNC %x0(s128)
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name: sub_i128 name: sub_i128
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: sub_i128 ; CHECK-LABEL: name: sub_i128
; CHECK: %lo1:_(s64) = COPY $x10 ; CHECK: %lo1:_(s64) = COPY $x10
; CHECK-NEXT: %hi1:_(s64) = COPY $x11 ; CHECK-NEXT: %hi1:_(s64) = COPY $x11
; CHECK-NEXT: %lo2:_(s64) = COPY $x12 ; CHECK-NEXT: %lo2:_(s64) = COPY $x12
; CHECK-NEXT: %hi2:_(s64) = COPY $x13 ; CHECK-NEXT: %hi2:_(s64) = COPY $x13
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s64) = G_USUBO %lo1, %lo2 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %lo1, %lo2
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo1(s64), %lo2
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB %hi1, %hi2
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[USUBO1]], [[C]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s64) = G_USUBE %hi1, %hi2, [[AND]] ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[USUBO]](s64) ; CHECK-NEXT: $x10 = COPY [[SUB]](s64)
; CHECK-NEXT: $x11 = COPY [[USUBE]](s64) ; CHECK-NEXT: $x11 = COPY [[SUB2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
%lo1:_(s64) = COPY $x10 %lo1:_(s64) = COPY $x10
%hi1:_(s64) = COPY $x11 %hi1:_(s64) = COPY $x11
%lo2:_(s64) = COPY $x12 %lo2:_(s64) = COPY $x12
%hi2:_(s64) = COPY $x13 %hi2:_(s64) = COPY $x13
%x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64)
%x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64)
%y:_(s128) = G_SUB %x1, %x2 %y:_(s128) = G_SUB %x1, %x2
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bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: sub_i192 ; CHECK-LABEL: name: sub_i192
; CHECK: %lo1:_(s64) = COPY $x10 ; CHECK: %lo1:_(s64) = COPY $x10
; CHECK-NEXT: %mid1:_(s64) = COPY $x11 ; CHECK-NEXT: %mid1:_(s64) = COPY $x11
; CHECK-NEXT: %hi1:_(s64) = COPY $x12 ; CHECK-NEXT: %hi1:_(s64) = COPY $x12
; CHECK-NEXT: %lo2:_(s64) = COPY $x13 ; CHECK-NEXT: %lo2:_(s64) = COPY $x13
; CHECK-NEXT: %mid2:_(s64) = COPY $x14 ; CHECK-NEXT: %mid2:_(s64) = COPY $x14
; CHECK-NEXT: %hi2:_(s64) = COPY $x15 ; CHECK-NEXT: %hi2:_(s64) = COPY $x15
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s64) = G_USUBO %lo1, %lo2 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %lo1, %lo2
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo1(s64), %lo2
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB %mid1, %mid2
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[SUB1]](s64), %mid1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[USUBO1]], [[C]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s64) = G_USUBE %mid1, %mid2, [[AND]] ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[AND]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[USUBE1]], [[C1]] ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB1]](s64), [[C1]]
; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s64) = G_USUBE %hi1, %hi2, [[AND1]] ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[USUBO]](s64) ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ICMP1]], [[AND1]]
; CHECK-NEXT: $x11 = COPY [[USUBE]](s64) ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s64) = G_SUB %hi1, %hi2
; CHECK-NEXT: $x12 = COPY [[USUBE2]](s64) ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C2]]
; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB [[SUB3]], [[AND2]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s64)
; CHECK-NEXT: $x11 = COPY [[SUB2]](s64)
; CHECK-NEXT: $x12 = COPY [[SUB4]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12
%lo1:_(s64) = COPY $x10 %lo1:_(s64) = COPY $x10
%mid1:_(s64) = COPY $x11 %mid1:_(s64) = COPY $x11
%hi1:_(s64) = COPY $x12 %hi1:_(s64) = COPY $x12
%lo2:_(s64) = COPY $x13 %lo2:_(s64) = COPY $x13
%mid2:_(s64) = COPY $x14 %mid2:_(s64) = COPY $x14
%hi2:_(s64) = COPY $x15 %hi2:_(s64) = COPY $x15
%x1:_(s192) = G_MERGE_VALUES %lo1(s64), %mid1(s64), %hi1(s64) %x1:_(s192) = G_MERGE_VALUES %lo1(s64), %mid1(s64), %hi1(s64)
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