[SPIRV] Add SPIR-V logical triple to llc

[Keenuts]

Summary

This commits adds the minimal required bits to build a logical SPIR-V
compute shader using LLC.

• Skip OpenCL-only capabilities & extensions for Logical SPIR-V.
• Checks hlsl.numthreads attribute emitted by the HLSL frontend.
• Fix execution mode to GLCompute in logical.

The main issue is the lack of "vulkan" bit in the triple.
Because as-is, SPIRV32/64 assumes OpenCL, and then, SPIRV assumes
Vulkan. This is ok-ish today, but not correct.

Idea is to replace the "shadermodelX" part the triple with "vulkanX". But this needs some thinking.

Depends on D155978

[Keenuts]

git process crashed, no changes I suppose.

[Keenuts]

• [SPIRV-V] Add SPIR-V logical triple to llc
• fixup! [SPIRV-V] Add SPIR-V logical triple to llc
• fixup! [SPIRV-V] Add SPIR-V logical triple to llc
• fixup! [SPIRV-V] Add SPIR-V logical triple to llc

Removed the Logical SPIRV data layout string. We might want to
stick with SPIRV32 data layout while this is fuzzy.

Removed changes to the HLSL frontend, and adds logic to check
the HLSL attributes in the backend.
I believe this is better, as we can emit LLVM from HLSL without having
to know the target backend.
Note: we might want to unify attributes later.

[Keenuts]

I believe this should be ready for review.
No mention of Vulkan in the triple yet (we do like SPIRV32/64, assume the API from the arch).
Next step would be to extend the triple to contain Vulkan (idea is to replace shadermodelX with vulkanX, need to discuss this with @beanz )

[beanz]

In D156424#4579940, @Keenuts wrote:

Next step would be to extend the triple to contain Vulkan (idea is to replace shadermodelX with vulkanX, need to discuss this with @beanz )

vulkanX in the triple makes sense to me.

Looping in @bogner.

[bogner]

This looks like a good start. I think a fair amount of it will need to change as the HLSL support matures, but most of that should be fine to handle in tree. Probably needs an approval from somebody who's worked more in the SPIR-V backend than I have as well though.

llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp

436

Not a problem with your patch in particular, but we need to change how we represent numthreads to something more sensible. Having every user of it parsing this string is ridiculous.

llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp

249

These both look reasonable for now, though as you mention we need to discuss unifying how we represent this stuff

llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp

539

Is this is a behaviour change? Looks like we'd just carry on without any capabilities before, but isOpenCLEnv() always returned true so maybe it was just impossible.

932

Does this do something reasonable if both "reqd_work_group_size" and "hlsl.numthreads" are set? By reasonable I mean something like "error" or "accept them if they're compatible", as opposed to "choose one arbitrarily". Might become irrelevant if we're able to unify the representation.

llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp

42

Can we get this from the datalayout at this point? It'd be nice to not have to update this in two places when we revisit it.

llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp

49–53

Probably need a TODO here instead of or in addition to the one in SPIRVSubtarget.cpp's computePointerSize

[Keenuts]

• fixup! [SPIR-V] Add SPIR-V logical triple.
• fixup! [SPIR-V] Add SPIR-V logical triple.

[Keenuts]

• fixup! [SPIR-V] Add SPIR-V logical triple.

[Keenuts]

Thanks for the review. Addressed the feedback. Waiting on https://reviews.llvm.org/D155978 to be merged before rebasing.

llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp

539

Yes, it is a behavior change, but was unreachable. (isOpenCLEnv() was as you said, always true).
Now that the value can be something else, I thought a noisy failure if we reached an in-between state was probably better.

932

Good catch.
Right now, we emit both, as this is valid SPIR-V, but the order depends of the order of those conditions, which makes is I believe not useful at all, just weird.
Adding an error in such cases, as I don't see a valid use-case for this.

llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp

42

Yes, that's better. Removed this in favor of getting it from the DataLayout (via TargetMachine)

llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp

49–53

Done. Removed computePointerSize since we get it from datalayout, and moved the TODO here.

[Keenuts]

Changed the pointer size from 32 bits to 64 bits to match
the parent change.

Reason: I had to pick one. 64 bits might allow us to implement
PhysicalStorage64 memory model with more ease, but this should have
no impact for Logical SPIR-V.

[iliya-diyachkov]

llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp

216–218

Maybe rename it to isEntryPoint? Also "entrypoint" -> "entry point"?

219–221

Could we avoid braces?

225–227

Braces?

234–236

Braces?

llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp

79–81

Braces?

[Keenuts]

coding style fixes.

[Keenuts]

typo fix

[Keenuts]

Thanks, coding-style fixes applied.

[iliya-diyachkov]

Thanks, Nathan.

The patch looks good to me.

llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.cpp

 
 } // end anonymous namespace
 
 static MCInstrAnalysis *createSPIRVInstrAnalysis(const MCInstrInfo *Info) {
   return new SPIRVMCInstrAnalysis(Info);
 }
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVTargetMC() {
-  for (Target *T : {&getTheSPIRV32Target(), &getTheSPIRV64Target()}) {
+  for (Target *T : {&getTheSPIRV32Target(), &getTheSPIRV64Target(),
+                    &getTheSPIRVLogicalTarget()}) {
     RegisterMCAsmInfo<SPIRVMCAsmInfo> X(*T);
     TargetRegistry::RegisterMCInstrInfo(*T, createSPIRVMCInstrInfo);
     TargetRegistry::RegisterMCRegInfo(*T, createSPIRVMCRegisterInfo);
     TargetRegistry::RegisterMCSubtargetInfo(*T, createSPIRVMCSubtargetInfo);
     TargetRegistry::RegisterSPIRVStreamer(*T, createSPIRVMCStreamer);
     TargetRegistry::RegisterMCInstPrinter(*T, createSPIRVMCInstPrinter);
     TargetRegistry::RegisterMCInstrAnalysis(*T, createSPIRVInstrAnalysis);
     TargetRegistry::RegisterMCCodeEmitter(*T, createSPIRVMCCodeEmitter);
     TargetRegistry::RegisterMCAsmBackend(*T, createSPIRVAsmBackend);
     TargetRegistry::RegisterAsmTargetStreamer(*T, createTargetAsmStreamer);
   }
 }

llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp

public:
   void outputEntryPoints();
   void outputDebugSourceAndStrings(const Module &M);
   void outputOpExtInstImports(const Module &M);
   void outputOpMemoryModel();
   void outputOpFunctionEnd();
   void outputExtFuncDecls();
   void outputExecutionModeFromMDNode(Register Reg, MDNode *Node,
                                      SPIRV::ExecutionMode::ExecutionMode EM);
+  void outputExecutionModeFromNumthreadsAttribute(
+      const Register &Reg, const Attribute &Attr,
+      SPIRV::ExecutionMode::ExecutionMode EM);
   void outputExecutionMode(const Module &M);
   void outputAnnotations(const Module &M);
   void outputModuleSections();
 
   void emitInstruction(const MachineInstr *MI) override;
   void emitFunctionEntryLabel() override {}
   void emitFunctionHeader() override;
   void emitFunctionBodyStart() override {}
void SPIRVAsmPrinter::outputExecutionModeFromMDNode(
   MCInst Inst;
   Inst.setOpcode(SPIRV::OpExecutionMode);
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createImm(static_cast<unsigned>(EM)));
   addOpsFromMDNode(Node, Inst, MAI);
   outputMCInst(Inst);
 }
 
+void SPIRVAsmPrinter::outputExecutionModeFromNumthreadsAttribute(
+    const Register &Reg, const Attribute &Attr,
+    SPIRV::ExecutionMode::ExecutionMode EM) {
+  assert(Attr.isValid() && "Function called with an invalid attribute.");
+
+  MCInst Inst;
+  Inst.setOpcode(SPIRV::OpExecutionMode);
+  Inst.addOperand(MCOperand::createReg(Reg));
+  Inst.addOperand(MCOperand::createImm(static_cast<unsigned>(EM)));
+
+  SmallVector<StringRef> NumThreads;
+  Attr.getValueAsString().split(NumThreads, ',');
+  assert(NumThreads.size() == 3 && "invalid numthreads");
+  for (uint32_t i = 0; i < 3; ++i) {
+    uint32_t V;
+    [[maybe_unused]] bool Result = NumThreads[i].getAsInteger(10, V);
+    assert(!Result && "Failed to parse numthreads");
+    Inst.addOperand(MCOperand::createImm(V));
+  }
+
+  outputMCInst(Inst);
+}
+
 void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
   NamedMDNode *Node = M.getNamedMetadata("spirv.ExecutionMode");
   if (Node) {
     for (unsigned i = 0; i < Node->getNumOperands(); i++) {
       MCInst Inst;
       Inst.setOpcode(SPIRV::OpExecutionMode);
       addOpsFromMDNode(cast<MDNode>(Node->getOperand(i)), Inst, MAI);
       outputMCInst(Inst);
     }
   }
   for (auto FI = M.begin(), E = M.end(); FI != E; ++FI) {
     const Function &F = *FI;
     if (F.isDeclaration())
       continue;
     Register FReg = MAI->getFuncReg(&F);
     assert(FReg.isValid());
     if (MDNode *Node = F.getMetadata("reqd_work_group_size"))
       outputExecutionModeFromMDNode(FReg, Node,
                                     SPIRV::ExecutionMode::LocalSize);
+    if (Attribute Attr = F.getFnAttribute("hlsl.numthreads"); Attr.isValid())
+      outputExecutionModeFromNumthreadsAttribute(
+          FReg, Attr, SPIRV::ExecutionMode::LocalSize);
     if (MDNode *Node = F.getMetadata("work_group_size_hint"))
       outputExecutionModeFromMDNode(FReg, Node,
                                     SPIRV::ExecutionMode::LocalSizeHint);
     if (MDNode *Node = F.getMetadata("intel_reqd_sub_group_size"))
       outputExecutionModeFromMDNode(FReg, Node,
                                     SPIRV::ExecutionMode::SubgroupSize);
     if (MDNode *Node = F.getMetadata("vec_type_hint")) {
       MCInst Inst;
       Inst.setOpcode(SPIRV::OpExecutionMode);
       Inst.addOperand(MCOperand::createReg(FReg));
       unsigned EM = static_cast<unsigned>(SPIRV::ExecutionMode::VecTypeHint);
       Inst.addOperand(MCOperand::createImm(EM));
       unsigned TypeCode = encodeVecTypeHint(getMDOperandAsType(Node, 0));
       Inst.addOperand(MCOperand::createImm(TypeCode));
       outputMCInst(Inst);
     }
-    if (!M.getNamedMetadata("spirv.ExecutionMode") &&
+    if (ST->isOpenCLEnv() && !M.getNamedMetadata("spirv.ExecutionMode") &&
         !M.getNamedMetadata("opencl.enable.FP_CONTRACT")) {
       MCInst Inst;
       Inst.setOpcode(SPIRV::OpExecutionMode);
       Inst.addOperand(MCOperand::createReg(FReg));
       unsigned EM = static_cast<unsigned>(SPIRV::ExecutionMode::ContractionOff);
       Inst.addOperand(MCOperand::createImm(EM));
       outputMCInst(Inst);
     }
bool SPIRVAsmPrinter::doInitialization(Module &M) {
   // We need to call the parent's one explicitly.
   return AsmPrinter::doInitialization(M);
 }
 
 // Force static initialization.
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVAsmPrinter() {
   RegisterAsmPrinter<SPIRVAsmPrinter> X(getTheSPIRV32Target());
   RegisterAsmPrinter<SPIRVAsmPrinter> Y(getTheSPIRV64Target());
+  RegisterAsmPrinter<SPIRVAsmPrinter> Z(getTheSPIRVLogicalTarget());
 }

llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp

static Type *getArgType(const Function &F, unsigned ArgIdx) {
   std::string KernelArgTypeStr = "opencl." + MDKernelArgType->getString().str();
   Type *ExistingOpaqueType =
       StructType::getTypeByName(F.getContext(), KernelArgTypeStr);
   return ExistingOpaqueType
              ? ExistingOpaqueType
              : StructType::create(F.getContext(), KernelArgTypeStr);
 }
 
+static bool isEntrypoint(const Function &F) {
+  // OpenCL handling: any function with the SPIR_KERNEL
+  // calling convention will be a potential entrypoint.
+  if (F.getCallingConv() == CallingConv::SPIR_KERNEL) {
+    return true;
+  }
+
+  // HLSL handling: special attribute are emitted from the
+  // front-end.
+  if (F.getFnAttribute("hlsl.shader").isValid()) {
+    return true;
+  }
+
+  return false;
+}
+
+static SPIRV::ExecutionModel::ExecutionModel
+getExecutionModel(const SPIRVSubtarget &STI, const Function &F) {
+  if (STI.isOpenCLEnv()) {
+    return SPIRV::ExecutionModel::Kernel;
+  }
+
+  auto attribute = F.getFnAttribute("hlsl.shader");
+  if (!attribute.isValid()) {
+    report_fatal_error(
+        "This entrypoint lacks mandatory hlsl.shader attribute.");
+  }
+
+  const auto value = attribute.getValueAsString();
+  if (value == "compute")
+    return SPIRV::ExecutionModel::GLCompute;
+
+  report_fatal_error("This HLSL entrypoint is not supported by this backend.");
+}
+
 bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
                                              const Function &F,
                                              ArrayRef<ArrayRef<Register>> VRegs,
                                              FunctionLoweringInfo &FLI) const {
   assert(GR && "Must initialize the SPIRV type registry before lowering args.");
   GR->setCurrentFunc(MIRBuilder.getMF());
 
   // Assign types and names to all args, and store their types for later.
if (F.isDeclaration())
       GR->add(&Arg, &MIRBuilder.getMF(), VRegs[i][0]);
     i++;
   }
   // Name the function.
   if (F.hasName())
     buildOpName(FuncVReg, F.getName(), MIRBuilder);
 
   // Handle entry points and function linkage.
-  if (F.getCallingConv() == CallingConv::SPIR_KERNEL) {
+  if (isEntrypoint(F)) {
+    const auto &STI = MIRBuilder.getMF().getSubtarget<SPIRVSubtarget>();
+    auto executionModel = getExecutionModel(STI, F);
     auto MIB = MIRBuilder.buildInstr(SPIRV::OpEntryPoint)
-                   .addImm(static_cast<uint32_t>(SPIRV::ExecutionModel::Kernel))
+                   .addImm(static_cast<uint32_t>(executionModel))
                    .addUse(FuncVReg);
     addStringImm(F.getName(), MIB);
   } else if (F.getLinkage() == GlobalValue::LinkageTypes::ExternalLinkage ||
              F.getLinkage() == GlobalValue::LinkOnceODRLinkage) {
     auto LnkTy = F.isDeclaration() ? SPIRV::LinkageType::Import
                                    : SPIRV::LinkageType::Export;
     buildOpDecorate(FuncVReg, MIRBuilder, SPIRV::Decoration::LinkageAttributes,
                     {static_cast<uint32_t>(LnkTy)}, F.getGlobalIdentifier());

llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h

private:
   SmallSet<Extension::Extension, 4> AllExtensions;
   unsigned MinVersion; // 0 if no min version is defined.
   unsigned MaxVersion; // 0 if no max version is defined.
   DenseSet<unsigned> AvailableCaps;
   // Remove a list of capabilities from dedupedCaps and add them to AllCaps,
   // recursing through their implicitly declared capabilities too.
   void pruneCapabilities(const CapabilityList &ToPrune);
 
+  void initAvailableCapabilitiesForOpenCL(const SPIRVSubtarget &ST);
+  void initAvailableCapabilitiesForVulkan(const SPIRVSubtarget &ST);
+
 public:
   RequirementHandler() : MinVersion(0), MaxVersion(0) {}
   void clear() {
     MinimalCaps.clear();
     AllCaps.clear();
     AvailableCaps.clear();
     AllExtensions.clear();
     MinVersion = 0;

llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp

void SPIRVModuleAnalysis::setBaseInfo(const Module &M) {
   // TODO: determine memory model and source language from the configuratoin.
   if (auto MemModel = M.getNamedMetadata("spirv.MemoryModel")) {
     auto MemMD = MemModel->getOperand(0);
     MAI.Addr = static_cast<SPIRV::AddressingModel::AddressingModel>(
         getMetadataUInt(MemMD, 0));
     MAI.Mem =
         static_cast<SPIRV::MemoryModel::MemoryModel>(getMetadataUInt(MemMD, 1));
   } else {
-    MAI.Mem = SPIRV::MemoryModel::OpenCL;
+    // TODO: Add support for VulkanMemoryModel.
+    MAI.Mem = ST->isOpenCLEnv() ? SPIRV::MemoryModel::OpenCL
+                                : SPIRV::MemoryModel::GLSL450;
+    if (MAI.Mem == SPIRV::MemoryModel::OpenCL) {
       unsigned PtrSize = ST->getPointerSize();
       MAI.Addr = PtrSize == 32   ? SPIRV::AddressingModel::Physical32
                  : PtrSize == 64 ? SPIRV::AddressingModel::Physical64
                                  : SPIRV::AddressingModel::Logical;
+    } else {
+      // TODO: Add support for PhysicalStorageBufferAddress.
+      MAI.Addr = SPIRV::AddressingModel::Logical;
+    }
   }
   // Get the OpenCL version number from metadata.
   // TODO: support other source languages.
   if (auto VerNode = M.getNamedMetadata("opencl.ocl.version")) {
     MAI.SrcLang = SPIRV::SourceLanguage::OpenCL_C;
     // Construct version literal in accordance with SPIRV-LLVM-Translator.
     // TODO: support multiple OCL version metadata.
     assert(VerNode->getNumOperands() > 0 && "Invalid SPIR");
void SPIRVModuleAnalysis::setBaseInfo(const Module &M) {
   // source language.
   MAI.Reqs.getAndAddRequirements(SPIRV::OperandCategory::MemoryModelOperand,
                                  MAI.Mem, *ST);
   MAI.Reqs.getAndAddRequirements(SPIRV::OperandCategory::SourceLanguageOperand,
                                  MAI.SrcLang, *ST);
   MAI.Reqs.getAndAddRequirements(SPIRV::OperandCategory::AddressingModelOperand,
                                  MAI.Addr, *ST);
 
+  if (ST->isOpenCLEnv()) {
     // TODO: check if it's required by default.
-  MAI.ExtInstSetMap[static_cast<unsigned>(SPIRV::InstructionSet::OpenCL_std)] =
+    MAI.ExtInstSetMap[static_cast<unsigned>(
+        SPIRV::InstructionSet::OpenCL_std)] =
         Register::index2VirtReg(MAI.getNextID());
   }
+}
 
 // Collect MI which defines the register in the given machine function.
 static void collectDefInstr(Register Reg, const MachineFunction *MF,
                             SPIRV::ModuleAnalysisInfo *MAI,
                             SPIRV::ModuleSectionType MSType,
                             bool DoInsert = true) {
   assert(MAI->hasRegisterAlias(MF, Reg) && "Cannot find register alias");
   MachineInstr *MI = MF->getRegInfo().getUniqueVRegDef(Reg);
for (const auto Cap : ToAdd)
     if (AvailableCaps.insert(Cap).second)
       addAvailableCaps(getSymbolicOperandCapabilities(
           SPIRV::OperandCategory::CapabilityOperand, Cap));
 }
 
 namespace llvm {
 namespace SPIRV {
 void RequirementHandler::initAvailableCapabilities(const SPIRVSubtarget &ST) {
-  // TODO: Implemented for other targets other then OpenCL.
-  if (!ST.isOpenCLEnv())
+  if (ST.isOpenCLEnv()) {
+    initAvailableCapabilitiesForOpenCL(ST);
+    return;
+  }
+
+  if (ST.isVulkanEnv()) {
+    initAvailableCapabilitiesForVulkan(ST);
     return;
+  }
+
+  report_fatal_error("Unimplemented environment for SPIR-V generation.");
+}
+
+void RequirementHandler::initAvailableCapabilitiesForOpenCL(
+    const SPIRVSubtarget &ST) {
   // Add the min requirements for different OpenCL and SPIR-V versions.
   addAvailableCaps({Capability::Addresses, Capability::Float16Buffer,
                     Capability::Int16, Capability::Int8, Capability::Kernel,
                     Capability::Linkage, Capability::Vector16,
                     Capability::Groups, Capability::GenericPointer,
                     Capability::Shader});
   if (ST.hasOpenCLFullProfile())
     addAvailableCaps({Capability::Int64, Capability::Int64Atomics});
void RequirementHandler::initAvailableCapabilitiesForOpenCL(
   addAvailableCaps({Capability::Float16, Capability::Float64});
 
   // Add cap for SPV_INTEL_optnone.
   // FIXME: this should be added only if the target has the extension.
   addAvailableCaps({Capability::OptNoneINTEL});
 
   // TODO: add OpenCL extensions.
 }
+
+void RequirementHandler::initAvailableCapabilitiesForVulkan(
+    const SPIRVSubtarget &ST) {
+  addAvailableCaps({Capability::Shader, Capability::Linkage});
+}
+
 } // namespace SPIRV
 } // namespace llvm
 
 // Add the required capabilities from a decoration instruction (including
 // BuiltIns).
 static void addOpDecorateReqs(const MachineInstr &MI, unsigned DecIndex,
                               SPIRV::RequirementHandler &Reqs,
                               const SPIRVSubtarget &ST) {
for (unsigned i = 0; i < Node->getNumOperands(); i++) {
         }
       }
     }
   }
   for (auto FI = M.begin(), E = M.end(); FI != E; ++FI) {
     const Function &F = *FI;
     if (F.isDeclaration())
       continue;
-    if (F.getMetadata("reqd_work_group_size"))
+
+    if (F.getMetadata("reqd_work_group_size") &&
+        F.getFnAttribute("hlsl.numthreads").isValid()) {
+      report_fatal_error("Invalid IR: 'reqd_work_group_size' and "
+                         "'hlsl.numthreads' cannot be present together.");
+    }
+
+    if (F.getMetadata("reqd_work_group_size")) {
       MAI.Reqs.getAndAddRequirements(
           SPIRV::OperandCategory::ExecutionModeOperand,
           SPIRV::ExecutionMode::LocalSize, ST);
+    } else if (F.getFnAttribute("hlsl.numthreads").isValid()) {
+      MAI.Reqs.getAndAddRequirements(
+          SPIRV::OperandCategory::ExecutionModeOperand,
+          SPIRV::ExecutionMode::LocalSize, ST);
+    }
+
     if (F.getMetadata("work_group_size_hint"))
       MAI.Reqs.getAndAddRequirements(
           SPIRV::OperandCategory::ExecutionModeOperand,
           SPIRV::ExecutionMode::LocalSizeHint, ST);
     if (F.getMetadata("intel_reqd_sub_group_size"))
       MAI.Reqs.getAndAddRequirements(
           SPIRV::OperandCategory::ExecutionModeOperand,
           SPIRV::ExecutionMode::SubgroupSize, ST);

llvm/lib/Target/SPIRV/SPIRVSubtarget.h

 #include "SPIRVInstrInfo.h"
 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/Target/TargetMachine.h"
+#include "llvm/TargetParser/Triple.h"
 
 #define GET_SUBTARGETINFO_HEADER
 #include "SPIRVGenSubtargetInfo.inc"
 
 namespace llvm {
 class StringRef;
 class SPIRVTargetMachine;
 
 class SPIRVSubtarget : public SPIRVGenSubtargetInfo {
 private:
   const unsigned PointerSize;
   uint32_t SPIRVVersion;
   uint32_t OpenCLVersion;
 
   SmallSet<SPIRV::Extension::Extension, 4> AvailableExtensions;
   SmallSet<SPIRV::InstructionSet::InstructionSet, 4> AvailableExtInstSets;
   std::unique_ptr<SPIRVGlobalRegistry> GR;
 
   SPIRVInstrInfo InstrInfo;
   SPIRVFrameLowering FrameLowering;
   SPIRVTargetLowering TLInfo;
+  Triple TargetTriple;
 
   // GlobalISel related APIs.
   std::unique_ptr<CallLowering> CallLoweringInfo;
   std::unique_ptr<RegisterBankInfo> RegBankInfo;
   std::unique_ptr<LegalizerInfo> Legalizer;
   std::unique_ptr<InstructionSelector> InstSelector;
 
   // TODO: Initialise the available extensions, extended instruction sets
public:
   SPIRVSubtarget &initSubtargetDependencies(StringRef CPU, StringRef FS);
 
   // Parses features string setting specified subtarget options.
   // The definition of this function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
   unsigned getPointerSize() const { return PointerSize; }
   bool canDirectlyComparePointers() const;
   // TODO: this environment is not implemented in Triple, we need to decide
-  // how to standartize its support. For now, let's assume that we always
-  // operate with OpenCL.
-  bool isOpenCLEnv() const { return true; }
+  // how to standardize its support. For now, let's assume SPIR-V with physical
+  // addressing is OpenCL, and Logical addressing is Vulkan.
+  bool isOpenCLEnv() const {
+    return TargetTriple.getArch() == Triple::spirv32 ||
+           TargetTriple.getArch() == Triple::spirv64;
+  }
+  bool isVulkanEnv() const { return TargetTriple.getArch() == Triple::spirv; }
   uint32_t getSPIRVVersion() const { return SPIRVVersion; };
   bool isAtLeastSPIRVVer(uint32_t VerToCompareTo) const;
   bool isAtLeastOpenCLVer(uint32_t VerToCompareTo) const;
   // TODO: implement command line args or other ways to determine this.
   bool hasOpenCLFullProfile() const { return true; }
   bool hasOpenCLImageSupport() const { return true; }
   bool canUseExtension(SPIRV::Extension::Extension E) const;
   bool canUseExtInstSet(SPIRV::InstructionSet::InstructionSet E) const;

llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp

 #define GET_SUBTARGETINFO_CTOR
 #include "SPIRVGenSubtargetInfo.inc"
 
 // Compare version numbers, but allow 0 to mean unspecified.
 static bool isAtLeastVer(uint32_t Target, uint32_t VerToCompareTo) {
   return Target == 0 || Target >= VerToCompareTo;
 }
 
-static unsigned computePointerSize(const Triple &TT) {
-  const auto Arch = TT.getArch();
-  // TODO: unify this with pointers legalization.
-  assert(TT.isSPIRV());
-  return Arch == Triple::spirv32 ? 32 : 64;
-}
-
 SPIRVSubtarget::SPIRVSubtarget(const Triple &TT, const std::string &CPU,
                                const std::string &FS,
                                const SPIRVTargetMachine &TM)
     : SPIRVGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS),
-      PointerSize(computePointerSize(TT)), SPIRVVersion(0), OpenCLVersion(0),
-      InstrInfo(), FrameLowering(initSubtargetDependencies(CPU, FS)),
-      TLInfo(TM, *this) {
+      PointerSize(TM.getPointerSizeInBits(/* AS= */ 0)), SPIRVVersion(0),
+      OpenCLVersion(0), InstrInfo(),
+      FrameLowering(initSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
+      TargetTriple(TT) {
   // The order of initialization is important.
   initAvailableExtensions();
   initAvailableExtInstSets();
 
   GR = std::make_unique<SPIRVGlobalRegistry>(PointerSize);
   CallLoweringInfo = std::make_unique<SPIRVCallLowering>(TLInfo, GR.get());
   Legalizer = std::make_unique<SPIRVLegalizerInfo>(*this);
   RegBankInfo = std::make_unique<SPIRVRegisterBankInfo>();
bool SPIRVSubtarget::canUseExtInstSet(
   return AvailableExtInstSets.contains(E);
 }
 
 bool SPIRVSubtarget::isAtLeastSPIRVVer(uint32_t VerToCompareTo) const {
   return isAtLeastVer(SPIRVVersion, VerToCompareTo);
 }
 
 bool SPIRVSubtarget::isAtLeastOpenCLVer(uint32_t VerToCompareTo) const {
+  if (!isOpenCLEnv()) {
+    return false;
+  }
+
   return isAtLeastVer(OpenCLVersion, VerToCompareTo);
 }
 
 // If the SPIR-V version is >= 1.4 we can call OpPtrEqual and OpPtrNotEqual.
 bool SPIRVSubtarget::canDirectlyComparePointers() const {
   return isAtLeastVer(SPIRVVersion, 14);
 }
 

llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp

 #include <optional>
 
 using namespace llvm;
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVTarget() {
   // Register the target.
   RegisterTargetMachine<SPIRVTargetMachine> X(getTheSPIRV32Target());
   RegisterTargetMachine<SPIRVTargetMachine> Y(getTheSPIRV64Target());
+  RegisterTargetMachine<SPIRVTargetMachine> Z(getTheSPIRVLogicalTarget());
 
   PassRegistry &PR = *PassRegistry::getPassRegistry();
   initializeGlobalISel(PR);
   initializeSPIRVModuleAnalysisPass(PR);
 }
 
 static std::string computeDataLayout(const Triple &TT) {
   const auto Arch = TT.getArch();
-  if (Arch == Triple::spirv32)
+  // TODO: this probably needs to be revisited:
+  //  AFAIU Logical SPIR-V has no pointer size. So falling-back on ID size.
+  //  Addressing mode can change how some pointers are handled
+  //  (PhysicalStorageBuffer64).
+  if (Arch == Triple::spirv32 || Arch == Triple::spirv)
     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
            "v96:128-v192:256-v256:256-v512:512-v1024:1024";
   return "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
          "v96:128-v192:256-v256:256-v512:512-v1024:1024";
 }
 
 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
   if (!RM)

llvm/lib/Target/SPIRV/TargetInfo/SPIRVTargetInfo.h

 #define LLVM_LIB_TARGET_SPIRV_TARGETINFO_SPIRVTARGETINFO_H
 
 namespace llvm {
 
 class Target;
 
 Target &getTheSPIRV32Target();
 Target &getTheSPIRV64Target();
+Target &getTheSPIRVLogicalTarget();
 
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_SPIRV_TARGETINFO_SPIRVTARGETINFO_H

llvm/lib/Target/SPIRV/TargetInfo/SPIRVTargetInfo.cpp

 Target &llvm::getTheSPIRV32Target() {
   static Target TheSPIRV32Target;
   return TheSPIRV32Target;
 }
 Target &llvm::getTheSPIRV64Target() {
   static Target TheSPIRV64Target;
   return TheSPIRV64Target;
 }
+Target &llvm::getTheSPIRVLogicalTarget() {
+  static Target TheSPIRVLogicalTarget;
+  return TheSPIRVLogicalTarget;
+}
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVTargetInfo() {
   RegisterTarget<Triple::spirv32> X(getTheSPIRV32Target(), "spirv32",
                                     "SPIR-V 32-bit", "SPIRV");
   RegisterTarget<Triple::spirv64> Y(getTheSPIRV64Target(), "spirv64",
                                     "SPIR-V 64-bit", "SPIRV");
+  RegisterTarget<Triple::spirv> Z(getTheSPIRVLogicalTarget(), "spirv",
+                                  "SPIR-V Logical", "SPIRV");
 }

llvm/test/CodeGen/SPIRV/ExecutionMode-ConflictingAttributes.ll

+; RUN: not --crash llc -O0 -mtriple=spirv-unknown-unknown %s -o - 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Invalid IR: 'reqd_work_group_size' and 'hlsl.numthreads' cannot be present together.
+
+define void @main() #1 !reqd_work_group_size !3 {
+entry:
+  ret void
+}
+
+attributes #1 = { "hlsl.numthreads"="4,8,16" "hlsl.shader"="compute" }
+!3 = !{i32 4, i32 8, i32 12}

llvm/test/CodeGen/SPIRV/ExecutionMode-GLCompute.ll

+; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+
+; CHECK-DAG: OpEntryPoint GLCompute %[[#entry:]] "main"
+; CHECK-DAG: OpExecutionMode %[[#entry]] LocalSize 4 8 16
+
+define void @main() #1 {
+entry:
+  ret void
+}
+
+attributes #1 = { "hlsl.numthreads"="4,8,16" "hlsl.shader"="compute" }

llvm/test/CodeGen/SPIRV/capability-Shader.ll

+; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+
+; CHECK-DAG: OpCapability Shader
+;; Ensure no other capability is listed.
+; CHECK-NOT: OpCapability
+
+define void @main() #1 {
+entry:
+  ret void
+}
+
+attributes #1 = { "hlsl.numthreads"="4,8,16" "hlsl.shader"="compute" }

llvm/test/CodeGen/SPIRV/empty-logical.ll

+; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+
+;; Ensure the required Capabilities are listed.
+; CHECK-DAG: OpCapability Shader
+; CHECK-DAG: OpCapability Linkage
+
+;; Ensure one, and only one, OpMemoryModel is defined.
+; CHECK:     OpMemoryModel Logical GLSL450
+; CHECK-NOT: OpMemoryModel