RegisterCoalescer: Avoid redundant implicit-def on rematerialize

[arsenm]

Summary

If this was coalescing a def of a subregister with a def of the super
register, it was introducing a redundant super-register def and
marking the subregister def as dead.

Resulting in something like:

dead $eax = MOVr0, implicit-def $rax, implicit-def $rax

Avoid this by checking if the new instruction already has the super
def, so we end up with this instead:

dead $eax = MOVr0, implicit-def $rax

The dead flag looks suspicious to me, seems like it's easy to buggily
interpret dead def of subreg and a non-dead def of an aliasing
register. It seems to be intentional though.

[arsenm]

e28708d4f03889214066fba81072f974864b919f

llvm/lib/CodeGen/RegisterCoalescer.cpp

bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
   // We need to remember these so we can add intervals once we insert
   // NewMI into SlotIndexes.
   //
   // We also expect to have tied implicit-defs of super registers originating
   // from SUBREG_TO_REG, such as:
   // $edi = MOV32r0 implicit-def dead $eflags, implicit-def $rdi
   // undef %0.sub_32bit = MOV32r0 implicit-def dead $eflags, implicit-def %0
 
+  bool NewMIDefinesFullReg = false;
+
   SmallVector<MCRegister, 4> NewMIImplDefs;
   for (unsigned i = NewMI.getDesc().getNumOperands(),
                 e = NewMI.getNumOperands();
        i != e; ++i) {
     MachineOperand &MO = NewMI.getOperand(i);
     if (MO.isReg() && MO.isDef()) {
       assert(MO.isImplicit());
       if (MO.getReg().isPhysical()) {
+        if (MO.getReg() == DstReg)
+          NewMIDefinesFullReg = true;
+
         assert(MO.isImplicit() && MO.getReg().isPhysical() &&
                (MO.isDead() ||
                 (DefSubIdx && (TRI->getSubReg(MO.getReg(), DefSubIdx) ==
                                MCRegister(NewMI.getOperand(0).getReg())))));
         NewMIImplDefs.push_back(MO.getReg().asMCReg());
       } else {
         assert(MO.getReg() == NewMI.getOperand(0).getReg() &&
                MO.getSubReg() == 0);
if (NewIdx != 0 && DstInt.hasSubRanges()) {
         DstInt.removeEmptySubRanges();
     }
   } else if (NewMI.getOperand(0).getReg() != CopyDstReg) {
     // The New instruction may be defining a sub-register of what's actually
     // been asked for. If so it must implicitly define the whole thing.
     assert(DstReg.isPhysical() &&
            "Only expect virtual or physical registers in remat");
     NewMI.getOperand(0).setIsDead(true);
+
+    if (!NewMIDefinesFullReg) {
       NewMI.addOperand(MachineOperand::CreateReg(
           CopyDstReg, true /*IsDef*/, true /*IsImp*/, false /*IsKill*/));
+    }
+
     // Record small dead def live-ranges for all the subregisters
     // of the destination register.
     // Otherwise, variables that live through may miss some
     // interferences, thus creating invalid allocation.
     // E.g., i386 code:
     // %1 = somedef ; %1 GR8
     // %2 = remat ; %2 GR32
     // CL = COPY %2.sub_8bit

llvm/test/CodeGen/X86/rematerialize-sub-super-reg.mir

body:             |
   bb.3:
     $rax = COPY %t3
     RET 0, $rax
 
 ...
 
 # Handle that rematerializing an instruction with an implicit def of a
 # virtual super register into a physical register works.
-#
-# FIXME: Resulting rematerializing has a redundant implicit-def
 ---
 name:            rematerialize_subregister_into_superreg_def_with_impdef_physreg
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: rematerialize_subregister_into_superreg_def_with_impdef_physreg
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   undef %t3.sub_32bit:gr64_with_sub_8bit = MOV32ri -11, implicit-def %t3
   ; CHECK-NEXT:   CMP64ri8 %t3, 1, implicit-def $eflags
   ; CHECK-NEXT:   JCC_1 %bb.2, 4, implicit killed $eflags
   ; CHECK-NEXT:   JMP_1 %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.1(0x80000000)
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   dead $eax = MOV32ri -11, implicit-def $rax, implicit-def $rax
+  ; CHECK-NEXT:   dead $eax = MOV32ri -11, implicit-def $rax
   ; CHECK-NEXT:   CMP64ri8 %t3, 1, implicit-def $eflags
   ; CHECK-NEXT:   JCC_1 %bb.1, 4, implicit killed $eflags
   ; CHECK-NEXT:   RET 0, $rax
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %t3:gr64_with_sub_8bit = ADD64ri8 %t3, 10, implicit-def $eflags