[PowerPC][MC] Recognize tlbilx and its mnemonics

[qiucf]

Summary

This patch makes MC recognize tlbilx instruction and its mnemonics, and fixes issue 64080:

void foo(void) { asm volatile("tlbilxlpid"); }

tlbilx exists in ISA 2.07 Book III-E. Since contents of Book III-E were eliminated after ISA 3.0, tlbilx does not exist in ISA 3.0 and ISA 3.1.

[nemanjai]

What version of the PowerISA is this from? What is the motivation for implementing this?

[qiucf]

The motivation is https://github.com/llvm/llvm-project/issues/64080

I see both GCC and XLC 16 recognize the instruction in inlineasm.

The instruction (tlbilx) can be found in ISA 2.07 but eliminated in 3.0 and 3.1 since it belongs to 'Book III-E'. Not sure if it should be implemented in current PPC backend. So I put this in draft mode.

In support of the OpenPOWER Foundation’s standardization of server architecture, Power ISA Version 3.0 streamlined this integration by choosing a single Book III and a set of widely used categories to become part of the base architecture for all forward-looking Power implementations. All other optional architecture categories were eliminated to ensure increased application portability between Power processors. Legacy embedded applications that require the eliminated material will continue to use V. 2.07B.

-Preface of ISA 3.0

[nemanjai]

In D156204#4530957, @qiucf wrote:

The motivation is https://github.com/llvm/llvm-project/issues/64080

I see both GCC and XLC 16 recognize the instruction in inlineasm.

The instruction (tlbilx) can be found in ISA 2.07 but eliminated in 3.0 and 3.1 since it belongs to 'Book III-E'. Not sure if it should be implemented in current PPC backend. So I put this in draft mode.

In support of the OpenPOWER Foundation’s standardization of server architecture, Power ISA Version 3.0 streamlined this integration by choosing a single Book III and a set of widely used categories to become part of the base architecture for all forward-looking Power implementations. All other optional architecture categories were eliminated to ensure increased application portability between Power processors. Legacy embedded applications that require the eliminated material will continue to use V. 2.07B.

-Preface of ISA 3.0

OK, thanks for clarifying. I am not against implementing this instruction and its aliases, but I think that anything from these removed optional categories should only be implemented with good justification. Needing it in the kernel builds is adequate justification in my opinion. Please update the description to mention the bug this is resolving.

[nickdesaulniers]

Thanks for the patch!

llvm/lib/Target/PowerPC/PPCInstrFormats.td

class XForm_base_r3xo_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                             list<dag> pattern>
   : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp;
 
 class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr,
                 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> {
   let RST = 0;
 }
 
+class XForm_tlbilx<bits<10> xo, dag OOL, dag IOL, string asmstr,
+      InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> {
+  bits<5> T;
+  let RST = T;
+}
+
 class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
                  InstrItinClass itin>
   : I<opcode, OOL, IOL, asmstr, itin> {
   let Inst{21-30} = xo;
 }
 
 // This is the same as XForm_base_r3xo, but the first two operands are swapped
 // when code is emitted.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RST, gprc:$RB),
                           "tlbie $RB,$RST", IIC_SprTLBIE, []>;
 
 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$RA, gprc:$RB), "tlbsx $RA, $RB",
                 IIC_LdStLoad>, Requires<[IsBookE]>;
 
 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$RA, gprc:$RB), "tlbivax $RA, $RB",
                 IIC_LdStLoad>, Requires<[IsBookE]>;
 
+def TLBILX : XForm_tlbilx<18, (outs), (ins u2imm:$T, gprc:$RA, gprc:$RB),
+    "tlbilx $T, $RA, $RB", IIC_LdStLoad>, Requires<[IsBookE]>;
+
 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
                            "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
 
 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
                            "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
 
 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RST), (ins gprc:$RA, i1imm:$WS),
                "tlbre $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
                 Requires<[IsPPC4xx]>;
 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
                 Requires<[IsPPC4xx]>;
 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
                 Requires<[IsPPC4xx]>;
 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
                 Requires<[IsPPC4xx]>;
 
+def : InstAlias<"tlbilxlpid", (TLBILX 0, R0, R0)>, Requires<[IsBookE]>;
+def : InstAlias<"tlbilxpid", (TLBILX 1, R0, R0)>, Requires<[IsBookE]>;
+def : InstAlias<"tlbilxva $RA, $RB", (TLBILX 3, gprc:$RA, gprc:$RB)>,
+                Requires<[IsBookE]>;
+def : InstAlias<"tlbilxva $RB", (TLBILX 3, R0, gprc:$RB)>, Requires<[IsBookE]>;
+
 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
 
 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
                          (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
                          (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;

llvm/lib/Target/PowerPC/PPCScheduleP9.td

def P9Model : SchedMachineModel {
   let MicroOpBufferSize = 44;
 
   let CompleteModel = 1;
 
   // Do not support SPE (Signal Processing Engine) or prefixed instructions on
   // Power 9, or MMA, or paired vector mem ops,  or PC relative mem ops, or
   // instructions introduced after ISA 3.0.
   let UnsupportedFeatures = [HasSPE, PrefixInstrs, MMA,
-                             PairedVectorMemops,
+                             PairedVectorMemops, IsBookE,
                              PCRelativeMemops, IsISA3_1, IsISAFuture];
 }
 
 let SchedModel = P9Model in {
 
   // ***************** Processor Resources *****************
 
   // Dispatcher slots:

llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s

 # CHECK-BE: tlbie 4                         # encoding: [0x7c,0x00,0x22,0x64]
 # CHECK-LE: tlbie 4                         # encoding: [0x64,0x22,0x00,0x7c]
             tlbie %r4, 0
 
 # CHECK-BE: tlbie 4                         # encoding: [0x7c,0x00,0x22,0x64]
 # CHECK-LE: tlbie 4                         # encoding: [0x64,0x22,0x00,0x7c]
             tlbie %r4
 
+# CHECK-BE: tlbilx 1, 4, 5                  # encoding: [0x7c,0x24,0x28,0x24]
+# CHECK-LE: tlbilx 1, 4, 5                  # encoding: [0x24,0x28,0x24,0x7c]
+            tlbilx 1, %r4, %r5
+
+# CHECK-BE: tlbilxlpid                      # encoding: [0x7c,0x00,0x00,0x24]
+# CHECK-LE: tlbilxlpid                      # encoding: [0x24,0x00,0x00,0x7c]
+            tlbilxlpid
+
+# CHECK-BE: tlbilxpid                       # encoding: [0x7c,0x20,0x00,0x24]
+# CHECK-LE: tlbilxpid                       # encoding: [0x24,0x00,0x20,0x7c]
+            tlbilxpid
+
+# CHECK-BE: tlbilxva 4, 5                   # encoding: [0x7c,0x64,0x28,0x24]
+# CHECK-LE: tlbilxva 4, 5                   # encoding: [0x24,0x28,0x64,0x7c]
+            tlbilxva %r4, %r5
+
+# CHECK-BE: tlbilxva 0, 5                   # encoding: [0x7c,0x60,0x28,0x24]
+# CHECK-LE: tlbilxva 0, 5                   # encoding: [0x24,0x28,0x60,0x7c]
+            tlbilxva %r5
+
 # CHECK-BE: rfi                             # encoding: [0x4c,0x00,0x00,0x64]
 # CHECK-LE: rfi                             # encoding: [0x64,0x00,0x00,0x4c]
             rfi
 # CHECK-BE: rfci                            # encoding: [0x4c,0x00,0x00,0x66]
 # CHECK-LE: rfci                            # encoding: [0x66,0x00,0x00,0x4c]
             rfci
 
 # CHECK-BE: wrtee 12                        # encoding: [0x7d,0x80,0x01,0x06]