[RISCV] Remove Opcode field from RVInst. Assign Inst{6-0} directly. NFC

[craig.topper]

Summary

Most places assign Opcode right after assigning every other bit in
Inst. I don't think treating Opcode separately adds much value. It
doesn't hide what bits belong to the opcode since every other bits is
listed.

This makes RVInst consistent with RVInst16 subclasss which already
assign Inst{1-0} directly.

[wangpc]

LGTM.
I think it makes the instruction encoding much easier to understand directly.

[asb]

Totally agree with your reasoning, I think this a good improvement. Thanks.

llvm/lib/Target/RISCV/RISCVInstrFormats.td

class RVInst<dag outs, dag ins, string opcodestr, string argstr,
     : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
   field bits<32> Inst;
   // SoftFail is a field the disassembler can use to provide a way for
   // instructions to not match without killing the whole decode process. It is
   // mainly used for ARM, but Tablegen expects this field to exist or it fails
   // to build the decode table.
   field bits<32> SoftFail = 0;
   let Size = 4;
-
-  bits<7> Opcode = 0;
-
-  let Inst{6-0} = Opcode;
 }
 
 // Pseudo instructions
 class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">
     : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
   bits<5> rs1;
   bits<5> rd;
 
   let Inst{31-25} = funct7;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = opcode.Value;
+  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstR4<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode, dag outs,
                dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> {
   bits<5> rs3;
   bits<5> rs2;
   bits<5> rs1;
   bits<5> rd;
 
   let Inst{31-27} = rs3;
   let Inst{26-25} = funct2;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = opcode.Value;
+  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstR4Frm<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
                   string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> {
   bits<5> rs3;
   bits<5> rs2;
   bits<5> rs1;
   bits<3> frm;
   bits<5> rd;
 
   let Inst{31-27} = rs3;
   let Inst{26-25} = funct2;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = frm;
   let Inst{11-7} = rd;
-  let Opcode = opcode.Value;
+  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
                     RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
                     string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<5> rd;
 
   let Inst{31-27} = funct5;
   let Inst{26} = aq;
   let Inst{25} = rl;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = opcode.Value;
+  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
                  string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<3> frm;
   bits<5> rd;
 
   let Inst{31-25} = funct7;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = frm;
   let Inst{11-7} = rd;
-  let Opcode = opcode.Value;
+  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
               string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
   bits<12> imm12;
   bits<5> rs1;
   bits<5> rd;
 
   let Inst{31-20} = imm12;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = opcode.Value;
+  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
                    dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
   bits<6> shamt;
   bits<5> rs1;
   bits<5> rd;
 
   let Inst{31-27} = imm11_7;
   let Inst{26} = 0;
   let Inst{25-20} = shamt;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = opcode.Value;
+  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstIShiftW<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
                     dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
   bits<5> shamt;
   bits<5> rs1;
   bits<5> rd;
 
   let Inst{31-25} = imm11_5;
   let Inst{24-20} = shamt;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = opcode.Value;
+  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
               string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatS> {
   bits<12> imm12;
   bits<5> rs2;
   bits<5> rs1;
 
   let Inst{31-25} = imm12{11-5};
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = imm12{4-0};
-  let Opcode = opcode.Value;
+  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
               string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatB> {
   bits<12> imm12;
   bits<5> rs2;
   bits<5> rs1;
 
   let Inst{31} = imm12{11};
   let Inst{30-25} = imm12{9-4};
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-8} = imm12{3-0};
   let Inst{7} = imm12{10};
-  let Opcode = opcode.Value;
+  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
               string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatU> {
   bits<20> imm20;
   bits<5> rd;
 
   let Inst{31-12} = imm20;
   let Inst{11-7} = rd;
-  let Opcode = opcode.Value;
+  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
               string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatJ> {
   bits<20> imm20;
   bits<5> rd;
 
   let Inst{31} = imm20{19};
   let Inst{30-21} = imm20{9-0};
   let Inst{20} = imm20{10};
   let Inst{19-12} = imm20{18-11};
   let Inst{11-7} = rd;
-  let Opcode = opcode.Value;
+  let Inst{6-0} = opcode.Value;
 }
 
 //===----------------------------------------------------------------------===//
 // Instruction classes for .insn directives
 //===----------------------------------------------------------------------===//
 
 class DirectiveInsnR<dag outs, dag ins, string argstr>
   : RVInst<outs, ins, "", "", [], InstFormatR> {
   bits<7> opcode;
   bits<7> funct7;
   bits<3> funct3;
 
   bits<5> rs2;
   bits<5> rs1;
   bits<5> rd;
 
   let Inst{31-25} = funct7;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = opcode;
+  let Inst{6-0} = opcode;
 
   let AsmString = ".insn r " # argstr;
 }
 
 class DirectiveInsnR4<dag outs, dag ins, string argstr>
   : RVInst<outs, ins, "", "", [], InstFormatR4> {
   bits<7> opcode;
   bits<2> funct2;
   bits<3> funct3;
 
   bits<5> rs3;
   bits<5> rs2;
   bits<5> rs1;
   bits<5> rd;
 
   let Inst{31-27} = rs3;
   let Inst{26-25} = funct2;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = opcode;
+  let Inst{6-0} = opcode;
 
   let AsmString = ".insn r4 " # argstr;
 }
 
 class DirectiveInsnI<dag outs, dag ins, string argstr>
   : RVInst<outs, ins, "", "", [], InstFormatI> {
   bits<7> opcode;
   bits<3> funct3;
 
   bits<12> imm12;
   bits<5> rs1;
   bits<5> rd;
 
   let Inst{31-20} = imm12;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = opcode;
+  let Inst{6-0} = opcode;
 
   let AsmString = ".insn i " # argstr;
 }
 
 class DirectiveInsnS<dag outs, dag ins, string argstr>
   : RVInst<outs, ins, "", "", [], InstFormatS> {
   bits<7> opcode;
   bits<3> funct3;
 
   bits<12> imm12;
   bits<5> rs2;
   bits<5> rs1;
 
   let Inst{31-25} = imm12{11-5};
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = imm12{4-0};
-  let Opcode = opcode;
+  let Inst{6-0} = opcode;
 
   let AsmString = ".insn s " # argstr;
 }
 
 class DirectiveInsnB<dag outs, dag ins, string argstr>
   : RVInst<outs, ins, "", "", [], InstFormatB> {
   bits<7> opcode;
   bits<3> funct3;
 
   bits<12> imm12;
   bits<5> rs2;
   bits<5> rs1;
 
   let Inst{31} = imm12{11};
   let Inst{30-25} = imm12{9-4};
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-8} = imm12{3-0};
   let Inst{7} = imm12{10};
-  let Opcode = opcode;
+  let Inst{6-0} = opcode;
 
   let AsmString = ".insn b " # argstr;
 }
 
 class DirectiveInsnU<dag outs, dag ins, string argstr>
   : RVInst<outs, ins, "", "", [], InstFormatU> {
   bits<7> opcode;
 
   bits<20> imm20;
   bits<5> rd;
 
   let Inst{31-12} = imm20;
   let Inst{11-7} = rd;
-  let Opcode = opcode;
+  let Inst{6-0} = opcode;
 
   let AsmString = ".insn u " # argstr;
 }
 
 class DirectiveInsnJ<dag outs, dag ins, string argstr>
   : RVInst<outs, ins, "", "", [], InstFormatJ> {
   bits<7> opcode;
 
   bits<20> imm20;
   bits<5> rd;
 
   let Inst{31-12} = imm20;
   let Inst{11-7} = rd;
-  let Opcode = opcode;
+  let Inst{6-0} = opcode;
 
   let AsmString = ".insn j " # argstr;
 }

llvm/lib/Target/RISCV/RISCVInstrFormatsV.td

class RVInstSetiVLi<dag outs, dag ins, string opcodestr, string argstr>
   bits<10> vtypei;
 
   let Inst{31} = 1;
   let Inst{30} = 1;
   let Inst{29-20} = vtypei{9-0};
   let Inst{19-15} = uimm;
   let Inst{14-12} = OPCFG.Value;
   let Inst{11-7} = rd;
-  let Opcode = OPC_OP_V.Value;
+  let Inst{6-0} = OPC_OP_V.Value;
 
   let Defs = [VTYPE, VL];
 }
 
 class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
   bits<5> rs1;
   bits<5> rd;
   bits<11> vtypei;
 
   let Inst{31} = 0;
   let Inst{30-20} = vtypei;
   let Inst{19-15} = rs1;
   let Inst{14-12} = OPCFG.Value;
   let Inst{11-7} = rd;
-  let Opcode = OPC_OP_V.Value;
+  let Inst{6-0} = OPC_OP_V.Value;
 
   let Defs = [VTYPE, VL];
 }
 
 class RVInstSetVL<dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<5> rd;
 
   let Inst{31} = 1;
   let Inst{30-25} = 0b000000;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = OPCFG.Value;
   let Inst{11-7} = rd;
-  let Opcode = OPC_OP_V.Value;
+  let Inst{6-0} = OPC_OP_V.Value;
 
   let Defs = [VTYPE, VL];
 }
 
 class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
                string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> vs1;
   bits<5> vd;
   bit vm;
 
   let Inst{31-26} = funct6;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = vs1;
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
-  let Opcode = OPC_OP_V.Value;
+  let Inst{6-0} = OPC_OP_V.Value;
 
   let Uses = [VTYPE, VL];
   let RVVConstraint = VMConstraint;
 }
 
 class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
                 string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> rs1;
   bits<5> vd;
   bit vm;
 
   let Inst{31-26} = funct6;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
-  let Opcode = OPC_OP_V.Value;
+  let Inst{6-0} = OPC_OP_V.Value;
 
   let Uses = [VTYPE, VL];
   let RVVConstraint = VMConstraint;
 }
 
 class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
                 string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs1;
   bits<5> vd;
   bit vm;
 
   let Inst{31-26} = funct6;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
-  let Opcode = OPC_OP_V.Value;
+  let Inst{6-0} = OPC_OP_V.Value;
 
   let Uses = [VTYPE, VL];
   let RVVConstraint = VMConstraint;
 }
 
 class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
                 string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> imm;
   bits<5> vd;
   bit vm;
 
   let Inst{31-26} = funct6;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = imm;
   let Inst{14-12} = OPIVI.Value;
   let Inst{11-7} = vd;
-  let Opcode = OPC_OP_V.Value;
+  let Inst{6-0} = OPC_OP_V.Value;
 
   let Uses = [VTYPE, VL];
   let RVVConstraint = VMConstraint;
 }
 
 class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
               dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> vd;
   bit vm;
 
   let Inst{31-26} = funct6;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = vs1;
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
-  let Opcode = OPC_OP_V.Value;
+  let Inst{6-0} = OPC_OP_V.Value;
 
   let Uses = [VTYPE, VL];
   let RVVConstraint = VMConstraint;
 }
 
 class RVInstVLU<bits<3> nf, bit mew, RISCVLSUMOP lumop,
                 bits<3> width, dag outs, dag ins, string opcodestr,
                 string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs1;
   bits<5> vd;
   bit vm;
 
   let Inst{31-29} = nf;
   let Inst{28} = mew;
   let Inst{27-26} = MOPLDUnitStride.Value;
   let Inst{25} = vm;
   let Inst{24-20} = lumop.Value;
   let Inst{19-15} = rs1;
   let Inst{14-12} = width;
   let Inst{11-7} = vd;
-  let Opcode = OPC_LOAD_FP.Value;
+  let Inst{6-0} = OPC_LOAD_FP.Value;
 
   let Uses = [VTYPE, VL];
   let RVVConstraint = VMConstraint;
 }
 
 class RVInstVLS<bits<3> nf, bit mew, bits<3> width,
                 dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<5> vd;
   bit vm;
 
   let Inst{31-29} = nf;
   let Inst{28} = mew;
   let Inst{27-26} = MOPLDStrided.Value;
   let Inst{25} = vm;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = width;
   let Inst{11-7} = vd;
-  let Opcode = OPC_LOAD_FP.Value;
+  let Inst{6-0} = OPC_LOAD_FP.Value;
 
   let Uses = [VTYPE, VL];
   let RVVConstraint = VMConstraint;
 }
 
 class RVInstVLX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
                 dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> rs1;
   bits<5> vd;
   bit vm;
 
   let Inst{31-29} = nf;
   let Inst{28} = mew;
   let Inst{27-26} = mop.Value;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = width;
   let Inst{11-7} = vd;
-  let Opcode = OPC_LOAD_FP.Value;
+  let Inst{6-0} = OPC_LOAD_FP.Value;
 
   let Uses = [VTYPE, VL];
   let RVVConstraint = VMConstraint;
 }
 
 class RVInstVSU<bits<3> nf, bit mew, RISCVLSUMOP sumop,
                 bits<3> width, dag outs, dag ins, string opcodestr,
                 string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs1;
   bits<5> vs3;
   bit vm;
 
   let Inst{31-29} = nf;
   let Inst{28} = mew;
   let Inst{27-26} = MOPSTUnitStride.Value;
   let Inst{25} = vm;
   let Inst{24-20} = sumop.Value;
   let Inst{19-15} = rs1;
   let Inst{14-12} = width;
   let Inst{11-7} = vs3;
-  let Opcode = OPC_STORE_FP.Value;
+  let Inst{6-0} = OPC_STORE_FP.Value;
 
   let Uses = [VTYPE, VL];
 }
 
 class RVInstVSS<bits<3> nf, bit mew, bits<3> width,
                 dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<5> vs3;
   bit vm;
 
   let Inst{31-29} = nf;
   let Inst{28} = mew;
   let Inst{27-26} = MOPSTStrided.Value;
   let Inst{25} = vm;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = width;
   let Inst{11-7} = vs3;
-  let Opcode = OPC_STORE_FP.Value;
+  let Inst{6-0} = OPC_STORE_FP.Value;
 
   let Uses = [VTYPE, VL];
 }
 
 class RVInstVSX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
                 dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> rs1;
   bits<5> vs3;
   bit vm;
 
   let Inst{31-29} = nf;
   let Inst{28} = mew;
   let Inst{27-26} = mop.Value;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = width;
   let Inst{11-7} = vs3;
-  let Opcode = OPC_STORE_FP.Value;
+  let Inst{6-0} = OPC_STORE_FP.Value;
 
   let Uses = [VTYPE, VL];
 }

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

class CVInstMac<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
   bits<5> rs1;
   bits<5> rd;
 
   let Inst{31-25} = funct7;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = OPC_CUSTOM_1.Value;
+  let Inst{6-0} = OPC_CUSTOM_1.Value;
   let DecoderNamespace = "XCVmac";
 }
 
 class CVInstMac16I<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
                    string opcodestr, string argstr, list<dag> pattern>
     : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatOther> {
   bits<5> imm5;
   bits<5> rs2;
   bits<5> rs1;
   bits<5> rd;
 
   let Inst{31-30} = funct2;
   let Inst{29-25} = imm5;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = OPC_CUSTOM_2.Value;
+  let Inst{6-0} = OPC_CUSTOM_2.Value;
   let DecoderNamespace = "XCVmac";
 }
 
 let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0,
     mayStore = 0, Constraints = "$rd = $rd_wb" in {
   // 32x32 bit macs
   def CV_MAC      : CVInstMac<0b1001000, 0b011, (outs GPR:$rd_wb),
                               (ins GPR:$rd, GPR:$rs1, GPR:$rs2),

llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

class RVInstVCCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,
 
   let Inst{31-28} = funct6_hi4;
   let Inst{27-26} = funct6_lo2;
   let Inst{25} = vm;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = OPC_CUSTOM_2.Value;
+  let Inst{6-0} = OPC_CUSTOM_2.Value;
 
   let Uses = [VTYPE, VL];
   let RVVConstraint = NoConstraint;
 }
 
 class RVInstVCFCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,
                        string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<5> rd;
   bit funct6_lo1;
   bit vm;
 
   let Inst{31-28} = funct6_hi4;
   let Inst{27} = 1;
   let Inst{26} = funct6_lo1;
   let Inst{25} = vm;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = OPC_CUSTOM_2.Value;
+  let Inst{6-0} = OPC_CUSTOM_2.Value;
 
   let Uses = [VTYPE, VL];
   let RVVConstraint = NoConstraint;
 }
 
 class GetFTypeInfo<int sew> {
   ValueType Scalar = !cond(!eq(sew, 16): f16,
                            !eq(sew, 32): f32,

llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

 
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
 class THInstVdotVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
                    string opcodestr, string argstr>
     : RVInstVV<funct6, opv, outs, ins, opcodestr, argstr> {
   let Inst{26} = 0;
-  let Opcode = OPC_CUSTOM_0.Value;
+  let Inst{6-0} = OPC_CUSTOM_0.Value;
   let DecoderNamespace = "THeadV";
 }
 
 class THInstVdotVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
                    string opcodestr, string argstr>
     : RVInstVX<funct6, opv, outs, ins, opcodestr, argstr> {
   let Inst{26} = 1;
-  let Opcode = OPC_CUSTOM_0.Value;
+  let Inst{6-0} = OPC_CUSTOM_0.Value;
   let DecoderNamespace = "THeadV";
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 // op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
 class THVdotALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
     : THInstVdotVV<funct6, opv, (outs VR:$vd),
                    (ins VR:$vs1, VR:$vs2, VMaskOp:$vm),

llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

class FPUnaryOp_imm<bits<7> funct7, bits<5> rs2val, bits<3> funct3, RISCVOpcode opcode,
   bits<5> imm;
   bits<5> rd;
 
   let Inst{31-25} = funct7;
   let Inst{24-20} = rs2val;
   let Inst{19-15} = imm;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = opcode.Value;
+  let Inst{6-0} = opcode.Value;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,
     UseNamedOperandTable = 1, hasPostISelHook = 1 in
 class FPUnaryOp_r_rtz<bits<7> funct7, bits<5> rs2val, DAGOperand rdty,
                       DAGOperand rs1ty, string opcodestr>
     : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd),
                  (ins rs1ty:$rs1, rtzarg:$frm), opcodestr,

llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

class RVInstIVI_VROR<bits<6> funct6, dag outs, dag ins, string opcodestr,
 
   let Inst{31-27} = funct6{5-1};
   let Inst{26} = imm{5};
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = imm{4-0};
   let Inst{14-12} = OPIVI.Value;
   let Inst{11-7} = vd;
-  let Opcode = OPC_OP_V.Value;
+  let Inst{6-0} = OPC_OP_V.Value;
 
   let Uses = [VTYPE, VL];
   let RVVConstraint = VMConstraint;
 }
 
 multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6>
     : VALU_IV_V_X<opcodestr, funct6> {
   def I : RVInstIVI_VROR<funct6, (outs VR:$vd),
               (ins VR:$vs2, uimm6:$imm, VMaskOp:$vm),
               opcodestr # ".vi", "$vd, $vs2, $imm$vm">,
          Sched<[WriteVIALUI_WorstCase, ReadVIALUV_WorstCase,
                 ReadVMask]>;
 }
 
 // op vd, vs2, vs1
 class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
     : VALUVVNoVm<funct6, opv, opcodestr> {
-  let Opcode = OPC_OP_P.Value;
+  let Inst{6-0} = OPC_OP_P.Value;
 }
 
 // op vd, vs2, imm, vm
 class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5>
     : VALUVINoVm<funct6, opcodestr, optype> {
-  let Opcode = OPC_OP_P.Value;
+  let Inst{6-0} = OPC_OP_P.Value;
   let Inst{14-12} = OPMVV.Value;
 }
 
 // op vd, vs2 (use vs1 as instruction encoding)
 class PALUVs2NoVm<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
     : VALUVs2NoVm<funct6, vs1, opv, opcodestr> {
-  let Opcode = OPC_OP_P.Value;
+  let Inst{6-0} = OPC_OP_P.Value;
 }
 
 multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
                          RISCVVFormat opv, string opcodestr> {
   def NAME # _VV : PALUVs2NoVm<funct6_vv, vs1, opv, opcodestr # ".vv">;
   def NAME # _VS : PALUVs2NoVm<funct6_vs, vs1, opv, opcodestr # ".vs">;
 }
 
 // vaeskf1.vi and vaeskf2.vi uses different opcode and format, we need
 // to customize one for them.
 class VAESKF_MV_I<bits<6> funct6, string opcodestr, Operand optype>
     : VALUVINoVm<funct6, opcodestr, optype> {
-  let Opcode = OPC_OP_P.Value;
+  let Inst{6-0} = OPC_OP_P.Value;
   let Inst{14-12} = OPMVV.Value;
 }
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
 def RnumArg_0_7 : AsmOperandClass {
   let Name = "RnumArg_0_7";
   let RenderMethod = "addImmOperands";
   let DiagnosticType = "InvalidRnumArg_0_7";