[RISCV] Remove zvk uimm constraints

[4vtomat]

Summary

Since the spec doesn't describe these behaviors as invalid,
the llvm-mc should just make them take care by hardware.

[craig.topper]

LGTM, but I'll give others time to chime in.

[asb]

This change overall looks good to me, but you should add additional lines to the ext-valid.s files so that we have test coverage for inputs using these immediates.

[ego]

LGTM.
I was initially surprised however the current spec makes all values valid by prescribing how seemingly "out of range" immediate field values get re-interpreted as being in-range. This wasn't the case in early version of the spec.

Thanks for bringing the behavior in line with the spec.

[craig.topper]

Reverse ping. Can we get this updated and committed before the branch?

[4vtomat]

Sorry for late update.
This update adds test case to zvkned.s and zvksed.s for more coverage as Alex mentioned.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

case Match_InvalidSpimm: {
     return Error(
         ErrorLoc,
         "stack adjustment is invalid for this instruction and register list; "
         "refer to Zc spec for a detailed range of stack adjustment");
   }
   case Match_InvalidRnumArg: {
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10);
   }
-  case Match_InvalidRnumArg_0_7: {
-    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 7);
-  }
-  case Match_InvalidRnumArg_1_10: {
-    return generateImmOutOfRangeError(Operands, ErrorInfo, 1, 10);
-  }
-  case Match_InvalidRnumArg_2_14: {
-    return generateImmOutOfRangeError(Operands, ErrorInfo, 2, 14);
-  }
   }
 
   llvm_unreachable("Unknown match type detected!");
 }
 
 // Attempts to match Name as a register (either using the default name or
 // alternative ABI names), setting RegNo to the matching register. Upon
 // failure, returns a non-valid MCRegister. If IsRVE, then registers x16-x31

llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

let Predicates = [HasStdExtZvknha], RVVConstraint = NoConstraint in {
   def VSHA2MS_VV : PALUVVNoVm<0b101101, OPMVV, "vsha2ms.vv">;
 } // Predicates = [HasStdExtZvknha]
 
 let Predicates = [HasStdExtZvkned], RVVConstraint = NoConstraint in {
   defm VAESDF     : VAES_MV_V_S<0b101000, 0b101001, 0b00001, OPMVV, "vaesdf">;
   defm VAESDM     : VAES_MV_V_S<0b101000, 0b101001, 0b00000, OPMVV, "vaesdm">;
   defm VAESEF     : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;
   defm VAESEM     : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
-  def  VAESKF1_VI : VAESKF_MV_I<0b100010, "vaeskf1.vi", rnum_1_10>;
-  def  VAESKF2_VI : VAESKF_MV_I<0b101010, "vaeskf2.vi", rnum_2_14>;
+  def  VAESKF1_VI : VAESKF_MV_I<0b100010, "vaeskf1.vi", uimm5>;
+  def  VAESKF2_VI : VAESKF_MV_I<0b101010, "vaeskf2.vi", uimm5>;
   def  VAESZ_VS   : PALUVs2NoVm<0b101001, 0b00111, OPMVV, "vaesz.vs">;
 } // Predicates = [HasStdExtZvkned]
 
 let Predicates = [HasStdExtZvksed], RVVConstraint = NoConstraint in {
-  def  VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", rnum_0_7>;
+  def  VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", uimm5>;
   defm VSM4R    : VAES_MV_V_S<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">;
 } // Predicates = [HasStdExtZvksed]
 
 let Predicates = [HasStdExtZvksh], RVVConstraint = NoConstraint in {
   def VSM3C_VI  : PALUVINoVm<0b101011, "vsm3c.vi", uimm5>;
   def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">;
 } // Predicates = [HasStdExtZvksh]
 

llvm/test/MC/RISCV/rvv/zvkned-invalid.s

-# RUN: not llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkned %s 2>&1 \
-# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
-
-vaeskf1.vi v10, v9, 0
-# CHECK-ERROR: immediate must be an integer in the range [1, 10]
-
-vaeskf2.vi v10, v9, 0
-# CHECK-ERROR: immediate must be an integer in the range [2, 14]

llvm/test/MC/RISCV/rvv/zvkned.s

 # CHECK-UNKNOWN: 77 25 91 a6   <unknown>
 
 vaeskf1.vi v10, v9, 1
 # CHECK-INST: vaeskf1.vi v10, v9, 1
 # CHECK-ENCODING: [0x77,0xa5,0x90,0x8a]
 # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
 # CHECK-UNKNOWN: 77 a5 90 8a   <unknown>
 
+vaeskf1.vi v10, v9, 31
+# CHECK-INST: vaeskf1.vi v10, v9, 31
+# CHECK-ENCODING: [0x77,0xa5,0x9f,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 77 a5 9f 8a   <unknown>
+
 vaeskf2.vi v10, v9, 2
 # CHECK-INST: vaeskf2.vi v10, v9, 2
 # CHECK-ENCODING: [0x77,0x25,0x91,0xaa]
 # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
 # CHECK-UNKNOWN: 77 25 91 aa   <unknown>
 
+vaeskf2.vi v10, v9, 31
+# CHECK-INST: vaeskf2.vi v10, v9, 31
+# CHECK-ENCODING: [0x77,0xa5,0x9f,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 77 a5 9f aa   <unknown>
+
 vaesz.vs v10, v9
 # CHECK-INST: vaesz.vs v10, v9
 # CHECK-ENCODING: [0x77,0xa5,0x93,0xa6]
 # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
 # CHECK-UNKNOWN: 77 a5 93 a6   <unknown>

llvm/test/MC/RISCV/rvv/zvksed-invalid.s

-# RUN: not llvm-mc -triple=riscv32 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
-# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
-
-vsm4k.vi v10, v9, 8
-# CHECK-ERROR: immediate must be an integer in the range [0, 7]

llvm/test/MC/RISCV/rvv/zvksed.s

 # RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
 # RUN:        | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
 # RUN:        | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
 # RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 vsm4k.vi v10, v9, 7
 # CHECK-INST: vsm4k.vi v10, v9, 7
 # CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
 # CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions){{$}}
 # CHECK-UNKNOWN: 77 a5 93 86   <unknown>
 
+vsm4k.vi v10, v9, 31
+# CHECK-INST: vsm4k.vi v10, v9, 31
+# CHECK-ENCODING: [0x77,0xa5,0x9f,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions){{$}}
+# CHECK-UNKNOWN: 77 a5 9f 86   <unknown>
+
 vsm4r.vv v10, v9
 # CHECK-INST: vsm4r.vv v10, v9
 # CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
 # CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions){{$}}
 # CHECK-UNKNOWN: 77 25 98 a2   <unknown>
 
 vsm4r.vs v10, v9
 # CHECK-INST: vsm4r.vs v10, v9
 # CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
 # CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions){{$}}
 # CHECK-UNKNOWN: 77 25 98 a6   <unknown>