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Differential D154525

[llvm-mca][RISCV] Fix typo in test for vsetvli instruction
ClosedPublic

Authored by michaelmaitland on Jul 5 2023, 10:13 AM.

Details

Reviewers
myhsu
craig.topper
reames
andreadb
Commits
rGa1b3b9d05d53: [llvm-mca][RISCV] Fix typo in test for vsetvli instruction
Summary

The instrument comment specified a different LMUL than the vsetvli
above it. This patch syncs the LMUL comment and the vsetvli.

Diff Detail

Event Timeline

michaelmaitland created this revision.Jul 5 2023, 10:13 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 5 2023, 10:13 AM
Herald added subscribers: jobnoorman, luke, VincentWu and 28 others. · View Herald Transcript
michaelmaitland requested review of this revision.Jul 5 2023, 10:13 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 5 2023, 10:13 AM
Herald added subscribers: llvm-commits, wangpc, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B243255: Diff 537411.Jul 5 2023, 11:56 AM
andreadb accepted this revision.Jul 5 2023, 12:27 PM

LGTM

This revision is now accepted and ready to land.Jul 5 2023, 12:27 PM
Closed by commit rGa1b3b9d05d53: [llvm-mca][RISCV] Fix typo in test for vsetvli instruction (authored by michaelmaitland). · Explain WhyJul 5 2023, 12:43 PM
This revision was automatically updated to reflect the committed changes.
michaelmaitland added a commit: rGa1b3b9d05d53: [llvm-mca][RISCV] Fix typo in test for vsetvli instruction.

Revision Contents

PathSize
llvm/
test/
tools/
llvm-mca/
RISCV/
10 lines
10 lines

Diff 537411

llvm/test/tools/llvm-mca/RISCV/instrument-in-middle.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
vsetvli zero, a0, e8, m8, tu, mu vsetvli zero, a0, e8, mf8, tu, mu
# LLVM-MCA-RISCV-LMUL MF8 # LLVM-MCA-RISCV-LMUL MF8
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 3 # CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 21 # CHECK-NEXT: Total Cycles: 21
# CHECK-NEXT: Total uOps: 3 # CHECK-NEXT: Total uOps: 3
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.14 # CHECK-NEXT: uOps Per Cycle: 0.14
# CHECK-NEXT: IPC: 0.14 # CHECK-NEXT: IPC: 0.14
# CHECK-NEXT: Block RThroughput: 17.0 # CHECK-NEXT: Block RThroughput: 17.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, mf8, tu, mu
# CHECK-NEXT: 1 4 1.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 1.00 vadd.vv v12, v12, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 17.00 17.00 - - # CHECK-NEXT: - - 1.00 - 17.00 17.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, mf8, tu, mu
# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vv v12, v12, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123456789 # CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 0 # CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . vadd.vv v12, v12, v12 # CHECK: [0,0] DeeeE. . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,1] .DeeE. . . . vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: [0,1] .DeeE. . . . vsetvli zero, a0, e8, mf8, tu, mu
# CHECK-NEXT: [0,2] . . . .DeeeE vadd.vv v12, v12, v12 # CHECK-NEXT: [0,2] . . . .DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, mf8, tu, mu
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 2. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total> # CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/multiple-same-instruments.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1 # LLVM-MCA-RISCV-LMUL M1
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1 # LLVM-MCA-RISCV-LMUL M1
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
vsub.vv v12, v12, v12 vsub.vv v12, v12, v12
vsetvli zero, a0, e8, m2, tu, mu vsetvli zero, a0, e8, m4, tu, mu
# LLVM-MCA-RISCV-LMUL M4 # LLVM-MCA-RISCV-LMUL M4
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
vsub.vv v12, v12, v12 vsub.vv v12, v12, v12
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 8 # CHECK-NEXT: Instructions: 8
# CHECK-NEXT: Total Cycles: 28 # CHECK-NEXT: Total Cycles: 28
# CHECK-NEXT: Total uOps: 8 # CHECK-NEXT: Total uOps: 8
Show All 12 Lines
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 2.00 vsub.vv v12, v12, v12 # CHECK-NEXT: 1 4 2.00 vsub.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m2, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m4, tu, mu
# CHECK-NEXT: 1 4 8.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 8.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 8.00 vsub.vv v12, v12, v12 # CHECK-NEXT: 1 4 8.00 vsub.vv v12, v12, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 3.00 - 22.00 22.00 - - # CHECK-NEXT: - - 3.00 - 22.00 22.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 2.00 2.00 - - vsub.vv v12, v12, v12 # CHECK-NEXT: - - - - 2.00 2.00 - - vsub.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m2, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m4, tu, mu
# CHECK-NEXT: - - - - 8.00 8.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 8.00 8.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 8.00 8.00 - - vsub.vv v12, v12, v12 # CHECK-NEXT: - - - - 8.00 8.00 - - vsub.vv v12, v12, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123456789 # CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 01234567 # CHECK-NEXT: Index 0123456789 01234567
# CHECK: [0,0] DeeE . . . . . . vsetvli zero, a0, e8, m1, tu, mu # CHECK: [0,0] DeeE . . . . . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE . . . . . vadd.vv v12, v12, v12 # CHECK-NEXT: [0,1] . DeeeE . . . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,2] . DeeE . . . . . vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: [0,2] . DeeE . . . . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,3] . . DeeeE . . . . vadd.vv v12, v12, v12 # CHECK-NEXT: [0,3] . . DeeeE . . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,4] . . .DeeeE . . . vsub.vv v12, v12, v12 # CHECK-NEXT: [0,4] . . .DeeeE . . . vsub.vv v12, v12, v12
# CHECK-NEXT: [0,5] . . . DeeE . . . vsetvli zero, a0, e8, m2, tu, mu # CHECK-NEXT: [0,5] . . . DeeE . . . vsetvli zero, a0, e8, m4, tu, mu
# CHECK-NEXT: [0,6] . . . DeeeE. . . vadd.vv v12, v12, v12 # CHECK-NEXT: [0,6] . . . DeeeE. . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,7] . . . . . DeeeE vsub.vv v12, v12, v12 # CHECK-NEXT: [0,7] . . . . . DeeeE vsub.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 4. 1 0.0 0.0 0.0 vsub.vv v12, v12, v12 # CHECK-NEXT: 4. 1 0.0 0.0 0.0 vsub.vv v12, v12, v12
# CHECK-NEXT: 5. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m2, tu, mu # CHECK-NEXT: 5. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m4, tu, mu
# CHECK-NEXT: 6. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 6. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 7. 1 0.0 0.0 0.0 vsub.vv v12, v12, v12 # CHECK-NEXT: 7. 1 0.0 0.0 0.0 vsub.vv v12, v12, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total> # CHECK-NEXT: 1 0.0 0.0 0.0 <total>