[RISCV] Add SEW to RISCVInversePseudoTable

[michaelmaitland]

Summary

Now that scheduler resources are split by SEW for some instructions,
add the ability to map (BaseInstr, LMUL, SEW) -> Pseudo. For
BaseInstrs that are not split by SEW, 0 is the default key.

This keeps the number of Pseudos the same and does not change
the size of RISCVInversePseudoTable. This table is only imported
when llvm-mca is built, so if you don't build llvm-mca, the size of
PseudoTables does not change.

This change will be used in a future patch by llvm-mca to determine
the schedule class based off of SEW data, now that the scheduler
now accounts for SEW for some instructions.

[craig.topper]

llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp

34

I dont' think this changes the table size. There was an 8 bit hole here.

llvm/lib/Target/RISCV/RISCVInstrFormats.td

222 ↗

(On Diff #535958)

nit: bits<2> not bit<2>

224 ↗

(On Diff #535958)

Can this be in the RISCVVPseudo class?

[myhsu]

llvm/lib/Target/RISCV/RISCVInstrFormats.td

222 ↗

(On Diff #535958)

making the field smaller: using something similar to MxSet might help. For instance:

let SEW = MxSet2<eew>.m in ...

[michaelmaitland]

Represent SEW in bits<3>

llvm/lib/Target/RISCV/RISCVInstrFormats.td

224 ↗

(On Diff #535958)

It did, but it feels slightly out of place since VLMul exists in RVInst. I wonder if VLMul should be moved to RISCVVPseudo in a separate patch.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrFormats.td

224 ↗

(On Diff #535958)

VLMul has to be there because it is part of TSFlags.

[michaelmaitland]

llvm/lib/Target/RISCV/RISCVInstrFormats.td

224 ↗

(On Diff #535958)

I understand now. I've moved SEW to RISCVVPseudo.

[myhsu]

this patch LGTM, @craig.topper do you have any other comments?

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

512

Why do we need to compress it 3 bits in tablegen, but we use 8 bits in RISCVCustomBehaviour.cpp?

[michaelmaitland]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

512

I can revert it to 8. I made it 3 because it looked like we were trying to pack tightly in this class. 3 bits ID as tight as you can get to represent this encoding. We can hold off on making it 3 until we’d like to add a field to the inverse table and we need the space. Let me know what you think.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

512

I think I'd prefer to use raw SEW rather than new format until we really need it.

[michaelmaitland]

Use 8bit sew

[craig.topper]

LGTM

[craig.topper]

llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp

104

Does passing 0 here mean it can only find pseudos where SEW is 0?

[michaelmaitland]

llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp

104

Yes, but this change only deals with LMUL specific pseudos, not LMUL and SEW specific pseudos. Please see the child patch to see how we deal with SEW specific pseudos.

llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp

 namespace RISCVVInversePseudosTable {
 using namespace llvm;
 using namespace llvm::RISCV;
 
 struct PseudoInfo {
   uint16_t Pseudo;
   uint16_t BaseInstr;
   uint8_t VLMul;
+  uint8_t SEW;
 };
 
 #define GET_RISCVVInversePseudosTable_IMPL
 #define GET_RISCVVInversePseudosTable_DECL
 #include "RISCVGenSearchableTables.inc"
 
 } // end namespace RISCVVInversePseudosTable
 
unsigned RISCVInstrumentManager::getSchedClassID(
   unsigned short Opcode = MCI.getOpcode();
   unsigned SchedClassID = MCII.get(Opcode).getSchedClass();
 
   for (const auto &I : IVec) {
     // Unknown Instrument kind
     if (I->getDesc() == RISCVLMULInstrument::DESC_NAME) {
       uint8_t LMUL = static_cast<RISCVLMULInstrument *>(I)->getLMUL();
       const RISCVVInversePseudosTable::PseudoInfo *RVV =
-          RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL);
+          RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0);
       // Not a RVV instr
       if (!RVV) {
         LLVM_DEBUG(
             dbgs()
             << "RVCB: Could not find PseudoInstruction for Opcode "
             << MCII.getName(Opcode) << ", LMUL=" << I->getData()
             << ". Ignoring instrumentation and using original SchedClassID="
             << SchedClassID << '\n');

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

 // This class holds the record of the RISCVVPseudoTable below.
 // This represents the information we need in codegen for each pseudo.
 // The definition should be consistent with `struct PseudoInfo` in
 // RISCVBaseInfo.h.
 class CONST8b<bits<8> val> {
   bits<8> V = val;
 }
 def InvalidIndex : CONST8b<0x80>;
+
+
+/// This class maps sew onto a bits<3> field so that SEW can be represented
+/// in as few bits as possible. This mapping does not come from the RVV spec
+/// and is an implementation defined mapping.
+class SEWTo3BitSEW<int sew> {
+  bits<3> s = !cond(
+    !eq(sew, 0) : 0b000,
+    !eq(sew, 8) : 0b001,
+    !eq(sew, 16) : 0b010,
+    !eq(sew, 32) : 0b011,
+    !eq(sew, 64) : 0b100
+  );
+}
+
 class RISCVVPseudo {
   Pseudo Pseudo = !cast<Pseudo>(NAME); // Used as a key.
   Instruction BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+
+  // SEW = 0 is used to denote that the RVInst is not SEW specific (Unknown).
+  // Unknown=0b000, E8 = 0b001, E16=0b010, E32=0b011, E64=0b100. This mapping
+  // does not come from the RVV spec and is an implementation defined mapping.
+  bits<3> SEW = 0;
 }
 
 // The actual table.
 def RISCVVPseudosTable : GenericTable {
   let FilterClass = "RISCVVPseudo";
   let CppTypeName = "PseudoInfo";
   let Fields = [ "Pseudo", "BaseInstr" ];
   let PrimaryKey = [ "Pseudo" ];
   let PrimaryKeyName = "getPseudoInfo";
   let PrimaryKeyEarlyOut = true;
 }
 
 def RISCVVInversePseudosTable : GenericTable {
   let FilterClass = "RISCVVPseudo";
   let CppTypeName = "PseudoInfo";
-  let Fields = [ "Pseudo", "BaseInstr", "VLMul" ];
-  let PrimaryKey = [ "BaseInstr", "VLMul" ];
+  let Fields = [ "Pseudo", "BaseInstr", "VLMul", "SEW"];
+  let PrimaryKey = [ "BaseInstr", "VLMul", "SEW"];
   let PrimaryKeyName = "getBaseInfo";
   let PrimaryKeyEarlyOut = true;
 }
 
 def RISCVVIntrinsicsTable : GenericTable {
   let FilterClass = "RISCVVIntrinsic";
   let CppTypeName = "RISCVVIntrinsicInfo";
   let Fields = ["IntrinsicID", "ScalarOperand", "VLOperand"];
class Join<list<string> strings, string separator> {
   string ret = !foldl(!head(strings), !tail(strings), a, b,
                       !cond(
                         !and(!empty(a), !empty(b)) : "",
                         !empty(a) : b,
                         !empty(b) : a,
                         1 : a#separator#b));
 }
 
-class VPseudo<Instruction instr, LMULInfo m, dag outs, dag ins> :
+class VPseudo<Instruction instr, LMULInfo m, dag outs, dag ins, int sew = 0> :
       Pseudo<outs, ins, []>, RISCVVPseudo {
   let BaseInstr = instr;
   let VLMul = m.value;
+  let SEW = SEWTo3BitSEW<sew>.s;
 }
 
 class GetVTypePredicates<VTypeInfo vti> {
   list<Predicate> Predicates = !cond(!eq(vti.Scalar, f16) : [HasVInstructionsF16],
                                      !eq(vti.Scalar, f32) : [HasVInstructionsAnyF],
                                      !eq(vti.Scalar, f64) : [HasVInstructionsF64],
                                      !eq(vti.SEW, 64) : [HasVInstructionsI64],
                                      true : [HasVInstructions]);
class VPseudoISegStoreMask<VReg ValClass, VReg IdxClass, int EEW, bits<3> LMUL,
   let HasSEWOp = 1;
 }
 
 multiclass VPseudoUSLoad {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         def "E" # eew # "_V_" # LInfo :
           VPseudoUSLoadNoMask<vreg, eew>,
           VLESched<LInfo>;
         def "E" # eew # "_V_" # LInfo # "_TU":
           VPseudoUSLoadNoMaskTU<vreg, eew>,
           VLESched<LInfo>;
         def "E" # eew # "_V_" # LInfo # "_MASK" :
           VPseudoUSLoadMask<vreg, eew>,
           RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
           VLESched<LInfo>;
       }
     }
   }
 }
 
 multiclass VPseudoFFLoad {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         def "E" # eew # "FF_V_" # LInfo:
           VPseudoUSLoadFFNoMask<vreg, eew>,
           VLFSched<LInfo>;
         def "E" # eew # "FF_V_" # LInfo # "_TU":
           VPseudoUSLoadFFNoMaskTU<vreg, eew>,
           VLFSched<LInfo>;
         def "E" # eew # "FF_V_" # LInfo # "_MASK":
           VPseudoUSLoadFFMask<vreg, eew>,
multiclass VPseudoLoadMask {
   }
 }
 
 multiclass VPseudoSLoad {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         def "E" # eew # "_V_" # LInfo : VPseudoSLoadNoMask<vreg, eew>,
                                         VLSSched<eew, LInfo>;
         def "E" # eew # "_V_" # LInfo # "_TU": VPseudoSLoadNoMaskTU<vreg, eew>,
                                         VLSSched<eew, LInfo>;
         def "E" # eew # "_V_" # LInfo # "_MASK" :
           VPseudoSLoadMask<vreg, eew>,
           RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
           VLSSched<eew, LInfo>;
multiclass VPseudoILoad<bit Ordered> {
   }
 }
 
 multiclass VPseudoUSStore {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         def "E" # eew # "_V_" # LInfo : VPseudoUSStoreNoMask<vreg, eew>,
                                         VSESched<LInfo>;
         def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSStoreMask<vreg, eew>,
                                                   VSESched<LInfo>;
       }
     }
   }
 }
multiclass VPseudoStoreMask {
   }
 }
 
 multiclass VPseudoSStore {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         def "E" # eew # "_V_" # LInfo : VPseudoSStoreNoMask<vreg, eew>,
                                         VSSSched<eew, LInfo>;
         def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSStoreMask<vreg, eew>,
                                                   VSSSched<eew, LInfo>;
       }
     }
   }
 }
foreach m = MxList in {
     defvar mx = m.MX;
     defvar sews = SchedSEWSet<mx>.val;
     let VLMul = m.value in
       foreach e = sews in {
         defvar suffix = "_" # m.MX # "_E" # e;
         defvar WriteVCompressV_MX_E = !cast<SchedWrite>("WriteVCompressV" # suffix);
         defvar ReadVCompressV_MX_E = !cast<SchedRead>("ReadVCompressV" # suffix);
 
+        let SEW = SEWTo3BitSEW<e>.s in
         def _VM # suffix : VPseudoUnaryAnyMask<m.vrclass, m.vrclass>,
                            Sched<[WriteVCompressV_MX_E, ReadVCompressV_MX_E, ReadVCompressV_MX_E]>;
       }
   }
 }
 
 multiclass VPseudoBinary<VReg RetClass,
                          VReg Op1Class,
                          DAGOperand Op2Class,
                          LMULInfo MInfo,
                          string Constraint = "",
                          int sew = 0> {
-  let VLMul = MInfo.value in {
+  let VLMul = MInfo.value, SEW=SEWTo3BitSEW<sew>.s in {
     defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
     def suffix : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
                                      Constraint>;
     def suffix # "_TU" : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class,
                                                Constraint>;
     def suffix # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
                                                    Constraint>,
                            RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
   }
 }
 
 multiclass VPseudoBinaryRoundingMode<VReg RetClass,
                                      VReg Op1Class,
                                      DAGOperand Op2Class,
                                      LMULInfo MInfo,
                                      string Constraint = "",
                                      int sew = 0> {
-  let VLMul = MInfo.value in {
+  let VLMul = MInfo.value, SEW=SEWTo3BitSEW<sew>.s in {
     defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
     def suffix : VPseudoBinaryNoMaskRoundingMode<RetClass, Op1Class, Op2Class,
                                                  Constraint>;
     def suffix # "_TU" :VPseudoBinaryNoMaskTURoundingMode<RetClass,
                                                           Op1Class, Op2Class,
                                                           Constraint>;
     def suffix # "_MASK" : VPseudoBinaryMaskPolicyRoundingMode<RetClass,
                                                                Op1Class,

 
 multiclass VPseudoBinaryEmul<VReg RetClass,
                              VReg Op1Class,
                              DAGOperand Op2Class,
                              LMULInfo lmul,
                              LMULInfo emul,
                              string Constraint = "",
                              int sew = 0> {
-  let VLMul = lmul.value in {
+  let VLMul = lmul.value, SEW=SEWTo3BitSEW<sew>.s in {
     defvar suffix = !if(sew, "_" # lmul.MX # "_E" # sew, "_" # lmul.MX);
     def suffix # "_" # emul.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
                                                             Constraint>;
     def suffix # "_" # emul.MX # "_TU": VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class,
                                                                      Constraint>;
     def suffix # "_" # emul.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
                                                                           Constraint>,
                                                   RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
foreach m = MxListF in {
     defvar sews = SchedSEWSet<m.MX, /*isF*/ 1>.val;
 
     let VLMul = m.value in
       foreach e = sews in {
         defvar suffix = "_" # mx # "_E" # e;
         defvar WriteVFSqrtV_MX_E = !cast<SchedWrite>("WriteVFSqrtV" # suffix);
         defvar ReadVFSqrtV_MX_E = !cast<SchedRead>("ReadVFSqrtV" # suffix);
 
+        let SEW = SEWTo3BitSEW<e>.s in {
           def "_V" # suffix : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
                               Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
                                      ReadVMask]>;
           def "_V" # suffix # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.vrclass>,
                                      Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
                                             ReadVMask]>;
           def "_V" # suffix # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
                                         RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
                                         Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
                                                ReadVMask]>;
         }
       }
   }
+}
 
 multiclass VPseudoVRCP_V {
   foreach m = MxListF in {
     defvar mx = m.MX;
     defvar WriteVFRecpV_MX = !cast<SchedWrite>("WriteVFRecpV_" # mx);
     defvar ReadVFRecpV_MX = !cast<SchedRead>("ReadVFRecpV_" # mx);
 
     let VLMul = m.value in {
defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint>,
               Sched<[WriteVFNCvtFToFV_MX, ReadVFNCvtFToFV_MX, ReadVMask]>;
   }
 }
 
 multiclass VPseudoUSSegLoad {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         foreach nf = NFSet<lmul>.L in {
           defvar vreg = SegRegClass<lmul, nf>.RC;
           def nf # "E" # eew # "_V_" # LInfo :
             VPseudoUSSegLoadNoMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;
           def nf # "E" # eew # "_V_" # LInfo # "_TU" :
             VPseudoUSSegLoadNoMaskTU<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;
           def nf # "E" # eew # "_V_" # LInfo # "_MASK" :
             VPseudoUSSegLoadMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;
         }
       }
     }
   }
 }
 
 multiclass VPseudoUSSegLoadFF {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         foreach nf = NFSet<lmul>.L in {
           defvar vreg = SegRegClass<lmul, nf>.RC;
           def nf # "E" # eew # "FF_V_" # LInfo :
             VPseudoUSSegLoadFFNoMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;
           def nf # "E" # eew # "FF_V_" # LInfo # "_TU" :
             VPseudoUSSegLoadFFNoMaskTU<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;
           def nf # "E" # eew # "FF_V_" # LInfo # "_MASK" :
             VPseudoUSSegLoadFFMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;
         }
       }
     }
   }
 }
 
 multiclass VPseudoSSegLoad {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         foreach nf = NFSet<lmul>.L in {
           defvar vreg = SegRegClass<lmul, nf>.RC;
           def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegLoadNoMask<vreg, eew, nf>,
                                                VLSSEGSched<nf, eew, LInfo>;
           def nf # "E" # eew # "_V_" # LInfo # "_TU" : VPseudoSSegLoadNoMaskTU<vreg, eew, nf>,
                                                        VLSSEGSched<nf, eew, LInfo>;
           def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegLoadMask<vreg, eew, nf>,
                                                          VLSSEGSched<nf, eew, LInfo>;
foreach idxEEW = EEWList in {
     }
   }
 }
 
 multiclass VPseudoUSSegStore {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         foreach nf = NFSet<lmul>.L in {
           defvar vreg = SegRegClass<lmul, nf>.RC;
           def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegStoreNoMask<vreg, eew, nf>,
                                                VSSEGSched<nf, eew, LInfo>;
           def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSSegStoreMask<vreg, eew, nf>,
                                                          VSSEGSched<nf, eew, LInfo>;
         }
       }
     }
   }
 }
 
 multiclass VPseudoSSegStore {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
-      let VLMul = lmul.value in {
+      let VLMul = lmul.value, SEW=SEWTo3BitSEW<eew>.s in {
         foreach nf = NFSet<lmul>.L in {
           defvar vreg = SegRegClass<lmul, nf>.RC;
           def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegStoreNoMask<vreg, eew, nf>,
                                                VSSSEGSched<nf, eew, LInfo>;
           def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegStoreMask<vreg, eew, nf>,
                                                          VSSSEGSched<nf, eew, LInfo>;
         }
       }