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Differential D153112

[RISCV] Match shl (ext v, splat 1) to vector widening add.
ClosedPublic

Authored by jacquesguan on Jun 16 2023, 2:04 AM.

Details

Reviewers
craig.topper
asb
luismarques
frasercrmck
Commits
rG04ed822dcc21: [RISCV] Match shl (ext v, splat 1) to vector widening add.
Summary

Since we use match shl (v, splat 1) to vadd, we could also expand to widening add.

Diff Detail

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
21 lines
test/
CodeGen/
RISCV/
rvv/
12 lines
12 lines
10 lines
10 lines

Diff 532498

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

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defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, sext_oneuse, "PseudoVWADD">; defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, sext_oneuse, "PseudoVWADD">;
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, zext_oneuse, "PseudoVWADDU">; defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, zext_oneuse, "PseudoVWADDU">;
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, anyext_oneuse, "PseudoVWADDU">; defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, anyext_oneuse, "PseudoVWADDU">;
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, sext_oneuse, "PseudoVWSUB">; defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, sext_oneuse, "PseudoVWSUB">;
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, zext_oneuse, "PseudoVWSUBU">; defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, zext_oneuse, "PseudoVWSUBU">;
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, anyext_oneuse, "PseudoVWSUBU">; defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, anyext_oneuse, "PseudoVWSUBU">;
// shl (ext v, splat 1) is a special case of widening add.
foreach vtiToWti = AllWidenableIntVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
def : Pat<(shl (wti.Vector (sext_oneuse (vti.Vector vti.RegClass:$rs1))),
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), 1, (XLenVT srcvalue)))),
(!cast<Instruction>("PseudoVWADD_VV_"#vti.LMul.MX)
vti.RegClass:$rs1, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
def : Pat<(shl (wti.Vector (zext_oneuse (vti.Vector vti.RegClass:$rs1))),
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), 1, (XLenVT srcvalue)))),
(!cast<Instruction>("PseudoVWADDU_VV_"#vti.LMul.MX)
vti.RegClass:$rs1, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
def : Pat<(shl (wti.Vector (anyext_oneuse (vti.Vector vti.RegClass:$rs1))),
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), 1, (XLenVT srcvalue)))),
(!cast<Instruction>("PseudoVWADDU_VV_"#vti.LMul.MX)
vti.RegClass:$rs1, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
}
}
// 11.3. Vector Integer Extension // 11.3. Vector Integer Extension
defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF2", defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF2",
AllFractionableVF2IntVectors>; AllFractionableVF2IntVectors>;
defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF2", defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF2",
AllFractionableVF2IntVectors>; AllFractionableVF2IntVectors>;
defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF4", defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF4",
AllFractionableVF4IntVectors>; AllFractionableVF4IntVectors>;
defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF4", defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF4",
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llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

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%ptrs = getelementptr inbounds i16, ptr %base, <vscale x 8 x i16> %eidxs %ptrs = getelementptr inbounds i16, ptr %base, <vscale x 8 x i16> %eidxs
%v = call <vscale x 8 x i16> @llvm.masked.gather.nxv8i16.nxv8p0(<vscale x 8 x ptr> %ptrs, i32 2, <vscale x 8 x i1> %m, <vscale x 8 x i16> %passthru) %v = call <vscale x 8 x i16> @llvm.masked.gather.nxv8i16.nxv8p0(<vscale x 8 x ptr> %ptrs, i32 2, <vscale x 8 x i1> %m, <vscale x 8 x i16> %passthru)
ret <vscale x 8 x i16> %v ret <vscale x 8 x i16> %v
} }
define <vscale x 8 x i16> @mgather_baseidx_nxv8i16(ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i16> %passthru) { define <vscale x 8 x i16> @mgather_baseidx_nxv8i16(ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i16> %passthru) {
; RV32-LABEL: mgather_baseidx_nxv8i16: ; RV32-LABEL: mgather_baseidx_nxv8i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; RV32-NEXT: vsetvli a1, zero, e16, m2, ta, mu
; RV32-NEXT: vsext.vf2 v12, v8 ; RV32-NEXT: vwadd.vv v12, v8, v8
; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv.v.v v8, v10 ; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_nxv8i16: ; RV64-LABEL: mgather_baseidx_nxv8i16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v16, v8 ; RV64-NEXT: vsext.vf4 v16, v8
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%ptrs = getelementptr inbounds half, ptr %base, <vscale x 8 x i16> %eidxs %ptrs = getelementptr inbounds half, ptr %base, <vscale x 8 x i16> %eidxs
%v = call <vscale x 8 x half> @llvm.masked.gather.nxv8f16.nxv8p0(<vscale x 8 x ptr> %ptrs, i32 2, <vscale x 8 x i1> %m, <vscale x 8 x half> %passthru) %v = call <vscale x 8 x half> @llvm.masked.gather.nxv8f16.nxv8p0(<vscale x 8 x ptr> %ptrs, i32 2, <vscale x 8 x i1> %m, <vscale x 8 x half> %passthru)
ret <vscale x 8 x half> %v ret <vscale x 8 x half> %v
} }
define <vscale x 8 x half> @mgather_baseidx_nxv8f16(ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x half> %passthru) { define <vscale x 8 x half> @mgather_baseidx_nxv8f16(ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x half> %passthru) {
; RV32-LABEL: mgather_baseidx_nxv8f16: ; RV32-LABEL: mgather_baseidx_nxv8f16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; RV32-NEXT: vsetvli a1, zero, e16, m2, ta, mu
; RV32-NEXT: vsext.vf2 v12, v8 ; RV32-NEXT: vwadd.vv v12, v8, v8
; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv.v.v v8, v10 ; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_nxv8f16: ; RV64-LABEL: mgather_baseidx_nxv8f16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v16, v8 ; RV64-NEXT: vsext.vf4 v16, v8
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llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll

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%ptrs = getelementptr inbounds i16, ptr %base, <vscale x 8 x i16> %eidxs %ptrs = getelementptr inbounds i16, ptr %base, <vscale x 8 x i16> %eidxs
call void @llvm.masked.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> %val, <vscale x 8 x ptr> %ptrs, i32 2, <vscale x 8 x i1> %m) call void @llvm.masked.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> %val, <vscale x 8 x ptr> %ptrs, i32 2, <vscale x 8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_nxv8i16(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_nxv8i16(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_nxv8i16: ; RV32-LABEL: mscatter_baseidx_nxv8i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; RV32-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; RV32-NEXT: vsext.vf2 v12, v10 ; RV32-NEXT: vwadd.vv v12, v10, v10
; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_nxv8i16: ; RV64-LABEL: mscatter_baseidx_nxv8i16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v16, v10 ; RV64-NEXT: vsext.vf4 v16, v10
; RV64-NEXT: vadd.vv v16, v16, v16 ; RV64-NEXT: vadd.vv v16, v16, v16
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%ptrs = getelementptr inbounds half, ptr %base, <vscale x 8 x i16> %eidxs %ptrs = getelementptr inbounds half, ptr %base, <vscale x 8 x i16> %eidxs
call void @llvm.masked.scatter.nxv8f16.nxv8p0(<vscale x 8 x half> %val, <vscale x 8 x ptr> %ptrs, i32 2, <vscale x 8 x i1> %m) call void @llvm.masked.scatter.nxv8f16.nxv8p0(<vscale x 8 x half> %val, <vscale x 8 x ptr> %ptrs, i32 2, <vscale x 8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_nxv8f16(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_nxv8f16(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_nxv8f16: ; RV32-LABEL: mscatter_baseidx_nxv8f16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; RV32-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; RV32-NEXT: vsext.vf2 v12, v10 ; RV32-NEXT: vwadd.vv v12, v10, v10
; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_nxv8f16: ; RV64-LABEL: mscatter_baseidx_nxv8f16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v16, v10 ; RV64-NEXT: vsext.vf4 v16, v10
; RV64-NEXT: vadd.vv v16, v16, v16 ; RV64-NEXT: vadd.vv v16, v16, v16
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llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

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%ptrs = getelementptr inbounds i16, ptr %base, <vscale x 8 x i16> %eidxs %ptrs = getelementptr inbounds i16, ptr %base, <vscale x 8 x i16> %eidxs
%v = call <vscale x 8 x i16> @llvm.vp.gather.nxv8i16.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i16> @llvm.vp.gather.nxv8i16.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v ret <vscale x 8 x i16> %v
} }
define <vscale x 8 x i16> @vpgather_baseidx_nxv8i16(ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i16> @vpgather_baseidx_nxv8i16(ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_nxv8i16: ; RV32-LABEL: vpgather_baseidx_nxv8i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma ; RV32-NEXT: vsetvli a2, zero, e16, m2, ta, ma
; RV32-NEXT: vsext.vf2 v12, v8 ; RV32-NEXT: vwadd.vv v12, v8, v8
; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_nxv8i16: ; RV64-LABEL: vpgather_baseidx_nxv8i16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v16, v8 ; RV64-NEXT: vsext.vf4 v16, v8
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%ptrs = getelementptr inbounds half, ptr %base, <vscale x 8 x i16> %eidxs %ptrs = getelementptr inbounds half, ptr %base, <vscale x 8 x i16> %eidxs
%v = call <vscale x 8 x half> @llvm.vp.gather.nxv8f16.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x half> @llvm.vp.gather.nxv8f16.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x half> %v ret <vscale x 8 x half> %v
} }
define <vscale x 8 x half> @vpgather_baseidx_nxv8f16(ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x half> @vpgather_baseidx_nxv8f16(ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_nxv8f16: ; RV32-LABEL: vpgather_baseidx_nxv8f16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma ; RV32-NEXT: vsetvli a2, zero, e16, m2, ta, ma
; RV32-NEXT: vsext.vf2 v12, v8 ; RV32-NEXT: vwadd.vv v12, v8, v8
; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_nxv8f16: ; RV64-LABEL: vpgather_baseidx_nxv8f16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v16, v8 ; RV64-NEXT: vsext.vf4 v16, v8
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llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

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%ptrs = getelementptr inbounds i16, ptr %base, <vscale x 8 x i16> %eidxs %ptrs = getelementptr inbounds i16, ptr %base, <vscale x 8 x i16> %eidxs
call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl) call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_baseidx_nxv8i16(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_nxv8i16(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_nxv8i16: ; RV32-LABEL: vpscatter_baseidx_nxv8i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma ; RV32-NEXT: vsetvli a2, zero, e16, m2, ta, ma
; RV32-NEXT: vsext.vf2 v12, v10 ; RV32-NEXT: vwadd.vv v12, v10, v10
; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_nxv8i16: ; RV64-LABEL: vpscatter_baseidx_nxv8i16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v16, v10 ; RV64-NEXT: vsext.vf4 v16, v10
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%ptrs = getelementptr inbounds half, ptr %base, <vscale x 8 x i16> %eidxs %ptrs = getelementptr inbounds half, ptr %base, <vscale x 8 x i16> %eidxs
call void @llvm.vp.scatter.nxv8f16.nxv8p0(<vscale x 8 x half> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl) call void @llvm.vp.scatter.nxv8f16.nxv8p0(<vscale x 8 x half> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_baseidx_nxv8f16(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_nxv8f16(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_nxv8f16: ; RV32-LABEL: vpscatter_baseidx_nxv8f16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma ; RV32-NEXT: vsetvli a2, zero, e16, m2, ta, ma
; RV32-NEXT: vsext.vf2 v12, v10 ; RV32-NEXT: vwadd.vv v12, v10, v10
; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_nxv8f16: ; RV64-LABEL: vpscatter_baseidx_nxv8f16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v16, v10 ; RV64-NEXT: vsext.vf4 v16, v10
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