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Differential D152680

[RISCV][NFC] Improve encoding/decoding tests for Zbb instructions
ClosedPublic

Authored by RamNalamothu on Jun 12 2023, 12:47 AM.

Details

Reviewers
craig.topper
asb
apazos
Commits
rGdbbd6276f20a: [RISCV][NFC] Improve encoding/decoding tests for Zbb instructions
Summary

Currently llvm/test/MC/RISCV/rv64zbb-valid.s doesn't cover all
the instructions e.g. maxu and llvm/test/MC/RISCV/rv32zbb-valid.s
can have rv64 run lines, similar to what Zba instruction tests have.

This patch does the following.

  • Add rv64 run lines in llvm/test/MC/RISCV/rv32zbb-valid.s
  • Keep only rv64 specific instructions in llvm/test/MC/RISCV/rv64zbb-valid.s
  • Move rv32 instructions, with different encodings from rv64, into llvm/test/MC/RISCV/rv32zbb-only-valid.s

Diff Detail

Unit TestsFailed

TimeTest
60,070 msx64 debian > MLIR.Examples/standalone::test.toy
60,070 msx64 debian > ThreadSanitizer-x86_64.ThreadSanitizer-x86_64::restore_stack.cpp

Event Timeline

RamNalamothu created this revision.Jun 12 2023, 12:47 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 12 2023, 12:47 AM
Herald added subscribers: jobnoorman, luke, VincentWu and 27 others. · View Herald Transcript
RamNalamothu requested review of this revision.Jun 12 2023, 12:47 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 12 2023, 12:47 AM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
RamNalamothu added reviewers: craig.topper, asb, apazos.Jun 12 2023, 12:50 AM
Harbormaster completed remote builds in B238119: Diff 530413.Jun 12 2023, 1:47 AM
asb accepted this revision.Jun 13 2023, 2:11 AM

LGTM, modulo one minor tweak to the rori on RV64 test.

llvm/test/MC/RISCV/rv64zbb-valid.s
13

It would make sense to test the wider shift amount supported on RV64 here

This revision is now accepted and ready to land.Jun 13 2023, 2:11 AM
RamNalamothu updated this revision to Diff 530845.Jun 13 2023, 3:18 AM

Test the wider 6-bit shift amount for rori on RV64.

RamNalamothu marked an inline comment as done.Jun 13 2023, 3:20 AM
Harbormaster completed remote builds in B238445: Diff 530845.Jun 13 2023, 5:34 AM
This revision was landed with ongoing or failed builds.Jun 13 2023, 7:48 AM
Closed by commit rGdbbd6276f20a: [RISCV][NFC] Improve encoding/decoding tests for Zbb instructions (authored by RamNalamothu). · Explain Why
This revision was automatically updated to reflect the committed changes.
RamNalamothu added a commit: rGdbbd6276f20a: [RISCV][NFC] Improve encoding/decoding tests for Zbb instructions.

Revision Contents

PathSize
llvm/
test/
MC/
RISCV/
6 lines
14 lines
37 lines

Diff 530845

llvm/test/MC/RISCV/rv32zbb-only-valid.s

# With Bitmanip base extension: # With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbb -riscv-no-aliases -show-encoding \ # RUN: llvm-mc %s -triple=riscv32 -mattr=+zbb -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbb < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbb < %s \
# RUN: | llvm-objdump --mattr=+zbb -M no-aliases -d -r - \ # RUN: | llvm-objdump --mattr=+zbb -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: zext.h t0, t1 # CHECK-ASM-AND-OBJ: zext.h t0, t1
# CHECK-ASM: encoding: [0xb3,0x42,0x03,0x08] # CHECK-ASM: encoding: [0xb3,0x42,0x03,0x08]
zext.h t0, t1 zext.h t0, t1
# CHECK-ASM-AND-OBJ: rori t0, t1, 31
# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61]
rori t0, t1, 31
# CHECK-ASM-AND-OBJ: rori t0, t1, 0
# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60]
rori t0, t1, 0
# CHECK-ASM-AND-OBJ: rev8 t0, t1 # CHECK-ASM-AND-OBJ: rev8 t0, t1
# CHECK-ASM: encoding: [0x93,0x52,0x83,0x69] # CHECK-ASM: encoding: [0x93,0x52,0x83,0x69]
rev8 t0, t1 rev8 t0, t1

llvm/test/MC/RISCV/rv32zbb-valid.s

# With Bitmanip base extension: # With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbb -riscv-no-aliases -show-encoding \ # RUN: llvm-mc %s -triple=riscv32 -mattr=+zbb -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbb -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbb < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbb < %s \
# RUN: | llvm-objdump --mattr=+zbb -M no-aliases -d -r - \ # RUN: | llvm-objdump --mattr=+zbb -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbb < %s \
# RUN: | llvm-objdump --mattr=+zbb -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: clz t0, t1 # CHECK-ASM-AND-OBJ: clz t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60] # CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
clz t0, t1 clz t0, t1
# CHECK-ASM-AND-OBJ: ctz t0, t1 # CHECK-ASM-AND-OBJ: ctz t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x13,0x60] # CHECK-ASM: encoding: [0x93,0x12,0x13,0x60]
ctz t0, t1 ctz t0, t1
# CHECK-ASM-AND-OBJ: cpop t0, t1 # CHECK-ASM-AND-OBJ: cpop t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x23,0x60] # CHECK-ASM: encoding: [0x93,0x12,0x23,0x60]
cpop t0, t1 cpop t0, t1
# CHECK-ASM-AND-OBJ: sext.b t0, t1 # CHECK-ASM-AND-OBJ: sext.b t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x43,0x60] # CHECK-ASM: encoding: [0x93,0x12,0x43,0x60]
sext.b t0, t1 sext.b t0, t1
# CHECK-ASM-AND-OBJ: sext.h t0, t1 # CHECK-ASM-AND-OBJ: sext.h t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60] # CHECK-ASM: encoding: [0x93,0x12,0x53,0x60]
sext.h t0, t1 sext.h t0, t1
# CHECK-ASM-AND-OBJ: zext.h t0, t1
# CHECK-ASM: encoding: [0xb3,0x42,0x03,0x08]
zext.h t0, t1
# CHECK-ASM-AND-OBJ: min t0, t1, t2 # CHECK-ASM-AND-OBJ: min t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a] # CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
min t0, t1, t2 min t0, t1, t2
# CHECK-ASM-AND-OBJ: minu t0, t1, t2 # CHECK-ASM-AND-OBJ: minu t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a] # CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
minu t0, t1, t2 minu t0, t1, t2
# CHECK-ASM-AND-OBJ: max t0, t1, t2 # CHECK-ASM-AND-OBJ: max t0, t1, t2
Show All 13 Lines
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x40] # CHECK-ASM: encoding: [0xb3,0x42,0x73,0x40]
xnor t0, t1, t2 xnor t0, t1, t2
# CHECK-ASM-AND-OBJ: rol t0, t1, t2 # CHECK-ASM-AND-OBJ: rol t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x60] # CHECK-ASM: encoding: [0xb3,0x12,0x73,0x60]
rol t0, t1, t2 rol t0, t1, t2
# CHECK-ASM-AND-OBJ: ror t0, t1, t2 # CHECK-ASM-AND-OBJ: ror t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x60] # CHECK-ASM: encoding: [0xb3,0x52,0x73,0x60]
ror t0, t1, t2 ror t0, t1, t2
# CHECK-ASM-AND-OBJ: rori t0, t1, 31
# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61]
rori t0, t1, 31
# CHECK-ASM-AND-OBJ: rori t0, t1, 0
# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60]
rori t0, t1, 0
# CHECK-ASM-AND-OBJ: orc.b t0, t1 # CHECK-ASM-AND-OBJ: orc.b t0, t1
# CHECK-ASM: encoding: [0x93,0x52,0x73,0x28] # CHECK-ASM: encoding: [0x93,0x52,0x73,0x28]
orc.b t0, t1 orc.b t0, t1

llvm/test/MC/RISCV/rv64zbb-valid.s

# With Bitmanip base extension: # With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbb -riscv-no-aliases -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+zbb -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbb < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbb < %s \
# RUN: | llvm-objdump --mattr=+zbb -M no-aliases -d -r - \ # RUN: | llvm-objdump --mattr=+zbb -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: clz t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
clz t0, t1
# CHECK-ASM-AND-OBJ: ctz t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x13,0x60]
ctz t0, t1
# CHECK-ASM-AND-OBJ: cpop t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x23,0x60]
cpop t0, t1
# CHECK-ASM-AND-OBJ: min t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
min t0, t1, t2
# CHECK-ASM-AND-OBJ: minu t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
minu t0, t1, t2
# CHECK-ASM-AND-OBJ: max t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
max t0, t1, t2
# CHECK-ASM-AND-OBJ: sext.b t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x43,0x60]
sext.b t0, t1
# CHECK-ASM-AND-OBJ: sext.h t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60]
sext.h t0, t1
# CHECK-ASM-AND-OBJ: zext.h t0, t1 # CHECK-ASM-AND-OBJ: zext.h t0, t1
# CHECK-ASM: encoding: [0xbb,0x42,0x03,0x08] # CHECK-ASM: encoding: [0xbb,0x42,0x03,0x08]
zext.h t0, t1 zext.h t0, t1
# CHECK-ASM-AND-OBJ: rori t0, t1, 63
# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x63]
rori t0, t1, 63
asbUnsubmitted
Done
ReplyInline Actions

It would make sense to test the wider shift amount supported on RV64 here

asb: It would make sense to test the wider shift amount supported on RV64 here
# CHECK-ASM-AND-OBJ: rori t0, t1, 0
# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60]
rori t0, t1, 0
# CHECK-ASM-AND-OBJ: rev8 t0, t1
# CHECK-ASM: encoding: [0x93,0x52,0x83,0x6b]
rev8 t0, t1
# CHECK-ASM-AND-OBJ: clzw t0, t1 # CHECK-ASM-AND-OBJ: clzw t0, t1
# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x60] # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x60]
clzw t0, t1 clzw t0, t1
# CHECK-ASM-AND-OBJ: ctzw t0, t1 # CHECK-ASM-AND-OBJ: ctzw t0, t1
# CHECK-ASM: encoding: [0x9b,0x12,0x13,0x60] # CHECK-ASM: encoding: [0x9b,0x12,0x13,0x60]
ctzw t0, t1 ctzw t0, t1
# CHECK-ASM-AND-OBJ: cpopw t0, t1 # CHECK-ASM-AND-OBJ: cpopw t0, t1
Show All 17 Lines
# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x60] # CHECK-ASM: encoding: [0xbb,0x52,0x73,0x60]
rorw t0, t1, t2 rorw t0, t1, t2
# CHECK-ASM-AND-OBJ: roriw t0, t1, 31 # CHECK-ASM-AND-OBJ: roriw t0, t1, 31
# CHECK-ASM: encoding: [0x9b,0x52,0xf3,0x61] # CHECK-ASM: encoding: [0x9b,0x52,0xf3,0x61]
roriw t0, t1, 31 roriw t0, t1, 31
# CHECK-ASM-AND-OBJ: roriw t0, t1, 0 # CHECK-ASM-AND-OBJ: roriw t0, t1, 0
# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x60] # CHECK-ASM: encoding: [0x9b,0x52,0x03,0x60]
roriw t0, t1, 0 roriw t0, t1, 0
# CHECK-ASM-AND-OBJ: rev8 t0, t1
# CHECK-ASM: encoding: [0x93,0x52,0x83,0x6b]
rev8 t0, t1