PowerPC/SPE: Add phony registers for high halves of SPE SuperRegs

[long5hot]

Summary

The intent of this patch is to make upper halves of SPE SuperRegs(s0,..,s31)
as artificial regs, similar to how X86 has done it.
And emit store /reload instructions for the required halves.

PR : https://github.com/llvm/llvm-project/issues/57307

[jhibbits]

I love the goal of this, but it looks incomplete. I only noted on one, but it's probably the same for the other tests, that the change will end up clobbering the top half of registers without saving and restoring them.

llvm/test/CodeGen/PowerPC/fp-strict.ll

1612

This is wrong, because below it's evmergeloing into these registers, which clobbers the top half.

[jhibbits]

Looks good to me, thanks!

[long5hot]

In D152437#4433280, @jhibbits wrote:

Looks good to me, thanks!

@jhibbits Can you please help to commit the changes??

[long5hot]

In D152437#4434132, @long5hot wrote:

In D152437#4433280, @jhibbits wrote:

Looks good to me, thanks!

@jhibbits Can you please help to commit the changes??

Name : Kishan Parmar
E-mail : [e-mail]

[DavidSpickett]

https://github.com/llvm/llvm-project/commit/c42f0a6e6476971974cb3f52c1138dbd8f9cca1f

The CI was failing because part of this wasn't clang-format-ed, but we don't signal that well so I don't blame you for missing it. See https://llvm.org/docs/Contributing.html#how-to-submit-a-patch for how to run it locally in future. For now I just ran it for you and updated the committed version.

Thanks for your contribution! If you are going to do more, consider getting commit access: https://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access

[arsenm]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

2333

This looks like you're working around inaccurate CSR regmasks. You should try adjusting those instead

2338

Don't use reference to MCPhysReg

[kosarev]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

2348–2349

Doesn't this invalidate the (implicit) iterators the for () loop above uses? Can we just do CSI[Idx] = CalleeSavedInfo(Lower); instead?

This seems to fail on CodeGen/PowerPC/spe.ll on builds with libc++'s consistency checks enabled, https://github.com/llvm/llvm-project/issues/68594.

******************** TEST 'LLVM :: CodeGen/PowerPC/spe.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /home/kosarev/labs/llvm-project/build/debug+expensive_checks/bin/llc -verify-machineinstrs < /home/kosarev/labs/llvm-project/llvm/test/CodeGen/PowerPC/spe.ll -mtriple=powerpc-unknown-linux-gnu           -mattr=+spe | /home/kosarev/labs/llvm-project/build/debug+expensive_checks/bin/FileCheck /home/kosarev/labs/llvm-project/llvm/test/CodeGen/PowerPC/spe.ll -check-prefixes=CHECK,SPE
+ /home/kosarev/labs/llvm-project/build/debug+expensive_checks/bin/llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mattr=+spe
+ /home/kosarev/labs/llvm-project/build/debug+expensive_checks/bin/FileCheck /home/kosarev/labs/llvm-project/llvm/test/CodeGen/PowerPC/spe.ll -check-prefixes=CHECK,SPE
/usr/include/c++/11/debug/safe_iterator.h:330:
In function:
    gnu_debug::_Safe_iterator<_Iterator, _Sequence, _Category>& 
    gnu_debug::_Safe_iterator<_Iterator, _Sequence, _Category>::operator++() 
    [with _Iterator = gnu_cxx::normal_iterator<llvm::CalleeSavedInfo*, std::
    vector<llvm::CalleeSavedInfo, std::allocator<llvm::CalleeSavedInfo> > >; 
    _Sequence = std::debug::vector<llvm::CalleeSavedInfo>; _Category = 
    std::forward_iterator_tag]

Error: attempt to increment a singular iterator.

Objects involved in the operation:
    iterator "this" @ 0x7ffec8d10870 {
      state = singular;
      references sequence @ 0x7ffec8d10b80
    }
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.	Program arguments: /home/kosarev/labs/llvm-project/build/debug+expensive_checks/bin/llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mattr=+spe
1.	Running pass 'Function Pass Manager' on module '<stdin>'.
2.	Running pass 'Prologue/Epilogue Insertion & Frame Finalization' on function '@test_fma'
 #0 0x00007f4576a916c8 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /home/kosarev/labs/llvm-project/llvm/lib/Support/Unix/Signals.inc:723:22
 #1 0x00007f4576a91ae4 PrintStackTraceSignalHandler(void*) /home/kosarev/labs/llvm-project/llvm/lib/Support/Unix/Signals.inc:798:1
 #2 0x00007f4576a8ef29 llvm::sys::RunSignalHandlers() /home/kosarev/labs/llvm-project/llvm/lib/Support/Signals.cpp:105:20
 #3 0x00007f4576a90f60 SignalHandler(int) /home/kosarev/labs/llvm-project/llvm/lib/Support/Unix/Signals.inc:413:1
 #4 0x00007f4576316520 (/lib/x86_64-linux-gnu/libc.so.6+0x42520)
 #5 0x00007f457636a9fc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
 #6 0x00007f457636a9fc __pthread_kill_internal ./nptl/pthread_kill.c:78:10
 #7 0x00007f457636a9fc pthread_kill ./nptl/pthread_kill.c:89:10
 #8 0x00007f4576316476 gsignal ./signal/../sysdeps/posix/raise.c:27:6
 #9 0x00007f45762fc7f3 abort ./stdlib/abort.c:81:7
#10 0x00007f45765a11fb std::__throw_bad_exception() (/lib/x86_64-linux-gnu/libstdc++.so.6+0xa51fb)
#11 0x00007f4580e2d6c3 __gnu_debug::_Safe_iterator<__gnu_cxx::__normal_iterator<llvm::CalleeSavedInfo*, std::__cxx1998::vector<llvm::CalleeSavedInfo, std::allocator<llvm::CalleeSavedInfo>>>, std::__debug::vector<llvm::CalleeSavedInfo, std::allocator<llvm::CalleeSavedInfo>>, std::forward_iterator_tag>::operator++() /usr/include/c++/11/debug/safe_iterator.h:333:49
#12 0x00007f4580e2b8da __gnu_debug::_Safe_iterator<__gnu_cxx::__normal_iterator<llvm::CalleeSavedInfo*, std::__cxx1998::vector<llvm::CalleeSavedInfo, std::allocator<llvm::CalleeSavedInfo>>>, std::__debug::vector<llvm::CalleeSavedInfo, std::allocator<llvm::CalleeSavedInfo>>, std::bidirectional_iterator_tag>::operator++() /usr/include/c++/11/debug/safe_iterator.h:588:10
#13 0x00007f4580e29b7e __gnu_debug::_Safe_iterator<__gnu_cxx::__normal_iterator<llvm::CalleeSavedInfo*, std::__cxx1998::vector<llvm::CalleeSavedInfo, std::allocator<llvm::CalleeSavedInfo>>>, std::__debug::vector<llvm::CalleeSavedInfo, std::allocator<llvm::CalleeSavedInfo>>, std::random_access_iterator_tag>::operator++() /usr/include/c++/11/debug/safe_iterator.h:743:10
#14 0x00007f4580e240d9 llvm::PPCFrameLowering::assignCalleeSavedSpillSlots(llvm::MachineFunction&, llvm::TargetRegisterInfo const*, std::__debug::vector<llvm::CalleeSavedInfo, std::allocator<llvm::CalleeSavedInfo>>&) const /home/kosarev/labs/llvm-project/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp:2338:32
#15 0x00007f4580e2751c llvm::TargetFrameLowering::assignCalleeSavedSpillSlots(llvm::MachineFunction&, llvm::TargetRegisterInfo const*, std::__debug::vector<llvm::CalleeSavedInfo, std::allocator<llvm::CalleeSavedInfo>>&, unsigned int&, unsigned int&) const /home/kosarev/labs/llvm-project/llvm/include/llvm/CodeGen/TargetFrameLowering.h:164:3
#16 0x00007f457ae1d03a assignCalleeSavedSpillSlots(llvm::MachineFunction&, llvm::BitVector const&, unsigned int&, unsigned int&) /home/kosarev/labs/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp:474:7
#17 0x00007f457ae1e434 (anonymous namespace)::PEI::spillCalleeSavedRegs(llvm::MachineFunction&) /home/kosarev/labs/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp:686:24
#18 0x00007f457ae1bc5c (anonymous namespace)::PEI::runOnMachineFunction(llvm::MachineFunction&) /home/kosarev/labs/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp:251:43
#19 0x00007f457ab2553c llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /home/kosarev/labs/llvm-project/llvm/lib/CodeGen/MachineFunctionPass.cpp:93:33
#20 0x00007f45771dd0e6 llvm::FPPassManager::runOnFunction(llvm::Function&) /home/kosarev/labs/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1435:20
#21 0x00007f45771dd496 llvm::FPPassManager::runOnModule(llvm::Module&) /home/kosarev/labs/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1481:13
#22 0x00007f45771dd917 (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) /home/kosarev/labs/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1550:20
#23 0x00007f45771d836e llvm::legacy::PassManagerImpl::run(llvm::Module&) /home/kosarev/labs/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:535:13
#24 0x00007f45771de261 llvm::legacy::PassManager::run(llvm::Module&) /home/kosarev/labs/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1678:1
#25 0x0000555a168b68c8 compileModule(char**, llvm::LLVMContext&) /home/kosarev/labs/llvm-project/llvm/tools/llc/llc.cpp:757:66
#26 0x0000555a168b4117 main /home/kosarev/labs/llvm-project/llvm/tools/llc/llc.cpp:416:35
#27 0x00007f45762fdd90 __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:58:16
#28 0x00007f45762fde40 call_init ./csu/../csu/libc-start.c:128:20
#29 0x00007f45762fde40 __libc_start_main ./csu/../csu/libc-start.c:379:5
#30 0x0000555a168b2d65 _start (/home/kosarev/labs/llvm-project/build/debug+expensive_checks/bin/llc+0xfd65)

[DavidSpickett]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

2348–2349

https://github.com/llvm/llvm-project/pull/73940 to fix this.

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

 // code can handle them by assigning a FrameIdx to a stack slot.
 bool PPCFrameLowering::assignCalleeSavedSpillSlots(
     MachineFunction &MF, const TargetRegisterInfo *TRI,
     std::vector<CalleeSavedInfo> &CSI) const {
 
   if (CSI.empty())
     return true; // Early exit if no callee saved registers are modified!
 
+  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
+  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+
+  if (Subtarget.hasSPE()) {
+    // In case of SPE we only have SuperRegs and CRs
+    // in our CalleSaveInfo vector.
+
+    unsigned Idx = 0;
+    for (auto &CalleeSaveReg : CSI) {
+      const MCPhysReg &Reg = CalleeSaveReg.getReg();
+      const MCPhysReg &Lower = RegInfo->getSubReg(Reg, 1);
+      const MCPhysReg &Higher = RegInfo->getSubReg(Reg, 2);
+
+      // Check only for SuperRegs.
+      if (Lower) {
+        if (MRI.isPhysRegModified(Higher)) {
+          Idx++;
+          continue;
+        } else {
+          // Replace Reg if only lower-32 bits modified
+          CSI.erase(CSI.begin() + Idx);
+          CSI.insert(CSI.begin() + Idx, CalleeSavedInfo(Lower));
+        }
+      }
+      Idx++;
+    }
+  }
+
   // Early exit if cannot spill gprs to volatile vector registers.
   MachineFrameInfo &MFI = MF.getFrameInfo();
   if (!EnablePEVectorSpills || MFI.hasCalls() || !Subtarget.hasP9Vector())
     return false;
 
   // Build a BitVector of VSRs that can be used for spilling GPRs.
   BitVector BVAllocatable = TRI->getAllocatableSet(MF);
   BitVector BVCalleeSaved(TRI->getNumRegs());
-  const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
-  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
   for (unsigned i = 0; CSRegs[i]; ++i)
     BVCalleeSaved.set(CSRegs[i]);
 
   for (unsigned Reg : BVAllocatable.set_bits()) {
     // Set to 0 if the register is not a volatile VSX register, or if it is
     // used in the function.
     if (BVCalleeSaved[Reg] || !PPC::VSRCRegClass.contains(Reg) ||
-        MF.getRegInfo().isPhysRegUsed(Reg))
+        MRI.isPhysRegUsed(Reg))
       BVAllocatable.reset(Reg);
   }
 
   bool AllSpilledToReg = true;
   unsigned LastVSRUsedForSpill = 0;
   for (auto &CS : CSI) {
     if (BVAllocatable.none())
       return false;

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

 //===----------------------------------------------------------------------===//
 
 let Namespace = "PPC" in {
 def sub_lt : SubRegIndex<1>;
 def sub_gt : SubRegIndex<1, 1>;
 def sub_eq : SubRegIndex<1, 2>;
 def sub_un : SubRegIndex<1, 3>;
 def sub_32 : SubRegIndex<32>;
+def sub_32_hi_phony : SubRegIndex<32,32>;
 def sub_64 : SubRegIndex<64>;
 def sub_vsx0 : SubRegIndex<128>;
 def sub_vsx1 : SubRegIndex<128, 128>;
 def sub_gp8_x0 : SubRegIndex<64>;
 def sub_gp8_x1 : SubRegIndex<64, 64>;
 def sub_fp0 : SubRegIndex<64>;
 def sub_fp1 : SubRegIndex<64, 64>;
 }

 
 // GP8 - One of the 32 64-bit general-purpose registers
 class GP8<GPR SubReg, string n> : PPCReg<n> {
   let HWEncoding = SubReg.HWEncoding;
   let SubRegs = [SubReg];
   let SubRegIndices = [sub_32];
 }
 
-// SPE - One of the 32 64-bit general-purpose registers (SPE)
-class SPE<GPR SubReg, string n> : PPCReg<n> {
-  let HWEncoding = SubReg.HWEncoding;
-  let SubRegs = [SubReg];
-  let SubRegIndices = [sub_32];
+class SPE<string n, bits<5> Enc, list<Register> subregs = []> : PPCReg<n> {
+  let HWEncoding{4-0} = Enc;
+  let SubRegs = subregs;
+  let SubRegIndices = [sub_32, sub_32_hi_phony];
+  let CoveredBySubRegs = 1;
 }
-
 // SPR - One of the 32-bit special-purpose registers
 class SPR<bits<10> num, string n> : PPCReg<n> {
   let HWEncoding{9-0} = num;
 }
 
 // FPR - One of the 32 64-bit floating-point registers
 class FPR<bits<5> num, string n> : PPCReg<n> {
   let HWEncoding{4-0} = num;
class GP8Pair<string n, bits<5> EvenIndex> : PPCReg<n> {
   let SubRegIndices = [sub_gp8_x0, sub_gp8_x1];
 }
 
 // General-purpose registers
 foreach Index = 0-31 in {
   def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>;
 }
 
+let isArtificial = 1 in {
+  foreach Index = 0-31 in {
+    def H#Index : GPR<-1,"">;
+  }
+}
+
 // 64-bit General-purpose registers
 foreach Index = 0-31 in {
   def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>,
                     DwarfRegNum<[Index, -2]>;
 }
 
 // SPE registers
 foreach Index = 0-31 in {
-  def S#Index : SPE<!cast<GPR>("R"#Index), "r"#Index>,
+  def S#Index : SPE<"r"#Index, Index, [!cast<GPR>("R"#Index), !cast<GPR>("H"#Index)]>,
                     DwarfRegNum<[!add(Index, 1200), !add(Index, 1200)]>;
+
 }
 
+
 // Floating-point registers
 foreach Index = 0-31 in {
   def F#Index : FPR<Index, "f"#Index>,
                 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
 }
 
 // Floating-point pair registers
 foreach Index = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 } in {

 // This is not allocated as a normal register; it appears only in
 // Uses and Defs.  The ABI says it needs to be preserved by a function,
 // but this is not achieved by saving and restoring it as with
 // most registers, it has to be done in code; to make this work all the
 // return and call instructions are described as Uses of RM, so instructions
 // that do nothing but change RM will not get deleted.
 def RM: PPCReg<"**ROUNDING MODE**">;
 
+let isAllocatable = 0 in
+def GPRC32 : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "H%u", 2, 12),
+                                                      (sequence "H%u", 30, 13),
+                                                      H31, H0, H1)>;
+
 /// Register classes
 // Allocate volatiles first
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
 def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),
                                                     (sequence "R%u", 30, 13),
                                                     R31, R0, R1, FP, BP)> {
   // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
   // put it at the end of the list.

llvm/test/CodeGen/PowerPC/fma-assoc.ll

 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
 ; CHECK-SPE-NEXT:    efdmul 4, 7, 9
 ; CHECK-SPE-NEXT:    efdmul 3, 3, 5
 ; CHECK-SPE-NEXT:    evldd 5, 8(1)
 ; CHECK-SPE-NEXT:    efdadd 3, 3, 4
 ; CHECK-SPE-NEXT:    efdadd 4, 3, 5
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul double %A, %B         ; <double> [#uses=1]
   %G = fmul double %C, %D         ; <double> [#uses=1]
   %H = fadd double %F, %G         ; <double> [#uses=1]
   %I = fadd double %H, %E         ; <double> [#uses=1]
   ret double %I
 }

 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
 ; CHECK-SPE-NEXT:    efdmul 4, 7, 9
 ; CHECK-SPE-NEXT:    efdmul 3, 3, 5
 ; CHECK-SPE-NEXT:    evldd 5, 8(1)
 ; CHECK-SPE-NEXT:    efdadd 3, 3, 4
 ; CHECK-SPE-NEXT:    efdadd 4, 5, 3
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul double %A, %B         ; <double> [#uses=1]
   %G = fmul double %C, %D         ; <double> [#uses=1]
   %H = fadd double %F, %G         ; <double> [#uses=1]
   %I = fadd double %E, %H         ; <double> [#uses=1]
   ret double %I
 }

 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
 ; CHECK-SPE-NEXT:    efdmul 4, 7, 9
 ; CHECK-SPE-NEXT:    efdmul 3, 3, 5
 ; CHECK-SPE-NEXT:    evldd 5, 8(1)
 ; CHECK-SPE-NEXT:    efdadd 3, 3, 4
 ; CHECK-SPE-NEXT:    efdsub 4, 3, 5
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul double %A, %B         ; <double> [#uses=1]
   %G = fmul double %C, %D         ; <double> [#uses=1]
   %H = fadd double %F, %G         ; <double> [#uses=1]
   %I = fsub double %H, %E         ; <double> [#uses=1]
   ret double %I
 }

 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
 ; CHECK-SPE-NEXT:    efdmul 4, 7, 9
 ; CHECK-SPE-NEXT:    efdmul 3, 3, 5
 ; CHECK-SPE-NEXT:    evldd 5, 8(1)
 ; CHECK-SPE-NEXT:    efdadd 3, 3, 4
 ; CHECK-SPE-NEXT:    efdsub 4, 5, 3
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul double %A, %B         ; <double> [#uses=1]
   %G = fmul double %C, %D         ; <double> [#uses=1]
   %H = fadd double %F, %G         ; <double> [#uses=1]
   %I = fsub double %E, %H         ; <double> [#uses=1]
   ret double %I
 }

 ; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
 ; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    efdmul 5, 5, 7
 ; CHECK-SPE-NEXT:    efdadd 3, 5, 3
 ; CHECK-SPE-NEXT:    efdadd 4, 3, 4
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul float %A, %B         ; <float> [#uses=1]
   %G = fpext float %F to double   ; <double> [#uses=1]
   %H = fmul double %C, %D         ; <double> [#uses=1]
   %I = fadd double %H, %G         ; <double> [#uses=1]
   %J = fadd double %I, %E         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE:       # %bb.0:
 ; CHECK-SPE-NEXT:    efsmul 3, 3, 4
 ; CHECK-SPE-NEXT:    efsmul 4, 5, 6
 ; CHECK-SPE-NEXT:    efsadd 3, 3, 4
 ; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    efdadd 4, 3, 4
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  float %D, double %E) {
   %F = fmul float %A, %B         ; <float> [#uses=1]
   %G = fmul float %C, %D         ; <float> [#uses=1]
   %H = fadd float %F, %G         ; <float> [#uses=1]
   %I = fpext float %H to double   ; <double> [#uses=1]
   %J = fadd double %I, %E         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
 ; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    efdmul 5, 5, 7
 ; CHECK-SPE-NEXT:    efdadd 3, 5, 3
 ; CHECK-SPE-NEXT:    efdadd 4, 4, 3
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul float %A, %B          ; <float> [#uses=1]
   %G = fpext float %F to double   ; <double> [#uses=1]
   %H = fmul double %C, %D         ; <double> [#uses=1]
   %I = fadd double %H, %G         ; <double> [#uses=1]
   %J = fadd double %E, %I         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE:       # %bb.0:
 ; CHECK-SPE-NEXT:    efsmul 3, 3, 4
 ; CHECK-SPE-NEXT:    efsmul 4, 5, 6
 ; CHECK-SPE-NEXT:    efsadd 3, 3, 4
 ; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    efdadd 4, 4, 3
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  float %D, double %E) {
   %F = fmul float %A, %B          ; <float> [#uses=1]
   %G = fmul float %C, %D          ; <float> [#uses=1]
   %H = fadd float %F, %G          ; <float> [#uses=1]
   %I = fpext float %H to double   ; <double> [#uses=1]
   %J = fadd double %E, %I         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
 ; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    efdmul 5, 5, 7
 ; CHECK-SPE-NEXT:    efdadd 3, 5, 3
 ; CHECK-SPE-NEXT:    efdsub 4, 3, 4
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul float %A, %B          ; <float> [#uses=1]
   %G = fpext float %F to double   ; <double> [#uses=1]
   %H = fmul double %C, %D         ; <double> [#uses=1]
   %I = fadd double %H, %G         ; <double> [#uses=1]
   %J = fsub double %I, %E         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE:       # %bb.0:
 ; CHECK-SPE-NEXT:    efsmul 3, 3, 4
 ; CHECK-SPE-NEXT:    efsmul 4, 5, 6
 ; CHECK-SPE-NEXT:    efsadd 3, 3, 4
 ; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    efdsub 4, 3, 4
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  float %D, double %E) {
   %F = fmul float %A, %B          ; <float> [#uses=1]
   %G = fmul float %C, %D          ; <float> [#uses=1]
   %H = fadd float %F, %G          ; <float> [#uses=1]
   %I = fpext float %H to double   ; <double> [#uses=1]
   %J = fsub double %I, %E         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
 ; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    efdmul 5, 5, 7
 ; CHECK-SPE-NEXT:    efdadd 3, 5, 3
 ; CHECK-SPE-NEXT:    efdsub 4, 4, 3
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul float %A, %B          ; <float> [#uses=1]
   %G = fpext float %F to double   ; <double> [#uses=1]
   %H = fmul double %C, %D         ; <double> [#uses=1]
   %I = fadd double %H, %G         ; <double> [#uses=1]
   %J = fsub double %E, %I         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE:       # %bb.0:
 ; CHECK-SPE-NEXT:    efsmul 3, 3, 4
 ; CHECK-SPE-NEXT:    efsmul 4, 5, 6
 ; CHECK-SPE-NEXT:    efsadd 3, 3, 4
 ; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    efdsub 4, 4, 3
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  float %D, double %E) {
   %F = fmul float %A, %B          ; <float> [#uses=1]
   %G = fmul float %C, %D          ; <float> [#uses=1]
   %H = fadd float %F, %G          ; <float> [#uses=1]
   %I = fpext float %H to double   ; <double> [#uses=1]
   %J = fsub double %E, %I         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
 ; CHECK-SPE-NEXT:    efdmul 4, 7, 9
 ; CHECK-SPE-NEXT:    efdmul 3, 3, 5
 ; CHECK-SPE-NEXT:    evldd 5, 8(1)
 ; CHECK-SPE-NEXT:    efdadd 3, 3, 4
 ; CHECK-SPE-NEXT:    efdadd 4, 3, 5
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
   %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
   %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
   %I = fadd reassoc double %H, %E         ; <double> [#uses=1]
   ret double %I
 }

 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
 ; CHECK-SPE-NEXT:    efdmul 4, 7, 9
 ; CHECK-SPE-NEXT:    efdmul 3, 3, 5
 ; CHECK-SPE-NEXT:    evldd 5, 8(1)
 ; CHECK-SPE-NEXT:    efdadd 3, 3, 4
 ; CHECK-SPE-NEXT:    efdadd 4, 5, 3
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
   %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
   %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
   %I = fadd reassoc double %E, %H         ; <double> [#uses=1]
   ret double %I
 }

 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
 ; CHECK-SPE-NEXT:    efdmul 4, 7, 9
 ; CHECK-SPE-NEXT:    efdmul 3, 3, 5
 ; CHECK-SPE-NEXT:    evldd 5, 8(1)
 ; CHECK-SPE-NEXT:    efdadd 3, 3, 4
 ; CHECK-SPE-NEXT:    efdsub 4, 3, 5
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
   %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
   %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
   %I = fsub reassoc double %H, %E         ; <double> [#uses=1]
   ret double %I
 }

 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
 ; CHECK-SPE-NEXT:    efdmul 4, 7, 9
 ; CHECK-SPE-NEXT:    efdmul 3, 3, 5
 ; CHECK-SPE-NEXT:    evldd 5, 8(1)
 ; CHECK-SPE-NEXT:    efdadd 3, 3, 4
 ; CHECK-SPE-NEXT:    efdsub 4, 3, 5
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul contract reassoc double %A, %B         ; <double> [#uses=1]
   %G = fmul contract reassoc double %C, %D         ; <double> [#uses=1]
   %H = fadd contract reassoc double %F, %G         ; <double> [#uses=1]
   %I = fsub contract reassoc double %H, %E         ; <double> [#uses=1]
   ret double %I
 }

 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
 ; CHECK-SPE-NEXT:    efdmul 4, 7, 9
 ; CHECK-SPE-NEXT:    efdmul 3, 3, 5
 ; CHECK-SPE-NEXT:    evldd 5, 8(1)
 ; CHECK-SPE-NEXT:    efdadd 3, 3, 4
 ; CHECK-SPE-NEXT:    efdsub 4, 5, 3
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
   %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
   %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
   %I = fsub reassoc double %E, %H         ; <double> [#uses=1]
   ret double %I
 }

 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    evmergelo 3, 3, 4
 ; CHECK-SPE-NEXT:    efdmul 4, 7, 9
 ; CHECK-SPE-NEXT:    efdmul 3, 3, 5
 ; CHECK-SPE-NEXT:    evldd 5, 8(1)
 ; CHECK-SPE-NEXT:    efdadd 3, 3, 4
 ; CHECK-SPE-NEXT:    efdsub 4, 5, 3
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
   %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
   %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
   %I = fsub reassoc nsz double %E, %H         ; <double> [#uses=1]
   ret double %I
 }

 ; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
 ; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    efdmul 5, 5, 7
 ; CHECK-SPE-NEXT:    efdadd 3, 5, 3
 ; CHECK-SPE-NEXT:    efdadd 4, 3, 4
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul reassoc float %A, %B         ; <float> [#uses=1]
   %G = fpext float %F to double   ; <double> [#uses=1]
   %H = fmul reassoc double %C, %D         ; <double> [#uses=1]
   %I = fadd reassoc double %H, %G         ; <double> [#uses=1]
   %J = fadd reassoc double %I, %E         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE:       # %bb.0:
 ; CHECK-SPE-NEXT:    efsmul 3, 3, 4
 ; CHECK-SPE-NEXT:    efsmul 4, 5, 6
 ; CHECK-SPE-NEXT:    efsadd 3, 3, 4
 ; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    efdadd 4, 3, 4
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  float %D, double %E) {
   %F = fmul reassoc float %A, %B         ; <float> [#uses=1]
   %G = fmul reassoc float %C, %D         ; <float> [#uses=1]
   %H = fadd reassoc float %F, %G         ; <float> [#uses=1]
   %I = fpext float %H to double   ; <double> [#uses=1]
   %J = fadd reassoc double %I, %E         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
 ; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    efdmul 5, 5, 7
 ; CHECK-SPE-NEXT:    efdadd 3, 5, 3
 ; CHECK-SPE-NEXT:    efdadd 4, 4, 3
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul reassoc float %A, %B          ; <float> [#uses=1]
   %G = fpext float %F to double   ; <double> [#uses=1]
   %H = fmul reassoc double %C, %D         ; <double> [#uses=1]
   %I = fadd reassoc double %H, %G         ; <double> [#uses=1]
   %J = fadd reassoc double %E, %I         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE:       # %bb.0:
 ; CHECK-SPE-NEXT:    efsmul 3, 3, 4
 ; CHECK-SPE-NEXT:    efsmul 4, 5, 6
 ; CHECK-SPE-NEXT:    efsadd 3, 3, 4
 ; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    efdadd 4, 4, 3
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  float %D, double %E) {
   %F = fmul reassoc float %A, %B          ; <float> [#uses=1]
   %G = fmul reassoc float %C, %D          ; <float> [#uses=1]
   %H = fadd reassoc float %F, %G          ; <float> [#uses=1]
   %I = fpext float %H to double   ; <double> [#uses=1]
   %J = fadd reassoc double %E, %I         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
 ; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    efdmul 5, 5, 7
 ; CHECK-SPE-NEXT:    efdadd 3, 5, 3
 ; CHECK-SPE-NEXT:    efdsub 4, 3, 4
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul reassoc float %A, %B          ; <float> [#uses=1]
   %G = fpext float %F to double   ; <double> [#uses=1]
   %H = fmul reassoc double %C, %D         ; <double> [#uses=1]
   %I = fadd reassoc double %H, %G         ; <double> [#uses=1]
   %J = fsub reassoc double %I, %E         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE:       # %bb.0:
 ; CHECK-SPE-NEXT:    efsmul 3, 3, 4
 ; CHECK-SPE-NEXT:    efsmul 4, 5, 6
 ; CHECK-SPE-NEXT:    efsadd 3, 3, 4
 ; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    efdsub 4, 3, 4
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  float %D, double %E) {
   %F = fmul reassoc float %A, %B          ; <float> [#uses=1]
   %G = fmul reassoc float %C, %D          ; <float> [#uses=1]
   %H = fadd reassoc float %F, %G          ; <float> [#uses=1]
   %I = fpext float %H to double   ; <double> [#uses=1]
   %J = fsub reassoc double %I, %E         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
 ; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    efdmul 5, 5, 7
 ; CHECK-SPE-NEXT:    efdadd 3, 5, 3
 ; CHECK-SPE-NEXT:    efdsub 4, 4, 3
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul reassoc float %A, %B          ; <float> [#uses=1]
   %G = fpext float %F to double   ; <double> [#uses=1]
   %H = fmul reassoc double %C, %D         ; <double> [#uses=1]
   %I = fadd reassoc double %H, %G         ; <double> [#uses=1]
   %J = fsub reassoc double %E, %I         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE-NEXT:    evmergelo 4, 9, 10
 ; CHECK-SPE-NEXT:    evmergelo 7, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    evmergelo 5, 5, 6
 ; CHECK-SPE-NEXT:    efdmul 5, 5, 7
 ; CHECK-SPE-NEXT:    efdadd 3, 5, 3
 ; CHECK-SPE-NEXT:    efdsub 4, 4, 3
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                              double %D, double %E) {
   %F = fmul reassoc float %A, %B
   %G = fpext float %F to double
   %H = fmul reassoc double %C, %D
   %I = fadd reassoc nsz double %H, %G
   %J = fsub reassoc nsz double %E, %I
   ret double %J

 ; CHECK-SPE:       # %bb.0:
 ; CHECK-SPE-NEXT:    efsmul 3, 3, 4
 ; CHECK-SPE-NEXT:    efsmul 4, 5, 6
 ; CHECK-SPE-NEXT:    efsadd 3, 3, 4
 ; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    efdsub 4, 4, 3
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                  float %D, double %E) {
   %F = fmul reassoc float %A, %B          ; <float> [#uses=1]
   %G = fmul reassoc float %C, %D          ; <float> [#uses=1]
   %H = fadd reassoc float %F, %G          ; <float> [#uses=1]
   %I = fpext float %H to double   ; <double> [#uses=1]
   %J = fsub reassoc double %E, %I         ; <double> [#uses=1]
   ret double %J

 ; CHECK-SPE:       # %bb.0:
 ; CHECK-SPE-NEXT:    efsmul 3, 3, 4
 ; CHECK-SPE-NEXT:    efsmul 4, 5, 6
 ; CHECK-SPE-NEXT:    efsadd 3, 3, 4
 ; CHECK-SPE-NEXT:    evmergelo 4, 7, 8
 ; CHECK-SPE-NEXT:    efdcfs 3, 3
 ; CHECK-SPE-NEXT:    efdsub 4, 4, 3
 ; CHECK-SPE-NEXT:    evmergehi 3, 4, 4
-; CHECK-SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; CHECK-SPE-NEXT:    blr
                                           float %D, double %E) {
   %F = fmul reassoc float %A, %B
   %G = fmul reassoc float %C, %D
   %H = fadd reassoc nsz float %F, %G
   %I = fpext float %H to double
   %J = fsub reassoc nsz double %E, %I
   ret double %J
 }

llvm/test/CodeGen/PowerPC/fp-strict-conv-spe.ll

 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    mflr r0
 ; SPE-NEXT:    stwu r1, -16(r1)
 ; SPE-NEXT:    stw r0, 20(r1)
 ; SPE-NEXT:    .cfi_def_cfa_offset 16
 ; SPE-NEXT:    .cfi_offset lr, 4
 ; SPE-NEXT:    evmergelo r4, r3, r4
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    bl __fixdfdi
 ; SPE-NEXT:    lwz r0, 20(r1)
 ; SPE-NEXT:    addi r1, r1, 16
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
 entry:
   %conv = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %m, metadata !"fpexcept.strict") #0
   ret i64 %conv
 }
 
 define i64 @d_to_u64(double %m) #0 {
 ; SPE-LABEL: d_to_u64:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    mflr r0
 ; SPE-NEXT:    stwu r1, -16(r1)
 ; SPE-NEXT:    stw r0, 20(r1)
 ; SPE-NEXT:    .cfi_def_cfa_offset 16
 ; SPE-NEXT:    .cfi_offset lr, 4
 ; SPE-NEXT:    evmergelo r4, r3, r4
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    bl __fixunsdfdi
 ; SPE-NEXT:    lwz r0, 20(r1)
 ; SPE-NEXT:    addi r1, r1, 16
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
 entry:
   %conv = call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %m, metadata !"fpexcept.strict") #0
   ret i64 %conv
entry:
   ret i32 %conv
 }
 
 define double @i32_to_d(i32 signext %m) #0 {
 ; SPE-LABEL: i32_to_d:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    efdcfsi r4, r3
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
 entry:
   %conv = tail call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret double %conv
 }
 
 define double @i64_to_d(i64 %m) #0 {
 ; SPE-LABEL: i64_to_d:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    mflr r0
 ; SPE-NEXT:    stwu r1, -16(r1)
 ; SPE-NEXT:    stw r0, 20(r1)
 ; SPE-NEXT:    .cfi_def_cfa_offset 16
 ; SPE-NEXT:    .cfi_offset lr, 4
 ; SPE-NEXT:    bl __floatdidf
 ; SPE-NEXT:    evmergelo r4, r3, r4
 ; SPE-NEXT:    evmergehi r3, r4, r4
 ; SPE-NEXT:    lwz r0, 20(r1)
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
 ; SPE-NEXT:    addi r1, r1, 16
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
 entry:
   %conv = tail call double @llvm.experimental.constrained.sitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret double %conv
 }
 
 define double @u32_to_d(i32 zeroext %m) #0 {
 ; SPE-LABEL: u32_to_d:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    efdcfui r4, r3
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
 entry:
   %conv = tail call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret double %conv
 }
 
 define double @u64_to_d(i64 %m) #0 {
 ; SPE-LABEL: u64_to_d:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    mflr r0
 ; SPE-NEXT:    stwu r1, -16(r1)
 ; SPE-NEXT:    stw r0, 20(r1)
 ; SPE-NEXT:    .cfi_def_cfa_offset 16
 ; SPE-NEXT:    .cfi_offset lr, 4
 ; SPE-NEXT:    bl __floatundidf
 ; SPE-NEXT:    evmergelo r4, r3, r4
 ; SPE-NEXT:    evmergehi r3, r4, r4
 ; SPE-NEXT:    lwz r0, 20(r1)
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
 ; SPE-NEXT:    addi r1, r1, 16
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
 entry:
   %conv = tail call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret double %conv
 }
 

llvm/test/CodeGen/PowerPC/fp-strict.ll

 ; NOVSX-NEXT:    blr
 ;
 ; SPE-LABEL: fadd_f64:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    evmergelo r5, r5, r6
 ; SPE-NEXT:    evmergelo r3, r3, r4
 ; SPE-NEXT:    efdadd r4, r3, r5
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
   %res = call double @llvm.experimental.constrained.fadd.f64(
                         double %f1, double %f2,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   ret double %res
 }
 

 ; NOVSX-NEXT:    blr
 ;
 ; SPE-LABEL: fsub_f64:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    evmergelo r5, r5, r6
 ; SPE-NEXT:    evmergelo r3, r3, r4
 ; SPE-NEXT:    efdsub r4, r3, r5
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
 
   %res = call double @llvm.experimental.constrained.fsub.f64(
                         double %f1, double %f2,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   ret double %res;
 }

 ; NOVSX-NEXT:    blr
 ;
 ; SPE-LABEL: fmul_f64:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    evmergelo r5, r5, r6
 ; SPE-NEXT:    evmergelo r3, r3, r4
 ; SPE-NEXT:    efdmul r4, r3, r5
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
 
   %res = call double @llvm.experimental.constrained.fmul.f64(
                         double %f1, double %f2,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   ret double %res;
 }

 ; NOVSX-NEXT:    blr
 ;
 ; SPE-LABEL: fdiv_f64:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    evmergelo r5, r5, r6
 ; SPE-NEXT:    evmergelo r3, r3, r4
 ; SPE-NEXT:    efddiv r4, r3, r5
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
 
   %res = call double @llvm.experimental.constrained.fdiv.f64(
                         double %f1, double %f2,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   ret double %res;
 }

 ; SPE-LABEL: no_fma_fold:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    evmergelo r7, r7, r8
 ; SPE-NEXT:    evmergelo r5, r5, r6
 ; SPE-NEXT:    evmergelo r3, r3, r4
 ; SPE-NEXT:    efdmul r3, r3, r5
 ; SPE-NEXT:    efdadd r4, r3, r7
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
   %mul = call double @llvm.experimental.constrained.fmul.f64(
                         double %f1, double %f2,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   %add = call double @llvm.experimental.constrained.fadd.f64(
                         double %mul, double %f3,
                         metadata !"round.dynamic",

 ; SPE-NEXT:    .cfi_def_cfa_offset 16
 ; SPE-NEXT:    .cfi_offset lr, 4
 ; SPE-NEXT:    evmergelo r8, r7, r8
 ; SPE-NEXT:    evmergelo r6, r5, r6
 ; SPE-NEXT:    evmergelo r4, r3, r4
 ; SPE-NEXT:    evmergehi r3, r4, r4
 ; SPE-NEXT:    evmergehi r5, r6, r6
 ; SPE-NEXT:    evmergehi r7, r8, r8
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r6 killed $r6 killed $s6
-; SPE-NEXT:    # kill: def $r8 killed $r8 killed $s8
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; SPE-NEXT:    # kill: def $r5 killed $r5 killed $s5
-; SPE-NEXT:    # kill: def $r7 killed $r7 killed $s7
 ; SPE-NEXT:    bl fma
 ; SPE-NEXT:    evmergelo r4, r3, r4
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
 ; SPE-NEXT:    lwz r0, 20(r1)
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    addi r1, r1, 16
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
   %res = call double @llvm.experimental.constrained.fma.f64(
                         double %f0, double %f1, double %f2,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   ret double %res

 ; NOVSX-NEXT:    fmadds f0, f2, f1, f0
 ; NOVSX-NEXT:    stfs f0, -16(r1)
 ; NOVSX-NEXT:    lvx v2, 0, r3
 ; NOVSX-NEXT:    blr
 ;
 ; SPE-LABEL: fmadd_v4f32:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    mflr r0
-; SPE-NEXT:    stwu r1, -96(r1)
-; SPE-NEXT:    stw r0, 100(r1)
-; SPE-NEXT:    .cfi_def_cfa_offset 96
+; SPE-NEXT:    stwu r1, -64(r1)
+; SPE-NEXT:    stw r0, 68(r1)
+; SPE-NEXT:    .cfi_def_cfa_offset 64
 ; SPE-NEXT:    .cfi_offset lr, 4
-; SPE-NEXT:    .cfi_offset r21, -88
-; SPE-NEXT:    .cfi_offset r22, -80
-; SPE-NEXT:    .cfi_offset r23, -72
-; SPE-NEXT:    .cfi_offset r24, -64
-; SPE-NEXT:    .cfi_offset r25, -56
-; SPE-NEXT:    .cfi_offset r26, -48
-; SPE-NEXT:    .cfi_offset r27, -40
-; SPE-NEXT:    .cfi_offset r28, -32
-; SPE-NEXT:    .cfi_offset r29, -24
-; SPE-NEXT:    .cfi_offset r30, -16
-; SPE-NEXT:    evstdd r27, 56(r1) # 8-byte Folded Spill
+; SPE-NEXT:    .cfi_offset r21, -44
+; SPE-NEXT:    .cfi_offset r22, -40
+; SPE-NEXT:    .cfi_offset r23, -36
+; SPE-NEXT:    .cfi_offset r24, -32
+; SPE-NEXT:    .cfi_offset r25, -28
+; SPE-NEXT:    .cfi_offset r26, -24
+; SPE-NEXT:    .cfi_offset r27, -20
+; SPE-NEXT:    .cfi_offset r28, -16
+; SPE-NEXT:    .cfi_offset r29, -12
+; SPE-NEXT:    .cfi_offset r30, -8
+; SPE-NEXT:    stw r27, 44(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r27, r5
-; SPE-NEXT:    lwz r5, 116(r1)
-; SPE-NEXT:    evstdd r25, 40(r1) # 8-byte Folded Spill
+; SPE-NEXT:    lwz r5, 84(r1)
+; SPE-NEXT:    stw r25, 36(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r25, r3
-; SPE-NEXT:    evstdd r26, 48(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r26, 40(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r26, r4
 ; SPE-NEXT:    mr r3, r6
 ; SPE-NEXT:    mr r4, r10
-; SPE-NEXT:    evstdd r21, 8(r1) # 8-byte Folded Spill
-; SPE-NEXT:    evstdd r22, 16(r1) # 8-byte Folded Spill
-; SPE-NEXT:    evstdd r23, 24(r1) # 8-byte Folded Spill
-; SPE-NEXT:    evstdd r24, 32(r1) # 8-byte Folded Spill
-; SPE-NEXT:    evstdd r28, 64(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r21, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT:    stw r22, 24(r1) # 4-byte Folded Spill
+; SPE-NEXT:    stw r23, 28(r1) # 4-byte Folded Spill
+; SPE-NEXT:    stw r24, 32(r1) # 4-byte Folded Spill
+; SPE-NEXT:    stw r28, 48(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r28, r7
-; SPE-NEXT:    evstdd r29, 72(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r29, 52(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r29, r8
-; SPE-NEXT:    evstdd r30, 80(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r30, 56(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r30, r9
-; SPE-NEXT:    lwz r24, 104(r1)
-; SPE-NEXT:    lwz r23, 108(r1)
-; SPE-NEXT:    lwz r22, 112(r1)
+; SPE-NEXT:    lwz r24, 72(r1)
+; SPE-NEXT:    lwz r23, 76(r1)
+; SPE-NEXT:    lwz r22, 80(r1)
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    mr r21, r3
 ; SPE-NEXT:    mr r3, r27
 ; SPE-NEXT:    mr r4, r30
 ; SPE-NEXT:    mr r5, r22
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    mr r30, r3
 ; SPE-NEXT:    mr r3, r26
 ; SPE-NEXT:    mr r4, r29
 ; SPE-NEXT:    mr r5, r23
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    mr r29, r3
 ; SPE-NEXT:    mr r3, r25
 ; SPE-NEXT:    mr r4, r28
 ; SPE-NEXT:    mr r5, r24
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    mr r4, r29
 ; SPE-NEXT:    mr r5, r30
 ; SPE-NEXT:    mr r6, r21
-; SPE-NEXT:    evldd r30, 80(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r29, 72(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r28, 64(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r27, 56(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r26, 48(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r25, 40(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r24, 32(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r23, 24(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r22, 16(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r21, 8(r1) # 8-byte Folded Reload
-; SPE-NEXT:    lwz r0, 100(r1)
-; SPE-NEXT:    addi r1, r1, 96
+; SPE-NEXT:    lwz r30, 56(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r29, 52(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r28, 48(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r27, 44(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r26, 40(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r25, 36(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r24, 32(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r23, 28(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r22, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r21, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r0, 68(r1)
+; SPE-NEXT:    addi r1, r1, 64
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
   %res = call <4 x float> @llvm.experimental.constrained.fma.v4f32(
                         <4 x float> %vf0, <4 x float> %vf1, <4 x float> %vf2,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   ret <4 x float> %res
 }

 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    fmadd f2, f2, f4, f6
 ; NOVSX-NEXT:    fmadd f1, f1, f3, f5
 ; NOVSX-NEXT:    blr
 ;
 ; SPE-LABEL: fmadd_v2f64:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    mflr r0
-; SPE-NEXT:    stwu r1, -64(r1)
-; SPE-NEXT:    stw r0, 68(r1)
-; SPE-NEXT:    .cfi_def_cfa_offset 64
+; SPE-NEXT:    stwu r1, -80(r1)
+; SPE-NEXT:    stw r0, 84(r1)
+; SPE-NEXT:    .cfi_def_cfa_offset 80
 ; SPE-NEXT:    .cfi_offset lr, 4
-; SPE-NEXT:    .cfi_offset r26, -48
-; SPE-NEXT:    .cfi_offset r27, -40
-; SPE-NEXT:    .cfi_offset r28, -32
-; SPE-NEXT:    .cfi_offset r29, -24
-; SPE-NEXT:    .cfi_offset r30, -16
+; SPE-NEXT:    .cfi_offset r26, -64
+; SPE-NEXT:    .cfi_offset r27, -56
+; SPE-NEXT:    .cfi_offset r28, -48
+; SPE-NEXT:    .cfi_offset r29, -40
+; SPE-NEXT:    .cfi_offset r30, -8
 ; SPE-NEXT:    evstdd r26, 16(r1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd r27, 24(r1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd r28, 32(r1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd r29, 40(r1) # 8-byte Folded Spill
-; SPE-NEXT:    evstdd r30, 48(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r30, 72(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    evmergelo r27, r7, r8
 ; SPE-NEXT:    evmergelo r9, r9, r10
 ; SPE-NEXT:    evmergelo r4, r5, r6
 ; SPE-NEXT:    mr r30, r3
-; SPE-NEXT:    evldd r8, 80(r1)
+; SPE-NEXT:    evldd r8, 96(r1)
 ; SPE-NEXT:    evmergehi r3, r4, r4
 ; SPE-NEXT:    evmergehi r5, r9, r9
 ; SPE-NEXT:    mr r6, r9
-; SPE-NEXT:    evldd r29, 88(r1)
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r5 killed $r5 killed $s5
+; SPE-NEXT:    evldd r29, 104(r1)
 ; SPE-NEXT:    evmergehi r7, r8, r8
-; SPE-NEXT:    evldd r28, 72(r1)
-; SPE-NEXT:    # kill: def $r7 killed $r7 killed $s7
-; SPE-NEXT:    # kill: def $r8 killed $r8 killed $s8
+; SPE-NEXT:    evldd r28, 88(r1)
 ; SPE-NEXT:    bl fma
 ; SPE-NEXT:    evmergelo r26, r3, r4
 ; SPE-NEXT:    evmergehi r3, r27, r27
 ; SPE-NEXT:    evmergehi r5, r28, r28
 ; SPE-NEXT:    evmergehi r7, r29, r29
 ; SPE-NEXT:    mr r4, r27
 ; SPE-NEXT:    mr r6, r28
 ; SPE-NEXT:    mr r8, r29
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; SPE-NEXT:    # kill: def $r5 killed $r5 killed $s5
-; SPE-NEXT:    # kill: def $r7 killed $r7 killed $s7
 ; SPE-NEXT:    bl fma
 ; SPE-NEXT:    li r5, 8
 ; SPE-NEXT:    evmergelo r3, r3, r4
 ; SPE-NEXT:    evstddx r3, r30, r5
 ; SPE-NEXT:    evstdd r26, 0(r30)
-; SPE-NEXT:    evldd r30, 48(r1) # 8-byte Folded Reload
+; SPE-NEXT:    lwz r30, 72(r1) # 4-byte Folded Reload
 ; SPE-NEXT:    evldd r29, 40(r1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd r28, 32(r1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd r27, 24(r1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd r26, 16(r1) # 8-byte Folded Reload
-; SPE-NEXT:    lwz r0, 68(r1)
-; SPE-NEXT:    addi r1, r1, 64
+; SPE-NEXT:    lwz r0, 84(r1)
+; SPE-NEXT:    addi r1, r1, 80
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
   %res = call <2 x double> @llvm.experimental.constrained.fma.v2f64(
                         <2 x double> %vf0, <2 x double> %vf1, <2 x double> %vf2,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   ret <2 x double> %res
 }

 ; SPE-NEXT:    .cfi_def_cfa_offset 16
 ; SPE-NEXT:    .cfi_offset lr, 4
 ; SPE-NEXT:    evmergelo r6, r5, r6
 ; SPE-NEXT:    evmergelo r4, r3, r4
 ; SPE-NEXT:    evmergelo r3, r7, r8
 ; SPE-NEXT:    efdneg r8, r3
 ; SPE-NEXT:    evmergehi r3, r4, r4
 ; SPE-NEXT:    evmergehi r5, r6, r6
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r6 killed $r6 killed $s6
 ; SPE-NEXT:    evmergehi r7, r8, r8
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; SPE-NEXT:    # kill: def $r5 killed $r5 killed $s5
-; SPE-NEXT:    # kill: def $r8 killed $r8 killed $s8
-; SPE-NEXT:    # kill: def $r7 killed $r7 killed $s7
 ; SPE-NEXT:    bl fma
 ; SPE-NEXT:    evmergelo r4, r3, r4
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
 ; SPE-NEXT:    lwz r0, 20(r1)
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    addi r1, r1, 16
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
   %neg = fneg double %f2
   %res = call double @llvm.experimental.constrained.fma.f64(
                         double %f0, double %f1, double %neg,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0

 ; NOVSX-NEXT:    fmadds f0, f1, f0, f2
 ; NOVSX-NEXT:    stfs f0, -16(r1)
 ; NOVSX-NEXT:    lvx v2, 0, r3
 ; NOVSX-NEXT:    blr
 ;
 ; SPE-LABEL: fmsub_v4f32:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    mflr r0
-; SPE-NEXT:    stwu r1, -96(r1)
-; SPE-NEXT:    stw r0, 100(r1)
-; SPE-NEXT:    .cfi_def_cfa_offset 96
+; SPE-NEXT:    stwu r1, -64(r1)
+; SPE-NEXT:    stw r0, 68(r1)
+; SPE-NEXT:    .cfi_def_cfa_offset 64
 ; SPE-NEXT:    .cfi_offset lr, 4
-; SPE-NEXT:    .cfi_offset r21, -88
-; SPE-NEXT:    .cfi_offset r22, -80
-; SPE-NEXT:    .cfi_offset r23, -72
-; SPE-NEXT:    .cfi_offset r24, -64
-; SPE-NEXT:    .cfi_offset r25, -56
-; SPE-NEXT:    .cfi_offset r26, -48
-; SPE-NEXT:    .cfi_offset r27, -40
-; SPE-NEXT:    .cfi_offset r28, -32
-; SPE-NEXT:    .cfi_offset r29, -24
-; SPE-NEXT:    .cfi_offset r30, -16
-; SPE-NEXT:    evstdd r25, 40(r1) # 8-byte Folded Spill
+; SPE-NEXT:    .cfi_offset r21, -44
+; SPE-NEXT:    .cfi_offset r22, -40
+; SPE-NEXT:    .cfi_offset r23, -36
+; SPE-NEXT:    .cfi_offset r24, -32
+; SPE-NEXT:    .cfi_offset r25, -28
+; SPE-NEXT:    .cfi_offset r26, -24
+; SPE-NEXT:    .cfi_offset r27, -20
+; SPE-NEXT:    .cfi_offset r28, -16
+; SPE-NEXT:    .cfi_offset r29, -12
+; SPE-NEXT:    .cfi_offset r30, -8
+; SPE-NEXT:    stw r25, 36(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r25, r3
-; SPE-NEXT:    evstdd r26, 48(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r26, 40(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r26, r4
-; SPE-NEXT:    evstdd r27, 56(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r27, 44(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r27, r5
-; SPE-NEXT:    evstdd r28, 64(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r28, 48(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r28, r7
-; SPE-NEXT:    lwz r3, 112(r1)
-; SPE-NEXT:    lwz r4, 104(r1)
-; SPE-NEXT:    lwz r5, 108(r1)
-; SPE-NEXT:    lwz r7, 116(r1)
-; SPE-NEXT:    evstdd r22, 16(r1) # 8-byte Folded Spill
+; SPE-NEXT:    lwz r3, 80(r1)
+; SPE-NEXT:    lwz r4, 72(r1)
+; SPE-NEXT:    lwz r5, 76(r1)
+; SPE-NEXT:    lwz r7, 84(r1)
+; SPE-NEXT:    stw r22, 24(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    efsneg r22, r3
-; SPE-NEXT:    evstdd r23, 24(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r23, 28(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    efsneg r23, r5
-; SPE-NEXT:    evstdd r24, 32(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r24, 32(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    efsneg r24, r4
 ; SPE-NEXT:    efsneg r5, r7
 ; SPE-NEXT:    mr r3, r6
 ; SPE-NEXT:    mr r4, r10
-; SPE-NEXT:    evstdd r21, 8(r1) # 8-byte Folded Spill
-; SPE-NEXT:    evstdd r29, 72(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r21, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT:    stw r29, 52(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r29, r8
-; SPE-NEXT:    evstdd r30, 80(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r30, 56(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r30, r9
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    mr r21, r3
 ; SPE-NEXT:    mr r3, r27
 ; SPE-NEXT:    mr r4, r30
 ; SPE-NEXT:    mr r5, r22
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    mr r30, r3
 ; SPE-NEXT:    mr r3, r26
 ; SPE-NEXT:    mr r4, r29
 ; SPE-NEXT:    mr r5, r23
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    mr r29, r3
 ; SPE-NEXT:    mr r3, r25
 ; SPE-NEXT:    mr r4, r28
 ; SPE-NEXT:    mr r5, r24
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    mr r4, r29
 ; SPE-NEXT:    mr r5, r30
 ; SPE-NEXT:    mr r6, r21
-; SPE-NEXT:    evldd r30, 80(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r29, 72(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r28, 64(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r27, 56(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r26, 48(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r25, 40(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r24, 32(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r23, 24(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r22, 16(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r21, 8(r1) # 8-byte Folded Reload
-; SPE-NEXT:    lwz r0, 100(r1)
-; SPE-NEXT:    addi r1, r1, 96
+; SPE-NEXT:    lwz r30, 56(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r29, 52(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r28, 48(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r27, 44(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r26, 40(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r25, 36(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r24, 32(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r23, 28(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r22, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r21, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r0, 68(r1)
+; SPE-NEXT:    addi r1, r1, 64
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
   %neg = fneg <4 x float> %vf2
   %res = call <4 x float> @llvm.experimental.constrained.fma.v4f32(
                         <4 x float> %vf0, <4 x float> %vf1, <4 x float> %neg,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   ret <4 x float> %res

 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    fmsub f2, f2, f4, f6
 ; NOVSX-NEXT:    fmsub f1, f1, f3, f5
 ; NOVSX-NEXT:    blr
 ;
 ; SPE-LABEL: fmsub_v2f64:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    mflr r0
-; SPE-NEXT:    stwu r1, -64(r1)
-; SPE-NEXT:    stw r0, 68(r1)
-; SPE-NEXT:    .cfi_def_cfa_offset 64
+; SPE-NEXT:    stwu r1, -80(r1)
+; SPE-NEXT:    stw r0, 84(r1)
+; SPE-NEXT:    .cfi_def_cfa_offset 80
 ; SPE-NEXT:    .cfi_offset lr, 4
-; SPE-NEXT:    .cfi_offset r26, -48
-; SPE-NEXT:    .cfi_offset r27, -40
-; SPE-NEXT:    .cfi_offset r28, -32
-; SPE-NEXT:    .cfi_offset r29, -24
-; SPE-NEXT:    .cfi_offset r30, -16
-; SPE-NEXT:    evstdd r30, 48(r1) # 8-byte Folded Spill
+; SPE-NEXT:    .cfi_offset r26, -64
+; SPE-NEXT:    .cfi_offset r27, -56
+; SPE-NEXT:    .cfi_offset r28, -48
+; SPE-NEXT:    .cfi_offset r29, -40
+; SPE-NEXT:    .cfi_offset r30, -8
+; SPE-NEXT:    stw r30, 72(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r30, r3
-; SPE-NEXT:    evldd r3, 80(r1)
-; SPE-NEXT:    evldd r11, 88(r1)
+; SPE-NEXT:    evldd r3, 96(r1)
+; SPE-NEXT:    evldd r11, 104(r1)
 ; SPE-NEXT:    evstdd r26, 16(r1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd r27, 24(r1) # 8-byte Folded Spill
 ; SPE-NEXT:    efdneg r27, r11
 ; SPE-NEXT:    evstdd r28, 32(r1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd r29, 40(r1) # 8-byte Folded Spill
 ; SPE-NEXT:    evmergelo r29, r7, r8
 ; SPE-NEXT:    evmergelo r9, r9, r10
 ; SPE-NEXT:    evmergelo r4, r5, r6
 ; SPE-NEXT:    efdneg r8, r3
 ; SPE-NEXT:    evmergehi r3, r4, r4
 ; SPE-NEXT:    evmergehi r5, r9, r9
 ; SPE-NEXT:    evmergehi r7, r8, r8
 ; SPE-NEXT:    mr r6, r9
-; SPE-NEXT:    evldd r28, 72(r1)
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r5 killed $r5 killed $s5
-; SPE-NEXT:    # kill: def $r7 killed $r7 killed $s7
-; SPE-NEXT:    # kill: def $r8 killed $r8 killed $s8
+; SPE-NEXT:    evldd r28, 88(r1)
 ; SPE-NEXT:    bl fma
 ; SPE-NEXT:    evmergelo r26, r3, r4
 ; SPE-NEXT:    evmergehi r3, r29, r29
 ; SPE-NEXT:    evmergehi r5, r28, r28
 ; SPE-NEXT:    evmergehi r7, r27, r27
 ; SPE-NEXT:    mr r4, r29
 ; SPE-NEXT:    mr r6, r28
 ; SPE-NEXT:    mr r8, r27
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; SPE-NEXT:    # kill: def $r5 killed $r5 killed $s5
-; SPE-NEXT:    # kill: def $r7 killed $r7 killed $s7
 ; SPE-NEXT:    bl fma
 ; SPE-NEXT:    li r5, 8
 ; SPE-NEXT:    evmergelo r3, r3, r4
 ; SPE-NEXT:    evstddx r3, r30, r5
 ; SPE-NEXT:    evstdd r26, 0(r30)
-; SPE-NEXT:    evldd r30, 48(r1) # 8-byte Folded Reload
+; SPE-NEXT:    lwz r30, 72(r1) # 4-byte Folded Reload
 ; SPE-NEXT:    evldd r29, 40(r1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd r28, 32(r1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd r27, 24(r1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd r26, 16(r1) # 8-byte Folded Reload
-; SPE-NEXT:    lwz r0, 68(r1)
-; SPE-NEXT:    addi r1, r1, 64
+; SPE-NEXT:    lwz r0, 84(r1)
+; SPE-NEXT:    addi r1, r1, 80
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
   %neg = fneg <2 x double> %vf2
   %res = call <2 x double> @llvm.experimental.constrained.fma.v2f64(
                         <2 x double> %vf0, <2 x double> %vf1, <2 x double> %neg,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   ret <2 x double> %res

 ; SPE-NEXT:    .cfi_def_cfa_offset 16
 ; SPE-NEXT:    .cfi_offset lr, 4
 ; SPE-NEXT:    evmergelo r8, r7, r8
 ; SPE-NEXT:    evmergelo r6, r5, r6
 ; SPE-NEXT:    evmergelo r4, r3, r4
 ; SPE-NEXT:    evmergehi r3, r4, r4
 ; SPE-NEXT:    evmergehi r5, r6, r6
 ; SPE-NEXT:    evmergehi r7, r8, r8
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r6 killed $r6 killed $s6
-; SPE-NEXT:    # kill: def $r8 killed $r8 killed $s8
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; SPE-NEXT:    # kill: def $r5 killed $r5 killed $s5
-; SPE-NEXT:    # kill: def $r7 killed $r7 killed $s7
 ; SPE-NEXT:    bl fma
 ; SPE-NEXT:    evmergelo r3, r3, r4
 ; SPE-NEXT:    efdneg r4, r3
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
 ; SPE-NEXT:    lwz r0, 20(r1)
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    addi r1, r1, 16
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
   %fma = call double @llvm.experimental.constrained.fma.f64(
                         double %f0, double %f1, double %f2,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   %res = fneg double %fma

 ; NOVSX-NEXT:    stfs f0, -16(r1)
 ; NOVSX-NEXT:    lvx v3, 0, r3
 ; NOVSX-NEXT:    vsubfp v2, v2, v3
 ; NOVSX-NEXT:    blr
 ;
 ; SPE-LABEL: fnmadd_v4f32:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    mflr r0
-; SPE-NEXT:    stwu r1, -96(r1)
-; SPE-NEXT:    stw r0, 100(r1)
-; SPE-NEXT:    .cfi_def_cfa_offset 96
+; SPE-NEXT:    stwu r1, -64(r1)
+; SPE-NEXT:    stw r0, 68(r1)
+; SPE-NEXT:    .cfi_def_cfa_offset 64
 ; SPE-NEXT:    .cfi_offset lr, 4
-; SPE-NEXT:    .cfi_offset r21, -88
-; SPE-NEXT:    .cfi_offset r22, -80
-; SPE-NEXT:    .cfi_offset r23, -72
-; SPE-NEXT:    .cfi_offset r24, -64
-; SPE-NEXT:    .cfi_offset r25, -56
-; SPE-NEXT:    .cfi_offset r26, -48
-; SPE-NEXT:    .cfi_offset r27, -40
-; SPE-NEXT:    .cfi_offset r28, -32
-; SPE-NEXT:    .cfi_offset r29, -24
-; SPE-NEXT:    .cfi_offset r30, -16
-; SPE-NEXT:    evstdd r27, 56(r1) # 8-byte Folded Spill
+; SPE-NEXT:    .cfi_offset r21, -44
+; SPE-NEXT:    .cfi_offset r22, -40
+; SPE-NEXT:    .cfi_offset r23, -36
+; SPE-NEXT:    .cfi_offset r24, -32
+; SPE-NEXT:    .cfi_offset r25, -28
+; SPE-NEXT:    .cfi_offset r26, -24
+; SPE-NEXT:    .cfi_offset r27, -20
+; SPE-NEXT:    .cfi_offset r28, -16
+; SPE-NEXT:    .cfi_offset r29, -12
+; SPE-NEXT:    .cfi_offset r30, -8
+; SPE-NEXT:    stw r27, 44(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r27, r5
-; SPE-NEXT:    lwz r5, 116(r1)
-; SPE-NEXT:    evstdd r25, 40(r1) # 8-byte Folded Spill
+; SPE-NEXT:    lwz r5, 84(r1)
+; SPE-NEXT:    stw r25, 36(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r25, r3
-; SPE-NEXT:    evstdd r26, 48(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r26, 40(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r26, r4
 ; SPE-NEXT:    mr r3, r6
 ; SPE-NEXT:    mr r4, r10
-; SPE-NEXT:    evstdd r21, 8(r1) # 8-byte Folded Spill
-; SPE-NEXT:    evstdd r22, 16(r1) # 8-byte Folded Spill
-; SPE-NEXT:    evstdd r23, 24(r1) # 8-byte Folded Spill
-; SPE-NEXT:    evstdd r24, 32(r1) # 8-byte Folded Spill
-; SPE-NEXT:    evstdd r28, 64(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r21, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT:    stw r22, 24(r1) # 4-byte Folded Spill
+; SPE-NEXT:    stw r23, 28(r1) # 4-byte Folded Spill
+; SPE-NEXT:    stw r24, 32(r1) # 4-byte Folded Spill
+; SPE-NEXT:    stw r28, 48(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r28, r7
-; SPE-NEXT:    evstdd r29, 72(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r29, 52(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r29, r8
-; SPE-NEXT:    evstdd r30, 80(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r30, 56(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r30, r9
-; SPE-NEXT:    lwz r24, 104(r1)
-; SPE-NEXT:    lwz r23, 108(r1)
-; SPE-NEXT:    lwz r22, 112(r1)
+; SPE-NEXT:    lwz r24, 72(r1)
+; SPE-NEXT:    lwz r23, 76(r1)
+; SPE-NEXT:    lwz r22, 80(r1)
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    mr r21, r3
 ; SPE-NEXT:    mr r3, r27
 ; SPE-NEXT:    mr r4, r30
 ; SPE-NEXT:    mr r5, r22
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    mr r30, r3
 ; SPE-NEXT:    mr r3, r26
 ; SPE-NEXT:    mr r4, r29
 ; SPE-NEXT:    mr r5, r23
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    mr r29, r3
 ; SPE-NEXT:    mr r3, r25
 ; SPE-NEXT:    mr r4, r28
 ; SPE-NEXT:    mr r5, r24
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    efsneg r4, r29
 ; SPE-NEXT:    efsneg r5, r30
 ; SPE-NEXT:    efsneg r3, r3
 ; SPE-NEXT:    efsneg r6, r21
-; SPE-NEXT:    evldd r30, 80(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r29, 72(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r28, 64(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r27, 56(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r26, 48(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r25, 40(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r24, 32(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r23, 24(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r22, 16(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r21, 8(r1) # 8-byte Folded Reload
-; SPE-NEXT:    lwz r0, 100(r1)
-; SPE-NEXT:    addi r1, r1, 96
+; SPE-NEXT:    lwz r30, 56(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r29, 52(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r28, 48(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r27, 44(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r26, 40(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r25, 36(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r24, 32(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r23, 28(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r22, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r21, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r0, 68(r1)
+; SPE-NEXT:    addi r1, r1, 64
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
   %fma = call <4 x float> @llvm.experimental.constrained.fma.v4f32(
                         <4 x float> %vf0, <4 x float> %vf1, <4 x float> %vf2,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   %res = fneg <4 x float> %fma
   ret <4 x float> %res

 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    fnmadd f2, f2, f4, f6
 ; NOVSX-NEXT:    fnmadd f1, f1, f3, f5
 ; NOVSX-NEXT:    blr
 ;
 ; SPE-LABEL: fnmadd_v2f64:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    mflr r0
-; SPE-NEXT:    stwu r1, -64(r1)
-; SPE-NEXT:    stw r0, 68(r1)
-; SPE-NEXT:    .cfi_def_cfa_offset 64
+; SPE-NEXT:    stwu r1, -80(r1)
+; SPE-NEXT:    stw r0, 84(r1)
+; SPE-NEXT:    .cfi_def_cfa_offset 80
 ; SPE-NEXT:    .cfi_offset lr, 4
-; SPE-NEXT:    .cfi_offset r26, -48
-; SPE-NEXT:    .cfi_offset r27, -40
-; SPE-NEXT:    .cfi_offset r28, -32
-; SPE-NEXT:    .cfi_offset r29, -24
-; SPE-NEXT:    .cfi_offset r30, -16
+; SPE-NEXT:    .cfi_offset r26, -64
+; SPE-NEXT:    .cfi_offset r27, -56
+; SPE-NEXT:    .cfi_offset r28, -48
+; SPE-NEXT:    .cfi_offset r29, -40
+; SPE-NEXT:    .cfi_offset r30, -8
 ; SPE-NEXT:    evstdd r26, 16(r1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd r27, 24(r1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd r28, 32(r1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd r29, 40(r1) # 8-byte Folded Spill
-; SPE-NEXT:    evstdd r30, 48(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r30, 72(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    evmergelo r27, r7, r8
 ; SPE-NEXT:    evmergelo r9, r9, r10
 ; SPE-NEXT:    evmergelo r4, r5, r6
 ; SPE-NEXT:    mr r30, r3
-; SPE-NEXT:    evldd r8, 80(r1)
+; SPE-NEXT:    evldd r8, 96(r1)
 ; SPE-NEXT:    evmergehi r3, r4, r4
 ; SPE-NEXT:    evmergehi r5, r9, r9
 ; SPE-NEXT:    mr r6, r9
-; SPE-NEXT:    evldd r29, 88(r1)
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r5 killed $r5 killed $s5
+; SPE-NEXT:    evldd r29, 104(r1)
 ; SPE-NEXT:    evmergehi r7, r8, r8
-; SPE-NEXT:    evldd r28, 72(r1)
-; SPE-NEXT:    # kill: def $r7 killed $r7 killed $s7
-; SPE-NEXT:    # kill: def $r8 killed $r8 killed $s8
+; SPE-NEXT:    evldd r28, 88(r1)
 ; SPE-NEXT:    bl fma
 ; SPE-NEXT:    evmergelo r26, r3, r4
 ; SPE-NEXT:    evmergehi r3, r27, r27
 ; SPE-NEXT:    evmergehi r5, r28, r28
 ; SPE-NEXT:    evmergehi r7, r29, r29
 ; SPE-NEXT:    mr r4, r27
 ; SPE-NEXT:    mr r6, r28
 ; SPE-NEXT:    mr r8, r29
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; SPE-NEXT:    # kill: def $r5 killed $r5 killed $s5
-; SPE-NEXT:    # kill: def $r7 killed $r7 killed $s7
 ; SPE-NEXT:    bl fma
 ; SPE-NEXT:    evmergelo r3, r3, r4
 ; SPE-NEXT:    li r5, 8
 ; SPE-NEXT:    efdneg r3, r3
 ; SPE-NEXT:    evstddx r3, r30, r5
 ; SPE-NEXT:    efdneg r3, r26
 ; SPE-NEXT:    evstdd r3, 0(r30)
-; SPE-NEXT:    evldd r30, 48(r1) # 8-byte Folded Reload
+; SPE-NEXT:    lwz r30, 72(r1) # 4-byte Folded Reload
 ; SPE-NEXT:    evldd r29, 40(r1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd r28, 32(r1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd r27, 24(r1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd r26, 16(r1) # 8-byte Folded Reload
-; SPE-NEXT:    lwz r0, 68(r1)
-; SPE-NEXT:    addi r1, r1, 64
+; SPE-NEXT:    lwz r0, 84(r1)
+; SPE-NEXT:    addi r1, r1, 80
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
   %fma = call <2 x double> @llvm.experimental.constrained.fma.v2f64(
                         <2 x double> %vf0, <2 x double> %vf1, <2 x double> %vf2,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   %res = fneg <2 x double> %fma
   ret <2 x double> %res

 ; SPE-NEXT:    .cfi_def_cfa_offset 16
 ; SPE-NEXT:    .cfi_offset lr, 4
 ; SPE-NEXT:    evmergelo r6, r5, r6
 ; SPE-NEXT:    evmergelo r4, r3, r4
 ; SPE-NEXT:    evmergelo r3, r7, r8
 ; SPE-NEXT:    efdneg r8, r3
 ; SPE-NEXT:    evmergehi r3, r4, r4
 ; SPE-NEXT:    evmergehi r5, r6, r6
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r6 killed $r6 killed $s6
 ; SPE-NEXT:    evmergehi r7, r8, r8
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; SPE-NEXT:    # kill: def $r5 killed $r5 killed $s5
-; SPE-NEXT:    # kill: def $r8 killed $r8 killed $s8
-; SPE-NEXT:    # kill: def $r7 killed $r7 killed $s7
 ; SPE-NEXT:    bl fma
 ; SPE-NEXT:    evmergelo r3, r3, r4
 ; SPE-NEXT:    efdneg r4, r3
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
 ; SPE-NEXT:    lwz r0, 20(r1)
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    addi r1, r1, 16
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
   %neg = fneg double %f2
   %fma = call double @llvm.experimental.constrained.fma.f64(
                         double %f0, double %f1, double %neg,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0

 ; NOVSX-NEXT:    stfs f0, -16(r1)
 ; NOVSX-NEXT:    lvx v2, 0, r3
 ; NOVSX-NEXT:    vsubfp v2, v5, v2
 ; NOVSX-NEXT:    blr
 ;
 ; SPE-LABEL: fnmsub_v4f32:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    mflr r0
-; SPE-NEXT:    stwu r1, -96(r1)
-; SPE-NEXT:    stw r0, 100(r1)
-; SPE-NEXT:    .cfi_def_cfa_offset 96
+; SPE-NEXT:    stwu r1, -64(r1)
+; SPE-NEXT:    stw r0, 68(r1)
+; SPE-NEXT:    .cfi_def_cfa_offset 64
 ; SPE-NEXT:    .cfi_offset lr, 4
-; SPE-NEXT:    .cfi_offset r21, -88
-; SPE-NEXT:    .cfi_offset r22, -80
-; SPE-NEXT:    .cfi_offset r23, -72
-; SPE-NEXT:    .cfi_offset r24, -64
-; SPE-NEXT:    .cfi_offset r25, -56
-; SPE-NEXT:    .cfi_offset r26, -48
-; SPE-NEXT:    .cfi_offset r27, -40
-; SPE-NEXT:    .cfi_offset r28, -32
-; SPE-NEXT:    .cfi_offset r29, -24
-; SPE-NEXT:    .cfi_offset r30, -16
-; SPE-NEXT:    evstdd r25, 40(r1) # 8-byte Folded Spill
+; SPE-NEXT:    .cfi_offset r21, -44
+; SPE-NEXT:    .cfi_offset r22, -40
+; SPE-NEXT:    .cfi_offset r23, -36
+; SPE-NEXT:    .cfi_offset r24, -32
+; SPE-NEXT:    .cfi_offset r25, -28
+; SPE-NEXT:    .cfi_offset r26, -24
+; SPE-NEXT:    .cfi_offset r27, -20
+; SPE-NEXT:    .cfi_offset r28, -16
+; SPE-NEXT:    .cfi_offset r29, -12
+; SPE-NEXT:    .cfi_offset r30, -8
+; SPE-NEXT:    stw r25, 36(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r25, r3
-; SPE-NEXT:    evstdd r26, 48(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r26, 40(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r26, r4
-; SPE-NEXT:    evstdd r27, 56(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r27, 44(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r27, r5
-; SPE-NEXT:    evstdd r28, 64(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r28, 48(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r28, r7
-; SPE-NEXT:    lwz r3, 112(r1)
-; SPE-NEXT:    lwz r4, 104(r1)
-; SPE-NEXT:    lwz r5, 108(r1)
-; SPE-NEXT:    lwz r7, 116(r1)
-; SPE-NEXT:    evstdd r22, 16(r1) # 8-byte Folded Spill
+; SPE-NEXT:    lwz r3, 80(r1)
+; SPE-NEXT:    lwz r4, 72(r1)
+; SPE-NEXT:    lwz r5, 76(r1)
+; SPE-NEXT:    lwz r7, 84(r1)
+; SPE-NEXT:    stw r22, 24(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    efsneg r22, r3
-; SPE-NEXT:    evstdd r23, 24(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r23, 28(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    efsneg r23, r5
-; SPE-NEXT:    evstdd r24, 32(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r24, 32(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    efsneg r24, r4
 ; SPE-NEXT:    efsneg r5, r7
 ; SPE-NEXT:    mr r3, r6
 ; SPE-NEXT:    mr r4, r10
-; SPE-NEXT:    evstdd r21, 8(r1) # 8-byte Folded Spill
-; SPE-NEXT:    evstdd r29, 72(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r21, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT:    stw r29, 52(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r29, r8
-; SPE-NEXT:    evstdd r30, 80(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r30, 56(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r30, r9
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    mr r21, r3
 ; SPE-NEXT:    mr r3, r27
 ; SPE-NEXT:    mr r4, r30
 ; SPE-NEXT:    mr r5, r22
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    mr r30, r3
 ; SPE-NEXT:    mr r3, r26
 ; SPE-NEXT:    mr r4, r29
 ; SPE-NEXT:    mr r5, r23
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    mr r29, r3
 ; SPE-NEXT:    mr r3, r25
 ; SPE-NEXT:    mr r4, r28
 ; SPE-NEXT:    mr r5, r24
 ; SPE-NEXT:    bl fmaf
 ; SPE-NEXT:    efsneg r4, r29
 ; SPE-NEXT:    efsneg r5, r30
 ; SPE-NEXT:    efsneg r3, r3
 ; SPE-NEXT:    efsneg r6, r21
-; SPE-NEXT:    evldd r30, 80(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r29, 72(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r28, 64(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r27, 56(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r26, 48(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r25, 40(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r24, 32(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r23, 24(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r22, 16(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r21, 8(r1) # 8-byte Folded Reload
-; SPE-NEXT:    lwz r0, 100(r1)
-; SPE-NEXT:    addi r1, r1, 96
+; SPE-NEXT:    lwz r30, 56(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r29, 52(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r28, 48(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r27, 44(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r26, 40(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r25, 36(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r24, 32(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r23, 28(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r22, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r21, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r0, 68(r1)
+; SPE-NEXT:    addi r1, r1, 64
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
   %neg = fneg <4 x float> %vf2
   %fma = call <4 x float> @llvm.experimental.constrained.fma.v4f32(
                         <4 x float> %vf0, <4 x float> %vf1, <4 x float> %neg,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   %res = fneg <4 x float> %fma

 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    fnmsub f2, f2, f4, f6
 ; NOVSX-NEXT:    fnmsub f1, f1, f3, f5
 ; NOVSX-NEXT:    blr
 ;
 ; SPE-LABEL: fnmsub_v2f64:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    mflr r0
-; SPE-NEXT:    stwu r1, -64(r1)
-; SPE-NEXT:    stw r0, 68(r1)
-; SPE-NEXT:    .cfi_def_cfa_offset 64
+; SPE-NEXT:    stwu r1, -80(r1)
+; SPE-NEXT:    stw r0, 84(r1)
+; SPE-NEXT:    .cfi_def_cfa_offset 80
 ; SPE-NEXT:    .cfi_offset lr, 4
-; SPE-NEXT:    .cfi_offset r26, -48
-; SPE-NEXT:    .cfi_offset r27, -40
-; SPE-NEXT:    .cfi_offset r28, -32
-; SPE-NEXT:    .cfi_offset r29, -24
-; SPE-NEXT:    .cfi_offset r30, -16
-; SPE-NEXT:    evstdd r30, 48(r1) # 8-byte Folded Spill
+; SPE-NEXT:    .cfi_offset r26, -64
+; SPE-NEXT:    .cfi_offset r27, -56
+; SPE-NEXT:    .cfi_offset r28, -48
+; SPE-NEXT:    .cfi_offset r29, -40
+; SPE-NEXT:    .cfi_offset r30, -8
+; SPE-NEXT:    stw r30, 72(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r30, r3
-; SPE-NEXT:    evldd r3, 80(r1)
-; SPE-NEXT:    evldd r11, 88(r1)
+; SPE-NEXT:    evldd r3, 96(r1)
+; SPE-NEXT:    evldd r11, 104(r1)
 ; SPE-NEXT:    evstdd r26, 16(r1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd r27, 24(r1) # 8-byte Folded Spill
 ; SPE-NEXT:    efdneg r27, r11
 ; SPE-NEXT:    evstdd r28, 32(r1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd r29, 40(r1) # 8-byte Folded Spill
 ; SPE-NEXT:    evmergelo r29, r7, r8
 ; SPE-NEXT:    evmergelo r9, r9, r10
 ; SPE-NEXT:    evmergelo r4, r5, r6
 ; SPE-NEXT:    efdneg r8, r3
 ; SPE-NEXT:    evmergehi r3, r4, r4
 ; SPE-NEXT:    evmergehi r5, r9, r9
 ; SPE-NEXT:    evmergehi r7, r8, r8
 ; SPE-NEXT:    mr r6, r9
-; SPE-NEXT:    evldd r28, 72(r1)
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r5 killed $r5 killed $s5
-; SPE-NEXT:    # kill: def $r7 killed $r7 killed $s7
-; SPE-NEXT:    # kill: def $r8 killed $r8 killed $s8
+; SPE-NEXT:    evldd r28, 88(r1)
 ; SPE-NEXT:    bl fma
 ; SPE-NEXT:    evmergelo r26, r3, r4
 ; SPE-NEXT:    evmergehi r3, r29, r29
 ; SPE-NEXT:    evmergehi r5, r28, r28
 ; SPE-NEXT:    evmergehi r7, r27, r27
 ; SPE-NEXT:    mr r4, r29
 ; SPE-NEXT:    mr r6, r28
 ; SPE-NEXT:    mr r8, r27
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; SPE-NEXT:    # kill: def $r5 killed $r5 killed $s5
-; SPE-NEXT:    # kill: def $r7 killed $r7 killed $s7
 ; SPE-NEXT:    bl fma
 ; SPE-NEXT:    evmergelo r3, r3, r4
 ; SPE-NEXT:    li r5, 8
 ; SPE-NEXT:    efdneg r3, r3
 ; SPE-NEXT:    evstddx r3, r30, r5
 ; SPE-NEXT:    efdneg r3, r26
 ; SPE-NEXT:    evstdd r3, 0(r30)
-; SPE-NEXT:    evldd r30, 48(r1) # 8-byte Folded Reload
+; SPE-NEXT:    lwz r30, 72(r1) # 4-byte Folded Reload
 ; SPE-NEXT:    evldd r29, 40(r1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd r28, 32(r1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd r27, 24(r1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd r26, 16(r1) # 8-byte Folded Reload
-; SPE-NEXT:    lwz r0, 68(r1)
-; SPE-NEXT:    addi r1, r1, 64
+; SPE-NEXT:    lwz r0, 84(r1)
+; SPE-NEXT:    addi r1, r1, 80
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
   %neg = fneg <2 x double> %vf2
   %fma = call <2 x double> @llvm.experimental.constrained.fma.v2f64(
                         <2 x double> %vf0, <2 x double> %vf1, <2 x double> %neg,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   %res = fneg <2 x double> %fma

 ; SPE:       # %bb.0:
 ; SPE-NEXT:    mflr r0
 ; SPE-NEXT:    stwu r1, -16(r1)
 ; SPE-NEXT:    stw r0, 20(r1)
 ; SPE-NEXT:    .cfi_def_cfa_offset 16
 ; SPE-NEXT:    .cfi_offset lr, 4
 ; SPE-NEXT:    evmergelo r4, r3, r4
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    bl sqrt
 ; SPE-NEXT:    evmergelo r4, r3, r4
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
 ; SPE-NEXT:    lwz r0, 20(r1)
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    addi r1, r1, 16
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
   %res = call double @llvm.experimental.constrained.sqrt.f64(
                         double %f1,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   ret double %res

 ; NOVSX-NEXT:    fsqrts f0, f0
 ; NOVSX-NEXT:    stfs f0, -16(r1)
 ; NOVSX-NEXT:    lvx v2, 0, r3
 ; NOVSX-NEXT:    blr
 ;
 ; SPE-LABEL: fsqrt_v4f32:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    mflr r0
-; SPE-NEXT:    stwu r1, -48(r1)
-; SPE-NEXT:    stw r0, 52(r1)
-; SPE-NEXT:    .cfi_def_cfa_offset 48
+; SPE-NEXT:    stwu r1, -32(r1)
+; SPE-NEXT:    stw r0, 36(r1)
+; SPE-NEXT:    .cfi_def_cfa_offset 32
 ; SPE-NEXT:    .cfi_offset lr, 4
-; SPE-NEXT:    .cfi_offset r27, -40
-; SPE-NEXT:    .cfi_offset r28, -32
-; SPE-NEXT:    .cfi_offset r29, -24
-; SPE-NEXT:    .cfi_offset r30, -16
-; SPE-NEXT:    evstdd r28, 16(r1) # 8-byte Folded Spill
+; SPE-NEXT:    .cfi_offset r27, -20
+; SPE-NEXT:    .cfi_offset r28, -16
+; SPE-NEXT:    .cfi_offset r29, -12
+; SPE-NEXT:    .cfi_offset r30, -8
+; SPE-NEXT:    stw r28, 16(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r28, r3
 ; SPE-NEXT:    mr r3, r6
-; SPE-NEXT:    evstdd r27, 8(r1) # 8-byte Folded Spill
-; SPE-NEXT:    evstdd r29, 24(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r27, 12(r1) # 4-byte Folded Spill
+; SPE-NEXT:    stw r29, 20(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r29, r4
-; SPE-NEXT:    evstdd r30, 32(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r30, 24(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr r30, r5
 ; SPE-NEXT:    bl sqrtf
 ; SPE-NEXT:    mr r27, r3
 ; SPE-NEXT:    mr r3, r30
 ; SPE-NEXT:    bl sqrtf
 ; SPE-NEXT:    mr r30, r3
 ; SPE-NEXT:    mr r3, r29
 ; SPE-NEXT:    bl sqrtf
 ; SPE-NEXT:    mr r29, r3
 ; SPE-NEXT:    mr r3, r28
 ; SPE-NEXT:    bl sqrtf
 ; SPE-NEXT:    mr r4, r29
 ; SPE-NEXT:    mr r5, r30
 ; SPE-NEXT:    mr r6, r27
-; SPE-NEXT:    evldd r30, 32(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r29, 24(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r28, 16(r1) # 8-byte Folded Reload
-; SPE-NEXT:    evldd r27, 8(r1) # 8-byte Folded Reload
-; SPE-NEXT:    lwz r0, 52(r1)
-; SPE-NEXT:    addi r1, r1, 48
+; SPE-NEXT:    lwz r30, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r29, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r28, 16(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r27, 12(r1) # 4-byte Folded Reload
+; SPE-NEXT:    lwz r0, 36(r1)
+; SPE-NEXT:    addi r1, r1, 32
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
   %res = call <4 x float> @llvm.experimental.constrained.sqrt.v4f32(
                         <4 x float> %vf1,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   ret <4 x float> %res
 }
 
 define <2 x double> @fsqrt_v2f64(<2 x double> %vf1) #0 {
 ; CHECK-LABEL: fsqrt_v2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xvsqrtdp v2, v2
 ; CHECK-NEXT:    blr
 ;
 ; NOVSX-LABEL: fsqrt_v2f64:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    fsqrt f2, f2
 ; NOVSX-NEXT:    fsqrt f1, f1
 ; NOVSX-NEXT:    blr
 ;
 ; SPE-LABEL: fsqrt_v2f64:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    mflr r0
-; SPE-NEXT:    stwu r1, -48(r1)
-; SPE-NEXT:    stw r0, 52(r1)
-; SPE-NEXT:    .cfi_def_cfa_offset 48
+; SPE-NEXT:    stwu r1, -64(r1)
+; SPE-NEXT:    stw r0, 68(r1)
+; SPE-NEXT:    .cfi_def_cfa_offset 64
 ; SPE-NEXT:    .cfi_offset lr, 4
-; SPE-NEXT:    .cfi_offset r28, -32
-; SPE-NEXT:    .cfi_offset r29, -24
-; SPE-NEXT:    .cfi_offset r30, -16
+; SPE-NEXT:    .cfi_offset r28, -48
+; SPE-NEXT:    .cfi_offset r29, -40
+; SPE-NEXT:    .cfi_offset r30, -8
 ; SPE-NEXT:    evstdd r28, 16(r1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd r29, 24(r1) # 8-byte Folded Spill
-; SPE-NEXT:    evstdd r30, 32(r1) # 8-byte Folded Spill
+; SPE-NEXT:    stw r30, 56(r1) # 4-byte Folded Spill
 ; SPE-NEXT:    evmergelo r29, r7, r8
 ; SPE-NEXT:    evmergelo r4, r5, r6
 ; SPE-NEXT:    mr r30, r3
 ; SPE-NEXT:    evmergehi r3, r4, r4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    bl sqrt
 ; SPE-NEXT:    evmergelo r28, r3, r4
 ; SPE-NEXT:    evmergehi r3, r29, r29
 ; SPE-NEXT:    mr r4, r29
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    bl sqrt
 ; SPE-NEXT:    li r5, 8
 ; SPE-NEXT:    evmergelo r3, r3, r4
 ; SPE-NEXT:    evstddx r3, r30, r5
 ; SPE-NEXT:    evstdd r28, 0(r30)
-; SPE-NEXT:    evldd r30, 32(r1) # 8-byte Folded Reload
+; SPE-NEXT:    lwz r30, 56(r1) # 4-byte Folded Reload
 ; SPE-NEXT:    evldd r29, 24(r1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd r28, 16(r1) # 8-byte Folded Reload
-; SPE-NEXT:    lwz r0, 52(r1)
-; SPE-NEXT:    addi r1, r1, 48
+; SPE-NEXT:    lwz r0, 68(r1)
+; SPE-NEXT:    addi r1, r1, 64
 ; SPE-NEXT:    mtlr r0
 ; SPE-NEXT:    blr
   %res = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(
                         <2 x double> %vf1,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   ret <2 x double> %res
 }
 
 attributes #0 = { strictfp }

llvm/test/CodeGen/PowerPC/inline-asm-physical-fpr-spe.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
 ; RUN:          -mattr=+spe |  FileCheck %s
 
 define i32 @test_f32(float %x) {
 ; CHECK-LABEL: test_f32:
-; CHECK:         #APP
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset r31, -4
+; CHECK-NEXT:    stw 3, 8(1)
+; CHECK-NEXT:    stw 31, 12(1) # 4-byte Folded Spill
+; CHECK-NEXT:    lwz 3, 8(1)
+; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    efsctsi 31, 3
 ; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    mr 3, 31
+; CHECK-NEXT:    lwz 31, 12(1) # 4-byte Folded Reload
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
 entry:
   %0 = call i32 asm sideeffect "efsctsi $0, $1", "={f31},f"(float %x)
   ret i32 %0
 }
 
 define i32 @test_f64(double %x) {
 ; CHECK-LABEL: test_f64:
-; CHECK:         #APP
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    efdctsi 0, 3
 ; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    mr 3, 0
+; CHECK-NEXT:    blr
 entry:
   %0 = call i32 asm sideeffect "efdctsi $0, $1", "={f0},d"(double %x)
   ret i32 %0
 }
 

llvm/test/CodeGen/PowerPC/pr55463.ll

 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stwu 1, -48(1)
 ; CHECK-NEXT:    li 3, .LCPI1_0@l
 ; CHECK-NEXT:    li 5, .LCPI1_1@l
 ; CHECK-NEXT:    lis 4, .LCPI1_0@ha
 ; CHECK-NEXT:    lis 6, .LCPI1_1@ha
 ; CHECK-NEXT:    stw 0, 52(1)
-; CHECK-NEXT:    evstdd 29, 24(1) # 8-byte Folded Spill
-; CHECK-NEXT:    evstdd 30, 32(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 29, 8(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 30, 16(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evlddx 30, 4, 3
 ; CHECK-NEXT:    # implicit-def: $r3
 ; CHECK-NEXT:    evlddx 29, 6, 5
-; CHECK-NEXT:    evstdd 28, 16(1) # 8-byte Folded Spill
+; CHECK-NEXT:    stw 28, 32(1) # 4-byte Folded Spill
 ; CHECK-NEXT:    # implicit-def: $r28
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB1_1: # %bb1
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    efdcfsi 8, 3
-; CHECK-NEXT:    mr 4, 30
-; CHECK-NEXT:    mr 6, 29
 ; CHECK-NEXT:    evmergehi 3, 30, 30
 ; CHECK-NEXT:    evmergehi 5, 29, 29
-; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; CHECK-NEXT:    # kill: def $r5 killed $r5 killed $s5
+; CHECK-NEXT:    mr 4, 30
+; CHECK-NEXT:    mr 6, 29
 ; CHECK-NEXT:    evmergehi 7, 8, 8
-; CHECK-NEXT:    # kill: def $r8 killed $r8 killed $s8
-; CHECK-NEXT:    # kill: def $r7 killed $r7 killed $s7
 ; CHECK-NEXT:    bl fma
 ; CHECK-NEXT:    evmergelo 3, 3, 4
 ; CHECK-NEXT:    addi 28, 28, -1
 ; CHECK-NEXT:    cmplwi 28, 0
 ; CHECK-NEXT:    efdctsiz 3, 3
 ; CHECK-NEXT:    bc 12, 1, .LBB1_1
 ; CHECK-NEXT:  # %bb.2: # %bb8
 ; CHECK-NEXT:    bl wibble
-; CHECK-NEXT:    evldd 30, 32(1) # 8-byte Folded Reload
-; CHECK-NEXT:    evldd 29, 24(1) # 8-byte Folded Reload
-; CHECK-NEXT:    evldd 28, 16(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 30, 16(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 29, 8(1) # 8-byte Folded Reload
+; CHECK-NEXT:    lwz 28, 32(1) # 4-byte Folded Reload
 ; CHECK-NEXT:    lwz 0, 52(1)
 ; CHECK-NEXT:    addi 1, 1, 48
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 bb:
   br label %bb1
 
 bb1:

llvm/test/CodeGen/PowerPC/spe.ll

 
 define double @test_ddiv(double %a, double %b) #0 {
 ; SPE-LABEL: test_ddiv:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    evmergelo 5, 5, 6
 ; SPE-NEXT:    evmergelo 3, 3, 4
 ; SPE-NEXT:    efddiv 4, 3, 5
 ; SPE-NEXT:    evmergehi 3, 4, 4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_ddiv:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
 ; EFPU2-NEXT:    stwu 1, -16(1)
 ; EFPU2-NEXT:    stw 0, 20(1)
 ; EFPU2-NEXT:    bl __divdf3

 
 define double @test_dmul(double %a, double %b) #0 {
 ; SPE-LABEL: test_dmul:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    evmergelo 5, 5, 6
 ; SPE-NEXT:    evmergelo 3, 3, 4
 ; SPE-NEXT:    efdmul 4, 3, 5
 ; SPE-NEXT:    evmergehi 3, 4, 4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_dmul:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
 ; EFPU2-NEXT:    stwu 1, -16(1)
 ; EFPU2-NEXT:    stw 0, 20(1)
 ; EFPU2-NEXT:    bl __muldf3
 ; EFPU2-NEXT:    lwz 0, 20(1)
 ; EFPU2-NEXT:    addi 1, 1, 16
 ; EFPU2-NEXT:    mtlr 0
 ; EFPU2-NEXT:    blr
   entry:
   %v = fmul double %a, %b
   ret double %v
 }
 
 define double @test_dadd(double %a, double %b) #0 {
 ; SPE-LABEL: test_dadd:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    evmergelo 5, 5, 6
 ; SPE-NEXT:    evmergelo 3, 3, 4
 ; SPE-NEXT:    efdadd 4, 3, 5
 ; SPE-NEXT:    evmergehi 3, 4, 4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_dadd:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
 ; EFPU2-NEXT:    stwu 1, -16(1)
 ; EFPU2-NEXT:    stw 0, 20(1)
 ; EFPU2-NEXT:    bl __adddf3
 ; EFPU2-NEXT:    lwz 0, 20(1)
 ; EFPU2-NEXT:    addi 1, 1, 16
 ; EFPU2-NEXT:    mtlr 0
 ; EFPU2-NEXT:    blr
   entry:
   %v = fadd double %a, %b
   ret double %v
 }
 
 define double @test_dsub(double %a, double %b) #0 {
 ; SPE-LABEL: test_dsub:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    evmergelo 5, 5, 6
 ; SPE-NEXT:    evmergelo 3, 3, 4
 ; SPE-NEXT:    efdsub 4, 3, 5
 ; SPE-NEXT:    evmergehi 3, 4, 4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_dsub:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
 ; EFPU2-NEXT:    stwu 1, -16(1)
 ; EFPU2-NEXT:    stw 0, 20(1)
 ; EFPU2-NEXT:    bl __subdf3
 ; EFPU2-NEXT:    lwz 0, 20(1)
 ; EFPU2-NEXT:    addi 1, 1, 16
 ; EFPU2-NEXT:    mtlr 0
 ; EFPU2-NEXT:    blr
   entry:
   %v = fsub double %a, %b
   ret double %v
 }
 
 define double @test_dneg(double %a) #0 {
 ; SPE-LABEL: test_dneg:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    evmergelo 3, 3, 4
 ; SPE-NEXT:    efdneg 4, 3
 ; SPE-NEXT:    evmergehi 3, 4, 4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_dneg:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    xoris 3, 3, 32768
 ; EFPU2-NEXT:    blr
   entry:
   %v = fsub double -0.0, %a
   ret double %v
 }
 
 define double @test_stod(float %a) #0 {
 ; SPE-LABEL: test_stod:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    efdcfs 4, 3
 ; SPE-NEXT:    evmergehi 3, 4, 4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_stod:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
 ; EFPU2-NEXT:    stwu 1, -16(1)
 ; EFPU2-NEXT:    stw 0, 20(1)
 ; EFPU2-NEXT:    bl __extendsfdf2

 ; SPE-NEXT:    stw 3, 12(1)
 ; SPE-NEXT:    lwz 3, 12(1)
 ; SPE-NEXT:    addi 1, 1, 16
 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_dcmpueq:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
-; EFPU2-NEXT:    stwu 1, -80(1)
+; EFPU2-NEXT:    stwu 1, -48(1)
 ; EFPU2-NEXT:    mfcr 12
-; EFPU2-NEXT:    stw 0, 84(1)
-; EFPU2-NEXT:    stw 12, 76(1)
-; EFPU2-NEXT:    evstdd 27, 24(1) # 8-byte Folded Spill
+; EFPU2-NEXT:    stw 0, 52(1)
+; EFPU2-NEXT:    stw 12, 24(1)
+; EFPU2-NEXT:    stw 27, 28(1) # 4-byte Folded Spill
 ; EFPU2-NEXT:    mr 27, 3
-; EFPU2-NEXT:    evstdd 28, 32(1) # 8-byte Folded Spill
+; EFPU2-NEXT:    stw 28, 32(1) # 4-byte Folded Spill
 ; EFPU2-NEXT:    mr 28, 4
-; EFPU2-NEXT:    evstdd 29, 40(1) # 8-byte Folded Spill
+; EFPU2-NEXT:    stw 29, 36(1) # 4-byte Folded Spill
 ; EFPU2-NEXT:    mr 29, 5
-; EFPU2-NEXT:    evstdd 30, 48(1) # 8-byte Folded Spill
+; EFPU2-NEXT:    stw 30, 40(1) # 4-byte Folded Spill
 ; EFPU2-NEXT:    mr 30, 6
 ; EFPU2-NEXT:    bl __eqdf2
 ; EFPU2-NEXT:    cmpwi 2, 3, 0
 ; EFPU2-NEXT:    mr 3, 27
 ; EFPU2-NEXT:    mr 4, 28
 ; EFPU2-NEXT:    mr 5, 29
 ; EFPU2-NEXT:    mr 6, 30
 ; EFPU2-NEXT:    bl __unorddf2
 ; EFPU2-NEXT:    bc 12, 10, .LBB42_3
 ; EFPU2-NEXT:  # %bb.1: # %entry
 ; EFPU2-NEXT:    cmpwi 3, 0
 ; EFPU2-NEXT:    bc 4, 2, .LBB42_3
 ; EFPU2-NEXT:  # %bb.2: # %fa
 ; EFPU2-NEXT:    li 3, 0
 ; EFPU2-NEXT:    b .LBB42_4
 ; EFPU2-NEXT:  .LBB42_3: # %tr
 ; EFPU2-NEXT:    li 3, 1
 ; EFPU2-NEXT:  .LBB42_4: # %ret
 ; EFPU2-NEXT:    stw 3, 20(1)
 ; EFPU2-NEXT:    lwz 3, 20(1)
-; EFPU2-NEXT:    evldd 30, 48(1) # 8-byte Folded Reload
-; EFPU2-NEXT:    evldd 29, 40(1) # 8-byte Folded Reload
-; EFPU2-NEXT:    evldd 28, 32(1) # 8-byte Folded Reload
-; EFPU2-NEXT:    lwz 12, 76(1)
-; EFPU2-NEXT:    evldd 27, 24(1) # 8-byte Folded Reload
+; EFPU2-NEXT:    lwz 30, 40(1) # 4-byte Folded Reload
+; EFPU2-NEXT:    lwz 29, 36(1) # 4-byte Folded Reload
+; EFPU2-NEXT:    lwz 28, 32(1) # 4-byte Folded Reload
+; EFPU2-NEXT:    lwz 12, 24(1)
+; EFPU2-NEXT:    lwz 27, 28(1) # 4-byte Folded Reload
 ; EFPU2-NEXT:    mtcrf 32, 12 # cr2
-; EFPU2-NEXT:    lwz 0, 84(1)
-; EFPU2-NEXT:    addi 1, 1, 80
+; EFPU2-NEXT:    lwz 0, 52(1)
+; EFPU2-NEXT:    addi 1, 1, 48
 ; EFPU2-NEXT:    mtlr 0
 ; EFPU2-NEXT:    blr
   entry:
   %r = alloca i32, align 4
   %c = fcmp ueq double %a, %b
   br i1 %c, label %tr, label %fa
 tr:
   store i32 1, ptr %r, align 4

 ; SPE-NEXT:    blr
 ; SPE-NEXT:  .LBB43_2: # %entry
 ; SPE-NEXT:    li 3, 0
 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_dcmpne:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
-; EFPU2-NEXT:    stwu 1, -80(1)
+; EFPU2-NEXT:    stwu 1, -48(1)
 ; EFPU2-NEXT:    mfcr 12
-; EFPU2-NEXT:    stw 0, 84(1)
-; EFPU2-NEXT:    stw 12, 76(1)
-; EFPU2-NEXT:    evstdd 27, 24(1) # 8-byte Folded Spill
+; EFPU2-NEXT:    stw 0, 52(1)
+; EFPU2-NEXT:    stw 12, 24(1)
+; EFPU2-NEXT:    stw 27, 28(1) # 4-byte Folded Spill
 ; EFPU2-NEXT:    mr 27, 3
-; EFPU2-NEXT:    evstdd 28, 32(1) # 8-byte Folded Spill
+; EFPU2-NEXT:    stw 28, 32(1) # 4-byte Folded Spill
 ; EFPU2-NEXT:    mr 28, 4
-; EFPU2-NEXT:    evstdd 29, 40(1) # 8-byte Folded Spill
+; EFPU2-NEXT:    stw 29, 36(1) # 4-byte Folded Spill
 ; EFPU2-NEXT:    mr 29, 5
-; EFPU2-NEXT:    evstdd 30, 48(1) # 8-byte Folded Spill
+; EFPU2-NEXT:    stw 30, 40(1) # 4-byte Folded Spill
 ; EFPU2-NEXT:    mr 30, 6
 ; EFPU2-NEXT:    bl __unorddf2
 ; EFPU2-NEXT:    cmpwi 2, 3, 0
 ; EFPU2-NEXT:    mr 3, 27
 ; EFPU2-NEXT:    mr 4, 28
 ; EFPU2-NEXT:    mr 5, 29
 ; EFPU2-NEXT:    mr 6, 30
 ; EFPU2-NEXT:    bl __eqdf2
-; EFPU2-NEXT:    evldd 30, 48(1) # 8-byte Folded Reload
+; EFPU2-NEXT:    lwz 30, 40(1) # 4-byte Folded Reload
 ; EFPU2-NEXT:    cmpwi 3, 0
-; EFPU2-NEXT:    evldd 29, 40(1) # 8-byte Folded Reload
+; EFPU2-NEXT:    lwz 29, 36(1) # 4-byte Folded Reload
 ; EFPU2-NEXT:    li 4, 1
-; EFPU2-NEXT:    evldd 28, 32(1) # 8-byte Folded Reload
+; EFPU2-NEXT:    lwz 28, 32(1) # 4-byte Folded Reload
 ; EFPU2-NEXT:    crorc 20, 2, 10
-; EFPU2-NEXT:    lwz 12, 76(1)
+; EFPU2-NEXT:    lwz 12, 24(1)
 ; EFPU2-NEXT:    bc 12, 20, .LBB43_2
 ; EFPU2-NEXT:  # %bb.1: # %entry
 ; EFPU2-NEXT:    ori 3, 4, 0
 ; EFPU2-NEXT:    b .LBB43_3
 ; EFPU2-NEXT:  .LBB43_2: # %entry
 ; EFPU2-NEXT:    li 3, 0
 ; EFPU2-NEXT:  .LBB43_3: # %entry
-; EFPU2-NEXT:    evldd 27, 24(1) # 8-byte Folded Reload
+; EFPU2-NEXT:    lwz 27, 28(1) # 4-byte Folded Reload
 ; EFPU2-NEXT:    mtcrf 32, 12 # cr2
-; EFPU2-NEXT:    lwz 0, 84(1)
-; EFPU2-NEXT:    addi 1, 1, 80
+; EFPU2-NEXT:    lwz 0, 52(1)
+; EFPU2-NEXT:    addi 1, 1, 48
 ; EFPU2-NEXT:    mtlr 0
 ; EFPU2-NEXT:    blr
   entry:
   %r = fcmp one double %a, %b
   ret i1 %r
 }
 
 define i32 @test_dcmpune(double %a, double %b) #0 {

 ; SPE-NEXT:    andi. 7, 7, 1
 ; SPE-NEXT:    evmergelo 5, 5, 6
 ; SPE-NEXT:    evmergelo 4, 3, 4
 ; SPE-NEXT:    bc 12, 1, .LBB49_2
 ; SPE-NEXT:  # %bb.1: # %entry
 ; SPE-NEXT:    evor 4, 5, 5
 ; SPE-NEXT:  .LBB49_2: # %entry
 ; SPE-NEXT:    evmergehi 3, 4, 4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_dselect:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    andi. 7, 7, 1
 ; EFPU2-NEXT:    bclr 12, 1, 0
 ; EFPU2-NEXT:  # %bb.1: # %entry
 ; EFPU2-NEXT:    ori 3, 5, 0
entry:
   ret i32 %v
 }
 
 define double @test_dfromui(i32 %a) #0 {
 ; SPE-LABEL: test_dfromui:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    efdcfui 4, 3
 ; SPE-NEXT:    evmergehi 3, 4, 4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_dfromui:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
 ; EFPU2-NEXT:    stwu 1, -16(1)
 ; EFPU2-NEXT:    stw 0, 20(1)
 ; EFPU2-NEXT:    bl __floatunsidf
 ; EFPU2-NEXT:    lwz 0, 20(1)
 ; EFPU2-NEXT:    addi 1, 1, 16
 ; EFPU2-NEXT:    mtlr 0
 ; EFPU2-NEXT:    blr
 entry:
   %v = uitofp i32 %a to double
   ret double %v
 }
 
 define double @test_dfromsi(i32 %a) #0 {
 ; SPE-LABEL: test_dfromsi:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    efdcfsi 4, 3
 ; SPE-NEXT:    evmergehi 3, 4, 4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_dfromsi:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
 ; EFPU2-NEXT:    stwu 1, -16(1)
 ; EFPU2-NEXT:    stw 0, 20(1)
 ; EFPU2-NEXT:    bl __floatsidf

 ; SPE-NEXT:    addi 3, 1, 32
 ; SPE-NEXT:    li 4, 0
 ; SPE-NEXT:    li 5, 20
 ; SPE-NEXT:    li 6, 1
 ; SPE-NEXT:    bl test_memset
 ; SPE-NEXT:    evldd 4, 24(1) # 8-byte Folded Reload
 ; SPE-NEXT:    li 5, 256
 ; SPE-NEXT:    evmergehi 3, 4, 4
-; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
 ; SPE-NEXT:    evlddx 30, 1, 5 # 8-byte Folded Reload
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    evldd 29, 248(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 28, 240(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 27, 232(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 26, 224(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 25, 216(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 24, 208(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 23, 200(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 22, 192(1) # 8-byte Folded Reload

 ; SPE-NEXT:    lwz 0, 292(1)
 ; SPE-NEXT:    addi 1, 1, 288
 ; SPE-NEXT:    mtlr 0
 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: test_spill:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
-; EFPU2-NEXT:    stwu 1, -144(1)
+; EFPU2-NEXT:    stwu 1, -128(1)
 ; EFPU2-NEXT:    mr 5, 3
 ; EFPU2-NEXT:    mr 6, 4
-; EFPU2-NEXT:    stw 0, 148(1)
-; EFPU2-NEXT:    evstdd 27, 104(1) # 8-byte Folded Spill
-; EFPU2-NEXT:    evstdd 28, 112(1) # 8-byte Folded Spill
-; EFPU2-NEXT:    evstdd 29, 120(1) # 8-byte Folded Spill
-; EFPU2-NEXT:    evstdd 30, 128(1) # 8-byte Folded Spill
-; EFPU2-NEXT:    lwz 28, 152(1)
+; EFPU2-NEXT:    stw 0, 132(1)
+; EFPU2-NEXT:    stw 27, 108(1) # 4-byte Folded Spill
+; EFPU2-NEXT:    stw 28, 112(1) # 4-byte Folded Spill
+; EFPU2-NEXT:    stw 29, 116(1) # 4-byte Folded Spill
+; EFPU2-NEXT:    stw 30, 120(1) # 4-byte Folded Spill
+; EFPU2-NEXT:    lwz 28, 136(1)
 ; EFPU2-NEXT:    bl __adddf3
 ; EFPU2-NEXT:    lis 5, 16393
 ; EFPU2-NEXT:    lis 6, -4069
 ; EFPU2-NEXT:    ori 5, 5, 8697
 ; EFPU2-NEXT:    ori 6, 6, 34414
 ; EFPU2-NEXT:    #APP
 ; EFPU2-NEXT:    #NO_APP
 ; EFPU2-NEXT:    bl __adddf3
 ; EFPU2-NEXT:    mr 30, 3
 ; EFPU2-NEXT:    mr 29, 4
-; EFPU2-NEXT:    addi 3, 1, 52
+; EFPU2-NEXT:    addi 3, 1, 56
 ; EFPU2-NEXT:    li 4, 0
 ; EFPU2-NEXT:    li 5, 24
 ; EFPU2-NEXT:    li 6, 1
 ; EFPU2-NEXT:    li 27, 0
 ; EFPU2-NEXT:    bl test_memset
 ; EFPU2-NEXT:    stw 27, 0(28)
 ; EFPU2-NEXT:    bl test_func2
-; EFPU2-NEXT:    addi 3, 1, 8
+; EFPU2-NEXT:    addi 3, 1, 12
 ; EFPU2-NEXT:    li 4, 0
 ; EFPU2-NEXT:    li 5, 20
 ; EFPU2-NEXT:    li 6, 1
 ; EFPU2-NEXT:    bl test_memset
 ; EFPU2-NEXT:    mr 3, 30
 ; EFPU2-NEXT:    mr 4, 29
-; EFPU2-NEXT:    evldd 30, 128(1) # 8-byte Folded Reload
-; EFPU2-NEXT:    evldd 29, 120(1) # 8-byte Folded Reload
-; EFPU2-NEXT:    evldd 28, 112(1) # 8-byte Folded Reload
-; EFPU2-NEXT:    evldd 27, 104(1) # 8-byte Folded Reload
-; EFPU2-NEXT:    lwz 0, 148(1)
-; EFPU2-NEXT:    addi 1, 1, 144
+; EFPU2-NEXT:    lwz 30, 120(1) # 4-byte Folded Reload
+; EFPU2-NEXT:    lwz 29, 116(1) # 4-byte Folded Reload
+; EFPU2-NEXT:    lwz 28, 112(1) # 4-byte Folded Reload
+; EFPU2-NEXT:    lwz 27, 108(1) # 4-byte Folded Reload
+; EFPU2-NEXT:    lwz 0, 132(1)
+; EFPU2-NEXT:    addi 1, 1, 128
 ; EFPU2-NEXT:    mtlr 0
 ; EFPU2-NEXT:    blr
 entry:
   %v1 = alloca [13 x i32], align 4
   %v2 = alloca [11 x i32], align 4
   %0 = fadd double %a, %a
   call void asm sideeffect "","~{s0},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"() nounwind
   %1 = fadd double %0, 3.14159

 
 define dso_local float @test_fma(i32 %d) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_fma:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stwu 1, -32(1)
 ; CHECK-NEXT:    cmpwi 3, 0
 ; CHECK-NEXT:    stw 0, 36(1)
-; CHECK-NEXT:    evstdd 29, 8(1) # 8-byte Folded Spill
-; CHECK-NEXT:    evstdd 30, 16(1) # 8-byte Folded Spill
+; CHECK-NEXT:    stw 29, 20(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 30, 24(1) # 4-byte Folded Spill
 ; CHECK-NEXT:    ble 0, .LBB56_3
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    mr 30, 3
 ; CHECK-NEXT:    li 29, 0
 ; CHECK-NEXT:    # implicit-def: $r5
 ; CHECK-NEXT:  .LBB56_2: # %for.body
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    efscfsi 3, 29
 ; CHECK-NEXT:    mr 4, 3
 ; CHECK-NEXT:    bl fmaf
 ; CHECK-NEXT:    addi 30, 30, -1
 ; CHECK-NEXT:    mr 5, 3
 ; CHECK-NEXT:    cmplwi 30, 0
 ; CHECK-NEXT:    addi 29, 29, 1
 ; CHECK-NEXT:    bc 12, 1, .LBB56_2
 ; CHECK-NEXT:    b .LBB56_4
 ; CHECK-NEXT:  .LBB56_3:
 ; CHECK-NEXT:    # implicit-def: $r5
 ; CHECK-NEXT:  .LBB56_4: # %for.cond.cleanup
 ; CHECK-NEXT:    mr 3, 5
-; CHECK-NEXT:    evldd 30, 16(1) # 8-byte Folded Reload
-; CHECK-NEXT:    evldd 29, 8(1) # 8-byte Folded Reload
+; CHECK-NEXT:    lwz 30, 24(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 29, 20(1) # 4-byte Folded Reload
 ; CHECK-NEXT:    lwz 0, 36(1)
 ; CHECK-NEXT:    addi 1, 1, 32
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 entry:
   %cmp8 = icmp sgt i32 %d, 0
   br i1 %cmp8, label %for.body, label %for.cond.cleanup
 

 define void @d(ptr %e, ptr %f) #0 {
 ; SPE-LABEL: d:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    mflr 0
 ; SPE-NEXT:    stwu 1, -48(1)
 ; SPE-NEXT:    stw 0, 52(1)
 ; SPE-NEXT:    lwz 4, 0(4)
 ; SPE-NEXT:    lwz 3, 0(3)
-; SPE-NEXT:    evstdd 29, 24(1) # 8-byte Folded Spill
+; SPE-NEXT:    evstdd 29, 8(1) # 8-byte Folded Spill
 ; SPE-NEXT:    efdcfs 29, 4
-; SPE-NEXT:    evstdd 28, 16(1) # 8-byte Folded Spill
+; SPE-NEXT:    stw 28, 32(1) # 4-byte Folded Spill
 ; SPE-NEXT:    mr 4, 29
-; SPE-NEXT:    evstdd 30, 32(1) # 8-byte Folded Spill
+; SPE-NEXT:    evstdd 30, 16(1) # 8-byte Folded Spill
 ; SPE-NEXT:    efdcfs 30, 3
 ; SPE-NEXT:    evmergehi 3, 29, 29
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    bl foo
 ; SPE-NEXT:    mr 28, 3
 ; SPE-NEXT:    evmergehi 3, 30, 30
 ; SPE-NEXT:    mr 4, 30
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    bl foo
 ; SPE-NEXT:    efdcfsi 3, 28
-; SPE-NEXT:    evldd 30, 32(1) # 8-byte Folded Reload
+; SPE-NEXT:    evldd 30, 16(1) # 8-byte Folded Reload
 ; SPE-NEXT:    efdmul 3, 29, 3
 ; SPE-NEXT:    efscfd 3, 3
-; SPE-NEXT:    evldd 29, 24(1) # 8-byte Folded Reload
+; SPE-NEXT:    evldd 29, 8(1) # 8-byte Folded Reload
 ; SPE-NEXT:    stw 3, 0(3)
-; SPE-NEXT:    evldd 28, 16(1) # 8-byte Folded Reload
+; SPE-NEXT:    lwz 28, 32(1) # 4-byte Folded Reload
 ; SPE-NEXT:    lwz 0, 52(1)
 ; SPE-NEXT:    addi 1, 1, 48
 ; SPE-NEXT:    mtlr 0
 ; SPE-NEXT:    blr
 ;
 ; EFPU2-LABEL: d:
 ; EFPU2:       # %bb.0: # %entry
 ; EFPU2-NEXT:    mflr 0
-; EFPU2-NEXT:    stwu 1, -64(1)
-; EFPU2-NEXT:    stw 0, 68(1)
+; EFPU2-NEXT:    stwu 1, -32(1)
+; EFPU2-NEXT:    stw 0, 36(1)
 ; EFPU2-NEXT:    lwz 3, 0(3)
-; EFPU2-NEXT:    evstdd 26, 16(1) # 8-byte Folded Spill
-; EFPU2-NEXT:    evstdd 27, 24(1) # 8-byte Folded Spill
-; EFPU2-NEXT:    evstdd 28, 32(1) # 8-byte Folded Spill
-; EFPU2-NEXT:    evstdd 29, 40(1) # 8-byte Folded Spill
-; EFPU2-NEXT:    evstdd 30, 48(1) # 8-byte Folded Spill
+; EFPU2-NEXT:    stw 26, 8(1) # 4-byte Folded Spill
+; EFPU2-NEXT:    stw 27, 12(1) # 4-byte Folded Spill
+; EFPU2-NEXT:    stw 28, 16(1) # 4-byte Folded Spill
+; EFPU2-NEXT:    stw 29, 20(1) # 4-byte Folded Spill
+; EFPU2-NEXT:    stw 30, 24(1) # 4-byte Folded Spill
 ; EFPU2-NEXT:    mr 30, 4
 ; EFPU2-NEXT:    bl __extendsfdf2
 ; EFPU2-NEXT:    mr 28, 3
 ; EFPU2-NEXT:    lwz 3, 0(30)
 ; EFPU2-NEXT:    mr 29, 4
 ; EFPU2-NEXT:    bl __extendsfdf2
 ; EFPU2-NEXT:    mr 30, 4
 ; EFPU2-NEXT:    mr 27, 3
 ; EFPU2-NEXT:    bl foo
 ; EFPU2-NEXT:    mr 26, 3
 ; EFPU2-NEXT:    mr 3, 28
 ; EFPU2-NEXT:    mr 4, 29
 ; EFPU2-NEXT:    bl foo
 ; EFPU2-NEXT:    mr 3, 26
 ; EFPU2-NEXT:    bl __floatsidf
 ; EFPU2-NEXT:    mr 6, 4
 ; EFPU2-NEXT:    mr 5, 3
 ; EFPU2-NEXT:    mr 3, 27
 ; EFPU2-NEXT:    mr 4, 30
 ; EFPU2-NEXT:    bl __muldf3
 ; EFPU2-NEXT:    bl __truncdfsf2
 ; EFPU2-NEXT:    stw 3, 0(3)
-; EFPU2-NEXT:    evldd 30, 48(1) # 8-byte Folded Reload
-; EFPU2-NEXT:    evldd 29, 40(1) # 8-byte Folded Reload
-; EFPU2-NEXT:    evldd 28, 32(1) # 8-byte Folded Reload
-; EFPU2-NEXT:    evldd 27, 24(1) # 8-byte Folded Reload
-; EFPU2-NEXT:    evldd 26, 16(1) # 8-byte Folded Reload
-; EFPU2-NEXT:    lwz 0, 68(1)
-; EFPU2-NEXT:    addi 1, 1, 64
+; EFPU2-NEXT:    lwz 30, 24(1) # 4-byte Folded Reload
+; EFPU2-NEXT:    lwz 29, 20(1) # 4-byte Folded Reload
+; EFPU2-NEXT:    lwz 28, 16(1) # 4-byte Folded Reload
+; EFPU2-NEXT:    lwz 27, 12(1) # 4-byte Folded Reload
+; EFPU2-NEXT:    lwz 26, 8(1) # 4-byte Folded Reload
+; EFPU2-NEXT:    lwz 0, 36(1)
+; EFPU2-NEXT:    addi 1, 1, 32
 ; EFPU2-NEXT:    mtlr 0
 ; EFPU2-NEXT:    blr
 entry:
   %0 = load float, ptr undef
   %conv = fpext float %0 to double
   %1 = load float, ptr %f
   %g = fpext float %1 to double
   %2 = call i32 @foo(double %g)
   %h = call i32 @foo(double %conv)
   %n = sitofp i32 %2 to double
   %k = fmul double %g, %n
   %l = fptrunc double %k to float
   store float %l, ptr undef
   ret void
 }
 attributes #0 = { nounwind }