[RISCV] Use PACK in RISCVMatInt for constants that have the same lower and upper 32 bits.

[craig.topper]

Summary

This requires Zbkb.

[reames]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

253

"The pack instruction packs the XLEN/2-bit lower halves of rs1 and rs2 into rd, with rs1 in the lower half and
rs2 in the upper half."

I think what you have happens to work since we can always generate a 2 instruction sequence for XLEN=32. Can you add an assert which shows we only hit this on 64 bit?

[craig.topper]

Add description of pack.

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

253

I think the 64 bit comment is better addressed by D152300

[reames]

LGTM

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

if (LeadingZeros == 32 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
       TmpSeq.emplace_back(RISCV::ADD_UW, 0);
 
       // Keep the new sequence if it is an improvement.
       if (TmpSeq.size() < Res.size())
         Res = TmpSeq;
     }
   }
 
+  // If the Low and High halves are the same, use pack. The pack instruction
+  // packs the XLEN/2-bit lower halves of rs1 and rs2 into rd, with rs1 in the
+  // lower half and rs2 in the upper half.
+  if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbkb]) {
+    int64_t LoVal = SignExtend64<32>(Val);
+    int64_t HiVal = SignExtend64<32>(Val >> 32);
+    if (LoVal == HiVal) {
+      RISCVMatInt::InstSeq TmpSeq;
+      generateInstSeqImpl(LoVal, ActiveFeatures, TmpSeq);
+      TmpSeq.emplace_back(RISCV::PACK, 0);
+      if (TmpSeq.size() < Res.size())
+        Res = TmpSeq;
+    }
+  }
+
   // Perform optimization with BCLRI/BSETI in the Zbs extension.
   if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbs]) {
     // 1. For values in range 0xffffffff 7fffffff ~ 0xffffffff 00000000,
     //    call generateInstSeqImpl with Val|0x80000000 (which is expected be
     //    an int32), then emit (BCLRI r, 31).
     // 2. For values in range 0x80000000 ~ 0xffffffff, call generateInstSeqImpl
     //    with Val&~0x80000000 (which is expected to be an int32), then
     //    emit (BSETI r, 31).
default:
     llvm_unreachable("Unexpected opcode!");
   case RISCV::LUI:
     return RISCVMatInt::Imm;
   case RISCV::ADD_UW:
     return RISCVMatInt::RegX0;
   case RISCV::SH1ADD:
   case RISCV::SH2ADD:
   case RISCV::SH3ADD:
+  case RISCV::PACK:
     return RISCVMatInt::RegReg;
   case RISCV::ADDI:
   case RISCV::ADDIW:
   case RISCV::SLLI:
   case RISCV::SRLI:
   case RISCV::SLLI_UW:
   case RISCV::RORI:
   case RISCV::BSETI:
   case RISCV::BCLRI:
   case RISCV::TH_SRRI:
     return RISCVMatInt::RegImm;
   }
 }
 
 } // namespace llvm::RISCVMatInt

llvm/test/CodeGen/RISCV/rv64zbkb.ll

 ; RV64ZBKB-NEXT:    ret
   %4 = add i16 %1, %0
   %5 = zext i16 %4 to i32
   %6 = shl i32 %5, 16
   %7 = zext i16 %2 to i32
   %8 = or i32 %6, %7
   ret i32 %8
 }
+
+define i64 @pack_i64_imm() {
+; RV64I-LABEL: pack_i64_imm:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a0, 65793
+; RV64I-NEXT:    addiw a0, a0, 16
+; RV64I-NEXT:    slli a1, a0, 32
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64ZBKB-LABEL: pack_i64_imm:
+; RV64ZBKB:       # %bb.0:
+; RV64ZBKB-NEXT:    lui a0, 65793
+; RV64ZBKB-NEXT:    addiw a0, a0, 16
+; RV64ZBKB-NEXT:    pack a0, a0, a0
+; RV64ZBKB-NEXT:    ret
+  ret i64 1157442765409226768 ; 0x0101010101010101
+}