Switch tests to use update_llc_test_checks

[MatzeB]

Summary

Switch and update some tests to use update_llc_test_checks to reduce clutter in upcoming change.

[thegameg]

LG

llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll

 ; Epilogue code. (What we pop does not matter.)
 ; mov sp, r7
 ; add sp,
 ; pop {r7, pc}
 ;
 ; bx lr
 define i32 @foo(i32 %a, i32 %b) "frame-pointer"="all" {
 ; ARM-ENABLE-LABEL: foo:
-; ARM-ENABLE:       @ %bb.0:
+; ARM-ENABLE:       Lfunc_begin0:
+; ARM-ENABLE-NEXT:  @ %bb.0:
 ; ARM-ENABLE-NEXT:    cmp r0, r1
 ; ARM-ENABLE-NEXT:    bge LBB0_2
 ; ARM-ENABLE-NEXT:  @ %bb.1: @ %true
 ; ARM-ENABLE-NEXT:    push {r7, lr}
 ; ARM-ENABLE-NEXT:    mov r7, sp
 ; ARM-ENABLE-NEXT:    push {r0}
 ; ARM-ENABLE-NEXT:    mov r1, sp
 ; ARM-ENABLE-NEXT:    mov r0, #0
 ; ARM-ENABLE-NEXT:    bl _doSomething
 ; ARM-ENABLE-NEXT:    mov sp, r7
 ; ARM-ENABLE-NEXT:    pop {r7, lr}
 ; ARM-ENABLE-NEXT:  LBB0_2: @ %false
 ; ARM-ENABLE-NEXT:    bx lr
+; ARM-ENABLE-NEXT:  Lfunc_end0:
 ;
 ; ARM-DISABLE-LABEL: foo:
-; ARM-DISABLE:       @ %bb.0:
+; ARM-DISABLE:       Lfunc_begin0:
+; ARM-DISABLE-NEXT:  @ %bb.0:
 ; ARM-DISABLE-NEXT:    push {r7, lr}
 ; ARM-DISABLE-NEXT:    mov r7, sp
 ; ARM-DISABLE-NEXT:    sub sp, sp, #4
 ; ARM-DISABLE-NEXT:    cmp r0, r1
 ; ARM-DISABLE-NEXT:    bge LBB0_2
 ; ARM-DISABLE-NEXT:  @ %bb.1: @ %true
 ; ARM-DISABLE-NEXT:    str r0, [sp]
 ; ARM-DISABLE-NEXT:    mov r1, sp
 ; ARM-DISABLE-NEXT:    mov r0, #0
 ; ARM-DISABLE-NEXT:    bl _doSomething
 ; ARM-DISABLE-NEXT:  LBB0_2: @ %false
 ; ARM-DISABLE-NEXT:    mov sp, r7
 ; ARM-DISABLE-NEXT:    pop {r7, pc}
+; ARM-DISABLE-NEXT:  Lfunc_end0:
 ;
 ; THUMB-ENABLE-LABEL: foo:
-; THUMB-ENABLE:       @ %bb.0:
+; THUMB-ENABLE:       Lfunc_begin0:
+; THUMB-ENABLE-NEXT:  @ %bb.0:
 ; THUMB-ENABLE-NEXT:    cmp r0, r1
 ; THUMB-ENABLE-NEXT:    bge LBB0_2
 ; THUMB-ENABLE-NEXT:  @ %bb.1: @ %true
 ; THUMB-ENABLE-NEXT:    push {r7, lr}
 ; THUMB-ENABLE-NEXT:    mov r7, sp
 ; THUMB-ENABLE-NEXT:    str r0, [sp, #-4]!
 ; THUMB-ENABLE-NEXT:    mov r1, sp
 ; THUMB-ENABLE-NEXT:    movs r0, #0
 ; THUMB-ENABLE-NEXT:    bl _doSomething
 ; THUMB-ENABLE-NEXT:    add sp, #4
 ; THUMB-ENABLE-NEXT:    pop.w {r7, lr}
 ; THUMB-ENABLE-NEXT:  LBB0_2: @ %false
 ; THUMB-ENABLE-NEXT:    bx lr
+; THUMB-ENABLE-NEXT:  Lfunc_end0:
 ;
 ; THUMB-DISABLE-LABEL: foo:
-; THUMB-DISABLE:       @ %bb.0:
+; THUMB-DISABLE:       Lfunc_begin0:
+; THUMB-DISABLE-NEXT:  @ %bb.0:
 ; THUMB-DISABLE-NEXT:    push {r7, lr}
 ; THUMB-DISABLE-NEXT:    mov r7, sp
 ; THUMB-DISABLE-NEXT:    sub sp, #4
 ; THUMB-DISABLE-NEXT:    cmp r0, r1
 ; THUMB-DISABLE-NEXT:    bge LBB0_2
 ; THUMB-DISABLE-NEXT:  @ %bb.1: @ %true
 ; THUMB-DISABLE-NEXT:    str r0, [sp]
 ; THUMB-DISABLE-NEXT:    mov r1, sp
 ; THUMB-DISABLE-NEXT:    movs r0, #0
 ; THUMB-DISABLE-NEXT:    bl _doSomething
 ; THUMB-DISABLE-NEXT:  LBB0_2: @ %false
 ; THUMB-DISABLE-NEXT:    add sp, #4
 ; THUMB-DISABLE-NEXT:    pop {r7, pc}
+; THUMB-DISABLE-NEXT:  Lfunc_end0:
   %tmp = alloca i32, align 4
   %tmp2 = icmp slt i32 %a, %b
   br i1 %tmp2, label %true, label %false
 
 true:
   store i32 %a, ptr %tmp, align 4
   %tmp4 = call i32 @doSomething(i32 0, ptr %tmp)
   br label %false

 ; [[ELSE_LABEL]]: @ %if.else
 ; Shift second argument by one and store into returned register.
 ; lsl{{s?}} r0, r1, #1
 ; pop {r4, r7, pc}
 ;
 ; bx lr
 define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) "frame-pointer"="all" {
 ; ARM-ENABLE-LABEL: freqSaveAndRestoreOutsideLoop:
-; ARM-ENABLE:       @ %bb.0: @ %entry
+; ARM-ENABLE:       Lfunc_begin1:
+; ARM-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-ENABLE-NEXT:    cmp r0, #0
 ; ARM-ENABLE-NEXT:    beq LBB1_4
 ; ARM-ENABLE-NEXT:  @ %bb.1: @ %for.preheader
 ; ARM-ENABLE-NEXT:    push {r4, r7, lr}
 ; ARM-ENABLE-NEXT:    add r7, sp, #4
 ; ARM-ENABLE-NEXT:    mov r0, #0
 ; ARM-ENABLE-NEXT:    mov r1, #10
 ; ARM-ENABLE-NEXT:    @ InlineAsm Start
 ; ARM-ENABLE-NEXT:    nop
 ; ARM-ENABLE-NEXT:    @ InlineAsm End
 ; ARM-ENABLE-NEXT:  LBB1_2: @ %for.body
 ; ARM-ENABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; ARM-ENABLE-NEXT:    @ InlineAsm Start
 ; ARM-ENABLE-NEXT:    mov r2, #1
 ; ARM-ENABLE-NEXT:    @ InlineAsm End
 ; ARM-ENABLE-NEXT:    add r0, r2, r0
 ; ARM-ENABLE-NEXT:    subs r1, r1, #1
 ; ARM-ENABLE-NEXT:    bne LBB1_2
 ; ARM-ENABLE-NEXT:  @ %bb.3: @ %for.end
 ; ARM-ENABLE-NEXT:    lsl r0, r0, #3
 ; ARM-ENABLE-NEXT:    pop {r4, r7, pc}
 ; ARM-ENABLE-NEXT:  LBB1_4: @ %if.else
 ; ARM-ENABLE-NEXT:    lsl r0, r1, #1
 ; ARM-ENABLE-NEXT:    bx lr
+; ARM-ENABLE-NEXT:  Lfunc_end1:
 ;
 ; ARM-DISABLE-LABEL: freqSaveAndRestoreOutsideLoop:
-; ARM-DISABLE:       @ %bb.0: @ %entry
+; ARM-DISABLE:       Lfunc_begin1:
+; ARM-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-DISABLE-NEXT:    push {r4, r7, lr}
 ; ARM-DISABLE-NEXT:    add r7, sp, #4
 ; ARM-DISABLE-NEXT:    cmp r0, #0
 ; ARM-DISABLE-NEXT:    beq LBB1_4
 ; ARM-DISABLE-NEXT:  @ %bb.1: @ %for.preheader
 ; ARM-DISABLE-NEXT:    mov r0, #0
 ; ARM-DISABLE-NEXT:    mov r1, #10
 ; ARM-DISABLE-NEXT:    @ InlineAsm Start
 ; ARM-DISABLE-NEXT:    nop
 ; ARM-DISABLE-NEXT:    @ InlineAsm End
 ; ARM-DISABLE-NEXT:  LBB1_2: @ %for.body
 ; ARM-DISABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; ARM-DISABLE-NEXT:    @ InlineAsm Start
 ; ARM-DISABLE-NEXT:    mov r2, #1
 ; ARM-DISABLE-NEXT:    @ InlineAsm End
 ; ARM-DISABLE-NEXT:    add r0, r2, r0
 ; ARM-DISABLE-NEXT:    subs r1, r1, #1
 ; ARM-DISABLE-NEXT:    bne LBB1_2
 ; ARM-DISABLE-NEXT:  @ %bb.3: @ %for.end
 ; ARM-DISABLE-NEXT:    lsl r0, r0, #3
 ; ARM-DISABLE-NEXT:    pop {r4, r7, pc}
 ; ARM-DISABLE-NEXT:  LBB1_4: @ %if.else
 ; ARM-DISABLE-NEXT:    lsl r0, r1, #1
 ; ARM-DISABLE-NEXT:    pop {r4, r7, pc}
+; ARM-DISABLE-NEXT:  Lfunc_end1:
 ;
 ; THUMB-ENABLE-LABEL: freqSaveAndRestoreOutsideLoop:
-; THUMB-ENABLE:       @ %bb.0: @ %entry
+; THUMB-ENABLE:       Lfunc_begin1:
+; THUMB-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-ENABLE-NEXT:    cbz r0, LBB1_4
 ; THUMB-ENABLE-NEXT:  @ %bb.1: @ %for.preheader
 ; THUMB-ENABLE-NEXT:    push {r4, r7, lr}
 ; THUMB-ENABLE-NEXT:    add r7, sp, #4
 ; THUMB-ENABLE-NEXT:    movs r0, #0
 ; THUMB-ENABLE-NEXT:    movs r1, #10
 ; THUMB-ENABLE-NEXT:    @ InlineAsm Start
 ; THUMB-ENABLE-NEXT:    nop
 ; THUMB-ENABLE-NEXT:    @ InlineAsm End
 ; THUMB-ENABLE-NEXT:  LBB1_2: @ %for.body
 ; THUMB-ENABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; THUMB-ENABLE-NEXT:    @ InlineAsm Start
 ; THUMB-ENABLE-NEXT:    mov.w r2, #1
 ; THUMB-ENABLE-NEXT:    @ InlineAsm End
 ; THUMB-ENABLE-NEXT:    add r0, r2
 ; THUMB-ENABLE-NEXT:    subs r1, #1
 ; THUMB-ENABLE-NEXT:    bne LBB1_2
 ; THUMB-ENABLE-NEXT:  @ %bb.3: @ %for.end
 ; THUMB-ENABLE-NEXT:    lsls r0, r0, #3
 ; THUMB-ENABLE-NEXT:    pop {r4, r7, pc}
 ; THUMB-ENABLE-NEXT:  LBB1_4: @ %if.else
 ; THUMB-ENABLE-NEXT:    lsls r0, r1, #1
 ; THUMB-ENABLE-NEXT:    bx lr
+; THUMB-ENABLE-NEXT:  Lfunc_end1:
 ;
 ; THUMB-DISABLE-LABEL: freqSaveAndRestoreOutsideLoop:
-; THUMB-DISABLE:       @ %bb.0: @ %entry
+; THUMB-DISABLE:       Lfunc_begin1:
+; THUMB-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-DISABLE-NEXT:    push {r4, r7, lr}
 ; THUMB-DISABLE-NEXT:    add r7, sp, #4
 ; THUMB-DISABLE-NEXT:    cbz r0, LBB1_4
 ; THUMB-DISABLE-NEXT:  @ %bb.1: @ %for.preheader
 ; THUMB-DISABLE-NEXT:    movs r0, #0
 ; THUMB-DISABLE-NEXT:    movs r1, #10
 ; THUMB-DISABLE-NEXT:    @ InlineAsm Start
 ; THUMB-DISABLE-NEXT:    nop
 ; THUMB-DISABLE-NEXT:    @ InlineAsm End
 ; THUMB-DISABLE-NEXT:  LBB1_2: @ %for.body
 ; THUMB-DISABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; THUMB-DISABLE-NEXT:    @ InlineAsm Start
 ; THUMB-DISABLE-NEXT:    mov.w r2, #1
 ; THUMB-DISABLE-NEXT:    @ InlineAsm End
 ; THUMB-DISABLE-NEXT:    add r0, r2
 ; THUMB-DISABLE-NEXT:    subs r1, #1
 ; THUMB-DISABLE-NEXT:    bne LBB1_2
 ; THUMB-DISABLE-NEXT:  @ %bb.3: @ %for.end
 ; THUMB-DISABLE-NEXT:    lsls r0, r0, #3
 ; THUMB-DISABLE-NEXT:    pop {r4, r7, pc}
 ; THUMB-DISABLE-NEXT:  LBB1_4: @ %if.else
 ; THUMB-DISABLE-NEXT:    lsls r0, r1, #1
 ; THUMB-DISABLE-NEXT:    pop {r4, r7, pc}
+; THUMB-DISABLE-NEXT:  Lfunc_end1:
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %for.preheader
 
 for.preheader:
   tail call void asm "nop", ""()
   br label %for.body
 

 ; THUMB-NEXT:    subs r1, #1
 ; THUMB-NEXT:    bne LBB2_1
 ; THUMB-NEXT:  @ %bb.2: @ %for.exit
 ; THUMB-NEXT:    @ InlineAsm Start
 ; THUMB-NEXT:    nop
 ; THUMB-NEXT:    @ InlineAsm End
 ; THUMB-NEXT:    pop {r4, r7, pc}
 ; ARM-ENABLE-LABEL: freqSaveAndRestoreOutsideLoop2:
-; ARM-ENABLE:       @ %bb.0: @ %entry
+; ARM-ENABLE:       Lfunc_begin2:
+; ARM-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-ENABLE-NEXT:    push {r4, r7, lr}
 ; ARM-ENABLE-NEXT:    add r7, sp, #4
 ; ARM-ENABLE-NEXT:    mov r0, #0
 ; ARM-ENABLE-NEXT:    mov r1, #10
 ; ARM-ENABLE-NEXT:    @ InlineAsm Start
 ; ARM-ENABLE-NEXT:    nop
 ; ARM-ENABLE-NEXT:    @ InlineAsm End
 ; ARM-ENABLE-NEXT:  LBB2_1: @ %for.body
 ; ARM-ENABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; ARM-ENABLE-NEXT:    @ InlineAsm Start
 ; ARM-ENABLE-NEXT:    mov r2, #1
 ; ARM-ENABLE-NEXT:    @ InlineAsm End
 ; ARM-ENABLE-NEXT:    add r0, r2, r0
 ; ARM-ENABLE-NEXT:    subs r1, r1, #1
 ; ARM-ENABLE-NEXT:    bne LBB2_1
 ; ARM-ENABLE-NEXT:  @ %bb.2: @ %for.exit
 ; ARM-ENABLE-NEXT:    @ InlineAsm Start
 ; ARM-ENABLE-NEXT:    nop
 ; ARM-ENABLE-NEXT:    @ InlineAsm End
 ; ARM-ENABLE-NEXT:    pop {r4, r7, pc}
+; ARM-ENABLE-NEXT:  Lfunc_end2:
 ;
 ; ARM-DISABLE-LABEL: freqSaveAndRestoreOutsideLoop2:
-; ARM-DISABLE:       @ %bb.0: @ %entry
+; ARM-DISABLE:       Lfunc_begin2:
+; ARM-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-DISABLE-NEXT:    push {r4, r7, lr}
 ; ARM-DISABLE-NEXT:    add r7, sp, #4
 ; ARM-DISABLE-NEXT:    mov r0, #0
 ; ARM-DISABLE-NEXT:    mov r1, #10
 ; ARM-DISABLE-NEXT:    @ InlineAsm Start
 ; ARM-DISABLE-NEXT:    nop
 ; ARM-DISABLE-NEXT:    @ InlineAsm End
 ; ARM-DISABLE-NEXT:  LBB2_1: @ %for.body
 ; ARM-DISABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; ARM-DISABLE-NEXT:    @ InlineAsm Start
 ; ARM-DISABLE-NEXT:    mov r2, #1
 ; ARM-DISABLE-NEXT:    @ InlineAsm End
 ; ARM-DISABLE-NEXT:    add r0, r2, r0
 ; ARM-DISABLE-NEXT:    subs r1, r1, #1
 ; ARM-DISABLE-NEXT:    bne LBB2_1
 ; ARM-DISABLE-NEXT:  @ %bb.2: @ %for.exit
 ; ARM-DISABLE-NEXT:    @ InlineAsm Start
 ; ARM-DISABLE-NEXT:    nop
 ; ARM-DISABLE-NEXT:    @ InlineAsm End
 ; ARM-DISABLE-NEXT:    pop {r4, r7, pc}
+; ARM-DISABLE-NEXT:  Lfunc_end2:
 ;
 ; THUMB-ENABLE-LABEL: freqSaveAndRestoreOutsideLoop2:
-; THUMB-ENABLE:       @ %bb.0: @ %entry
+; THUMB-ENABLE:       Lfunc_begin2:
+; THUMB-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-ENABLE-NEXT:    push {r4, r7, lr}
 ; THUMB-ENABLE-NEXT:    add r7, sp, #4
 ; THUMB-ENABLE-NEXT:    movs r0, #0
 ; THUMB-ENABLE-NEXT:    movs r1, #10
 ; THUMB-ENABLE-NEXT:    @ InlineAsm Start
 ; THUMB-ENABLE-NEXT:    nop
 ; THUMB-ENABLE-NEXT:    @ InlineAsm End
 ; THUMB-ENABLE-NEXT:  LBB2_1: @ %for.body
 ; THUMB-ENABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; THUMB-ENABLE-NEXT:    @ InlineAsm Start
 ; THUMB-ENABLE-NEXT:    mov.w r2, #1
 ; THUMB-ENABLE-NEXT:    @ InlineAsm End
 ; THUMB-ENABLE-NEXT:    add r0, r2
 ; THUMB-ENABLE-NEXT:    subs r1, #1
 ; THUMB-ENABLE-NEXT:    bne LBB2_1
 ; THUMB-ENABLE-NEXT:  @ %bb.2: @ %for.exit
 ; THUMB-ENABLE-NEXT:    @ InlineAsm Start
 ; THUMB-ENABLE-NEXT:    nop
 ; THUMB-ENABLE-NEXT:    @ InlineAsm End
 ; THUMB-ENABLE-NEXT:    pop {r4, r7, pc}
+; THUMB-ENABLE-NEXT:  Lfunc_end2:
 ;
 ; THUMB-DISABLE-LABEL: freqSaveAndRestoreOutsideLoop2:
-; THUMB-DISABLE:       @ %bb.0: @ %entry
+; THUMB-DISABLE:       Lfunc_begin2:
+; THUMB-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-DISABLE-NEXT:    push {r4, r7, lr}
 ; THUMB-DISABLE-NEXT:    add r7, sp, #4
 ; THUMB-DISABLE-NEXT:    movs r0, #0
 ; THUMB-DISABLE-NEXT:    movs r1, #10
 ; THUMB-DISABLE-NEXT:    @ InlineAsm Start
 ; THUMB-DISABLE-NEXT:    nop
 ; THUMB-DISABLE-NEXT:    @ InlineAsm End
 ; THUMB-DISABLE-NEXT:  LBB2_1: @ %for.body
 ; THUMB-DISABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; THUMB-DISABLE-NEXT:    @ InlineAsm Start
 ; THUMB-DISABLE-NEXT:    mov.w r2, #1
 ; THUMB-DISABLE-NEXT:    @ InlineAsm End
 ; THUMB-DISABLE-NEXT:    add r0, r2
 ; THUMB-DISABLE-NEXT:    subs r1, #1
 ; THUMB-DISABLE-NEXT:    bne LBB2_1
 ; THUMB-DISABLE-NEXT:  @ %bb.2: @ %for.exit
 ; THUMB-DISABLE-NEXT:    @ InlineAsm Start
 ; THUMB-DISABLE-NEXT:    nop
 ; THUMB-DISABLE-NEXT:    @ InlineAsm End
 ; THUMB-DISABLE-NEXT:    pop {r4, r7, pc}
+; THUMB-DISABLE-NEXT:  Lfunc_end2:
 entry:
   br label %for.preheader
 
 for.preheader:
   tail call void asm "nop", ""()
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry

 ; [[ELSE_LABEL]]: @ %if.else
 ; Shift second argument by one and store into returned register.
 ; lsl{{s?}} r0, r1, #1
 ; pop {r4, r7, pc}
 ;
 ; bx lr
 define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) "frame-pointer"="all" {
 ; ARM-ENABLE-LABEL: loopInfoSaveOutsideLoop:
-; ARM-ENABLE:       @ %bb.0: @ %entry
+; ARM-ENABLE:       Lfunc_begin3:
+; ARM-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-ENABLE-NEXT:    cmp r0, #0
 ; ARM-ENABLE-NEXT:    beq LBB3_4
 ; ARM-ENABLE-NEXT:  @ %bb.1: @ %for.preheader
 ; ARM-ENABLE-NEXT:    push {r4, r7, lr}
 ; ARM-ENABLE-NEXT:    add r7, sp, #4
 ; ARM-ENABLE-NEXT:    mov r0, #0
 ; ARM-ENABLE-NEXT:    mov r1, #10
 ; ARM-ENABLE-NEXT:    @ InlineAsm Start

 ; ARM-ENABLE-NEXT:    lsl r0, r0, #3
 ; ARM-ENABLE-NEXT:    @ InlineAsm Start
 ; ARM-ENABLE-NEXT:    nop
 ; ARM-ENABLE-NEXT:    @ InlineAsm End
 ; ARM-ENABLE-NEXT:    pop {r4, r7, pc}
 ; ARM-ENABLE-NEXT:  LBB3_4: @ %if.else
 ; ARM-ENABLE-NEXT:    lsl r0, r1, #1
 ; ARM-ENABLE-NEXT:    bx lr
+; ARM-ENABLE-NEXT:  Lfunc_end3:
 ;
 ; ARM-DISABLE-LABEL: loopInfoSaveOutsideLoop:
-; ARM-DISABLE:       @ %bb.0: @ %entry
+; ARM-DISABLE:       Lfunc_begin3:
+; ARM-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-DISABLE-NEXT:    push {r4, r7, lr}
 ; ARM-DISABLE-NEXT:    add r7, sp, #4
 ; ARM-DISABLE-NEXT:    cmp r0, #0
 ; ARM-DISABLE-NEXT:    beq LBB3_4
 ; ARM-DISABLE-NEXT:  @ %bb.1: @ %for.preheader
 ; ARM-DISABLE-NEXT:    mov r0, #0
 ; ARM-DISABLE-NEXT:    mov r1, #10
 ; ARM-DISABLE-NEXT:    @ InlineAsm Start

 ; ARM-DISABLE-NEXT:    lsl r0, r0, #3
 ; ARM-DISABLE-NEXT:    @ InlineAsm Start
 ; ARM-DISABLE-NEXT:    nop
 ; ARM-DISABLE-NEXT:    @ InlineAsm End
 ; ARM-DISABLE-NEXT:    pop {r4, r7, pc}
 ; ARM-DISABLE-NEXT:  LBB3_4: @ %if.else
 ; ARM-DISABLE-NEXT:    lsl r0, r1, #1
 ; ARM-DISABLE-NEXT:    pop {r4, r7, pc}
+; ARM-DISABLE-NEXT:  Lfunc_end3:
 ;
 ; THUMB-ENABLE-LABEL: loopInfoSaveOutsideLoop:
-; THUMB-ENABLE:       @ %bb.0: @ %entry
+; THUMB-ENABLE:       Lfunc_begin3:
+; THUMB-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-ENABLE-NEXT:    cbz r0, LBB3_4
 ; THUMB-ENABLE-NEXT:  @ %bb.1: @ %for.preheader
 ; THUMB-ENABLE-NEXT:    push {r4, r7, lr}
 ; THUMB-ENABLE-NEXT:    add r7, sp, #4
 ; THUMB-ENABLE-NEXT:    movs r0, #0
 ; THUMB-ENABLE-NEXT:    movs r1, #10
 ; THUMB-ENABLE-NEXT:    @ InlineAsm Start
 ; THUMB-ENABLE-NEXT:    nop

 ; THUMB-ENABLE-NEXT:    lsls r0, r0, #3
 ; THUMB-ENABLE-NEXT:    @ InlineAsm Start
 ; THUMB-ENABLE-NEXT:    nop
 ; THUMB-ENABLE-NEXT:    @ InlineAsm End
 ; THUMB-ENABLE-NEXT:    pop {r4, r7, pc}
 ; THUMB-ENABLE-NEXT:  LBB3_4: @ %if.else
 ; THUMB-ENABLE-NEXT:    lsls r0, r1, #1
 ; THUMB-ENABLE-NEXT:    bx lr
+; THUMB-ENABLE-NEXT:  Lfunc_end3:
 ;
 ; THUMB-DISABLE-LABEL: loopInfoSaveOutsideLoop:
-; THUMB-DISABLE:       @ %bb.0: @ %entry
+; THUMB-DISABLE:       Lfunc_begin3:
+; THUMB-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-DISABLE-NEXT:    push {r4, r7, lr}
 ; THUMB-DISABLE-NEXT:    add r7, sp, #4
 ; THUMB-DISABLE-NEXT:    cbz r0, LBB3_4
 ; THUMB-DISABLE-NEXT:  @ %bb.1: @ %for.preheader
 ; THUMB-DISABLE-NEXT:    movs r0, #0
 ; THUMB-DISABLE-NEXT:    movs r1, #10
 ; THUMB-DISABLE-NEXT:    @ InlineAsm Start
 ; THUMB-DISABLE-NEXT:    nop

 ; THUMB-DISABLE-NEXT:    lsls r0, r0, #3
 ; THUMB-DISABLE-NEXT:    @ InlineAsm Start
 ; THUMB-DISABLE-NEXT:    nop
 ; THUMB-DISABLE-NEXT:    @ InlineAsm End
 ; THUMB-DISABLE-NEXT:    pop {r4, r7, pc}
 ; THUMB-DISABLE-NEXT:  LBB3_4: @ %if.else
 ; THUMB-DISABLE-NEXT:    lsls r0, r1, #1
 ; THUMB-DISABLE-NEXT:    pop {r4, r7, pc}
+; THUMB-DISABLE-NEXT:  Lfunc_end3:
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %for.preheader
 
 for.preheader:
   tail call void asm "nop", ""()
   br label %for.body
 

 ; [[ELSE_LABEL]]: @ %if.else
 ; Shift second argument by one and store into returned register.
 ; lsl{{s?}} r0, r1, #1
 ; pop {r4, r7, pc}
 ;
 ; bx lr
 define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) "frame-pointer"="all" nounwind {
 ; ARM-ENABLE-LABEL: loopInfoRestoreOutsideLoop:
-; ARM-ENABLE:       @ %bb.0: @ %entry
+; ARM-ENABLE:       Lfunc_begin4:
+; ARM-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-ENABLE-NEXT:    cmp r0, #0
 ; ARM-ENABLE-NEXT:    beq LBB4_4
 ; ARM-ENABLE-NEXT:  @ %bb.1: @ %if.then
 ; ARM-ENABLE-NEXT:    push {r4, r7, lr}
 ; ARM-ENABLE-NEXT:    add r7, sp, #4
 ; ARM-ENABLE-NEXT:    mov r0, #0
 ; ARM-ENABLE-NEXT:    mov r1, #10
 ; ARM-ENABLE-NEXT:    @ InlineAsm Start
 ; ARM-ENABLE-NEXT:    nop
 ; ARM-ENABLE-NEXT:    @ InlineAsm End
 ; ARM-ENABLE-NEXT:  LBB4_2: @ %for.body
 ; ARM-ENABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; ARM-ENABLE-NEXT:    @ InlineAsm Start
 ; ARM-ENABLE-NEXT:    mov r2, #1
 ; ARM-ENABLE-NEXT:    @ InlineAsm End
 ; ARM-ENABLE-NEXT:    add r0, r2, r0
 ; ARM-ENABLE-NEXT:    subs r1, r1, #1
 ; ARM-ENABLE-NEXT:    bne LBB4_2
 ; ARM-ENABLE-NEXT:  @ %bb.3: @ %for.end
 ; ARM-ENABLE-NEXT:    lsl r0, r0, #3
 ; ARM-ENABLE-NEXT:    pop {r4, r7, pc}
 ; ARM-ENABLE-NEXT:  LBB4_4: @ %if.else
 ; ARM-ENABLE-NEXT:    lsl r0, r1, #1
 ; ARM-ENABLE-NEXT:    bx lr
+; ARM-ENABLE-NEXT:  Lfunc_end4:
 ;
 ; ARM-DISABLE-LABEL: loopInfoRestoreOutsideLoop:
-; ARM-DISABLE:       @ %bb.0: @ %entry
+; ARM-DISABLE:       Lfunc_begin4:
+; ARM-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-DISABLE-NEXT:    push {r4, r7, lr}
 ; ARM-DISABLE-NEXT:    add r7, sp, #4
 ; ARM-DISABLE-NEXT:    cmp r0, #0
 ; ARM-DISABLE-NEXT:    beq LBB4_4
 ; ARM-DISABLE-NEXT:  @ %bb.1: @ %if.then
 ; ARM-DISABLE-NEXT:    mov r0, #0
 ; ARM-DISABLE-NEXT:    mov r1, #10
 ; ARM-DISABLE-NEXT:    @ InlineAsm Start
 ; ARM-DISABLE-NEXT:    nop
 ; ARM-DISABLE-NEXT:    @ InlineAsm End
 ; ARM-DISABLE-NEXT:  LBB4_2: @ %for.body
 ; ARM-DISABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; ARM-DISABLE-NEXT:    @ InlineAsm Start
 ; ARM-DISABLE-NEXT:    mov r2, #1
 ; ARM-DISABLE-NEXT:    @ InlineAsm End
 ; ARM-DISABLE-NEXT:    add r0, r2, r0
 ; ARM-DISABLE-NEXT:    subs r1, r1, #1
 ; ARM-DISABLE-NEXT:    bne LBB4_2
 ; ARM-DISABLE-NEXT:  @ %bb.3: @ %for.end
 ; ARM-DISABLE-NEXT:    lsl r0, r0, #3
 ; ARM-DISABLE-NEXT:    pop {r4, r7, pc}
 ; ARM-DISABLE-NEXT:  LBB4_4: @ %if.else
 ; ARM-DISABLE-NEXT:    lsl r0, r1, #1
 ; ARM-DISABLE-NEXT:    pop {r4, r7, pc}
+; ARM-DISABLE-NEXT:  Lfunc_end4:
 ;
 ; THUMB-ENABLE-LABEL: loopInfoRestoreOutsideLoop:
-; THUMB-ENABLE:       @ %bb.0: @ %entry
+; THUMB-ENABLE:       Lfunc_begin4:
+; THUMB-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-ENABLE-NEXT:    cbz r0, LBB4_4
 ; THUMB-ENABLE-NEXT:  @ %bb.1: @ %if.then
 ; THUMB-ENABLE-NEXT:    push {r4, r7, lr}
 ; THUMB-ENABLE-NEXT:    add r7, sp, #4
 ; THUMB-ENABLE-NEXT:    movs r0, #0
 ; THUMB-ENABLE-NEXT:    movs r1, #10
 ; THUMB-ENABLE-NEXT:    @ InlineAsm Start
 ; THUMB-ENABLE-NEXT:    nop
 ; THUMB-ENABLE-NEXT:    @ InlineAsm End
 ; THUMB-ENABLE-NEXT:  LBB4_2: @ %for.body
 ; THUMB-ENABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; THUMB-ENABLE-NEXT:    @ InlineAsm Start
 ; THUMB-ENABLE-NEXT:    mov.w r2, #1
 ; THUMB-ENABLE-NEXT:    @ InlineAsm End
 ; THUMB-ENABLE-NEXT:    add r0, r2
 ; THUMB-ENABLE-NEXT:    subs r1, #1
 ; THUMB-ENABLE-NEXT:    bne LBB4_2
 ; THUMB-ENABLE-NEXT:  @ %bb.3: @ %for.end
 ; THUMB-ENABLE-NEXT:    lsls r0, r0, #3
 ; THUMB-ENABLE-NEXT:    pop {r4, r7, pc}
 ; THUMB-ENABLE-NEXT:  LBB4_4: @ %if.else
 ; THUMB-ENABLE-NEXT:    lsls r0, r1, #1
 ; THUMB-ENABLE-NEXT:    bx lr
+; THUMB-ENABLE-NEXT:  Lfunc_end4:
 ;
 ; THUMB-DISABLE-LABEL: loopInfoRestoreOutsideLoop:
-; THUMB-DISABLE:       @ %bb.0: @ %entry
+; THUMB-DISABLE:       Lfunc_begin4:
+; THUMB-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-DISABLE-NEXT:    push {r4, r7, lr}
 ; THUMB-DISABLE-NEXT:    add r7, sp, #4
 ; THUMB-DISABLE-NEXT:    cbz r0, LBB4_4
 ; THUMB-DISABLE-NEXT:  @ %bb.1: @ %if.then
 ; THUMB-DISABLE-NEXT:    movs r0, #0
 ; THUMB-DISABLE-NEXT:    movs r1, #10
 ; THUMB-DISABLE-NEXT:    @ InlineAsm Start
 ; THUMB-DISABLE-NEXT:    nop
 ; THUMB-DISABLE-NEXT:    @ InlineAsm End
 ; THUMB-DISABLE-NEXT:  LBB4_2: @ %for.body
 ; THUMB-DISABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; THUMB-DISABLE-NEXT:    @ InlineAsm Start
 ; THUMB-DISABLE-NEXT:    mov.w r2, #1
 ; THUMB-DISABLE-NEXT:    @ InlineAsm End
 ; THUMB-DISABLE-NEXT:    add r0, r2
 ; THUMB-DISABLE-NEXT:    subs r1, #1
 ; THUMB-DISABLE-NEXT:    bne LBB4_2
 ; THUMB-DISABLE-NEXT:  @ %bb.3: @ %for.end
 ; THUMB-DISABLE-NEXT:    lsls r0, r0, #3
 ; THUMB-DISABLE-NEXT:    pop {r4, r7, pc}
 ; THUMB-DISABLE-NEXT:  LBB4_4: @ %if.else
 ; THUMB-DISABLE-NEXT:    lsls r0, r1, #1
 ; THUMB-DISABLE-NEXT:    pop {r4, r7, pc}
+; THUMB-DISABLE-NEXT:  Lfunc_end4:
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %if.then
 
 if.then:                                          ; preds = %entry
   tail call void asm "nop", "~{r4}"()
   br label %for.body
 

 ; ARM-NEXT:    mov r0, #0
 ; ARM-NEXT:    bx lr
 ;
 ; THUMB-LABEL: emptyFrame:
 ; THUMB:       @ %bb.0: @ %entry
 ; THUMB-NEXT:    movs r0, #0
 ; THUMB-NEXT:    bx lr
 ; ARM-ENABLE-LABEL: emptyFrame:
-; ARM-ENABLE:       @ %bb.0: @ %entry
+; ARM-ENABLE:       Lfunc_begin5:
+; ARM-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-ENABLE-NEXT:    mov r0, #0
 ; ARM-ENABLE-NEXT:    bx lr
+; ARM-ENABLE-NEXT:  Lfunc_end5:
 ;
 ; ARM-DISABLE-LABEL: emptyFrame:
-; ARM-DISABLE:       @ %bb.0: @ %entry
+; ARM-DISABLE:       Lfunc_begin5:
+; ARM-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-DISABLE-NEXT:    mov r0, #0
 ; ARM-DISABLE-NEXT:    bx lr
+; ARM-DISABLE-NEXT:  Lfunc_end5:
 ;
 ; THUMB-ENABLE-LABEL: emptyFrame:
-; THUMB-ENABLE:       @ %bb.0: @ %entry
+; THUMB-ENABLE:       Lfunc_begin5:
+; THUMB-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-ENABLE-NEXT:    movs r0, #0
 ; THUMB-ENABLE-NEXT:    bx lr
+; THUMB-ENABLE-NEXT:  Lfunc_end5:
 ;
 ; THUMB-DISABLE-LABEL: emptyFrame:
-; THUMB-DISABLE:       @ %bb.0: @ %entry
+; THUMB-DISABLE:       Lfunc_begin5:
+; THUMB-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-DISABLE-NEXT:    movs r0, #0
 ; THUMB-DISABLE-NEXT:    bx lr
+; THUMB-DISABLE-NEXT:  Lfunc_end5:
 entry:
   ret i32 0
 }
 
 ; Check that we handle inline asm correctly.
 ; inlineAsm:
 ;
 ; cmp r0, #0

 ; [[ELSE_LABEL]]: @ %if.else
 ; Shift second argument by one and store into returned register.
 ; lsl{{s?}} r0, r1, #1
 ; pop {r4, r7, pc}
 ;
 ; bx lr
 define i32 @inlineAsm(i32 %cond, i32 %N) "frame-pointer"="all" {
 ; ARM-ENABLE-LABEL: inlineAsm:
-; ARM-ENABLE:       @ %bb.0: @ %entry
+; ARM-ENABLE:       Lfunc_begin6:
+; ARM-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-ENABLE-NEXT:    cmp r0, #0
 ; ARM-ENABLE-NEXT:    beq LBB6_4
 ; ARM-ENABLE-NEXT:  @ %bb.1: @ %for.preheader
 ; ARM-ENABLE-NEXT:    push {r4, r7, lr}
 ; ARM-ENABLE-NEXT:    add r7, sp, #4
 ; ARM-ENABLE-NEXT:    mov r0, #10
 ; ARM-ENABLE-NEXT:    @ InlineAsm Start
 ; ARM-ENABLE-NEXT:    nop

 ; ARM-ENABLE-NEXT:    mov r0, #0
 ; ARM-ENABLE-NEXT:    @ InlineAsm Start
 ; ARM-ENABLE-NEXT:    nop
 ; ARM-ENABLE-NEXT:    @ InlineAsm End
 ; ARM-ENABLE-NEXT:    pop {r4, r7, pc}
 ; ARM-ENABLE-NEXT:  LBB6_4: @ %if.else
 ; ARM-ENABLE-NEXT:    lsl r0, r1, #1
 ; ARM-ENABLE-NEXT:    bx lr
+; ARM-ENABLE-NEXT:  Lfunc_end6:
 ;
 ; ARM-DISABLE-LABEL: inlineAsm:
-; ARM-DISABLE:       @ %bb.0: @ %entry
+; ARM-DISABLE:       Lfunc_begin6:
+; ARM-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-DISABLE-NEXT:    push {r4, r7, lr}
 ; ARM-DISABLE-NEXT:    add r7, sp, #4
 ; ARM-DISABLE-NEXT:    cmp r0, #0
 ; ARM-DISABLE-NEXT:    beq LBB6_4
 ; ARM-DISABLE-NEXT:  @ %bb.1: @ %for.preheader
 ; ARM-DISABLE-NEXT:    mov r0, #10
 ; ARM-DISABLE-NEXT:    @ InlineAsm Start
 ; ARM-DISABLE-NEXT:    nop

 ; ARM-DISABLE-NEXT:    mov r0, #0
 ; ARM-DISABLE-NEXT:    @ InlineAsm Start
 ; ARM-DISABLE-NEXT:    nop
 ; ARM-DISABLE-NEXT:    @ InlineAsm End
 ; ARM-DISABLE-NEXT:    pop {r4, r7, pc}
 ; ARM-DISABLE-NEXT:  LBB6_4: @ %if.else
 ; ARM-DISABLE-NEXT:    lsl r0, r1, #1
 ; ARM-DISABLE-NEXT:    pop {r4, r7, pc}
+; ARM-DISABLE-NEXT:  Lfunc_end6:
 ;
 ; THUMB-ENABLE-LABEL: inlineAsm:
-; THUMB-ENABLE:       @ %bb.0: @ %entry
+; THUMB-ENABLE:       Lfunc_begin6:
+; THUMB-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-ENABLE-NEXT:    cbz r0, LBB6_4
 ; THUMB-ENABLE-NEXT:  @ %bb.1: @ %for.preheader
 ; THUMB-ENABLE-NEXT:    push {r4, r7, lr}
 ; THUMB-ENABLE-NEXT:    add r7, sp, #4
 ; THUMB-ENABLE-NEXT:    movs r0, #10
 ; THUMB-ENABLE-NEXT:    @ InlineAsm Start
 ; THUMB-ENABLE-NEXT:    nop
 ; THUMB-ENABLE-NEXT:    @ InlineAsm End
 ; THUMB-ENABLE-NEXT:  LBB6_2: @ %for.body
 ; THUMB-ENABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; THUMB-ENABLE-NEXT:    subs r0, #1
 ; THUMB-ENABLE-NEXT:    @ InlineAsm Start
 ; THUMB-ENABLE-NEXT:    add.w r4, r4, #1
 ; THUMB-ENABLE-NEXT:    @ InlineAsm End
 ; THUMB-ENABLE-NEXT:    bne LBB6_2
 ; THUMB-ENABLE-NEXT:  @ %bb.3: @ %for.exit
 ; THUMB-ENABLE-NEXT:    movs r0, #0
 ; THUMB-ENABLE-NEXT:    @ InlineAsm Start
 ; THUMB-ENABLE-NEXT:    nop
 ; THUMB-ENABLE-NEXT:    @ InlineAsm End
 ; THUMB-ENABLE-NEXT:    pop {r4, r7, pc}
 ; THUMB-ENABLE-NEXT:  LBB6_4: @ %if.else
 ; THUMB-ENABLE-NEXT:    lsls r0, r1, #1
 ; THUMB-ENABLE-NEXT:    bx lr
+; THUMB-ENABLE-NEXT:  Lfunc_end6:
 ;
 ; THUMB-DISABLE-LABEL: inlineAsm:
-; THUMB-DISABLE:       @ %bb.0: @ %entry
+; THUMB-DISABLE:       Lfunc_begin6:
+; THUMB-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-DISABLE-NEXT:    push {r4, r7, lr}
 ; THUMB-DISABLE-NEXT:    add r7, sp, #4
 ; THUMB-DISABLE-NEXT:    cbz r0, LBB6_4
 ; THUMB-DISABLE-NEXT:  @ %bb.1: @ %for.preheader
 ; THUMB-DISABLE-NEXT:    movs r0, #10
 ; THUMB-DISABLE-NEXT:    @ InlineAsm Start
 ; THUMB-DISABLE-NEXT:    nop
 ; THUMB-DISABLE-NEXT:    @ InlineAsm End
 ; THUMB-DISABLE-NEXT:  LBB6_2: @ %for.body
 ; THUMB-DISABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; THUMB-DISABLE-NEXT:    subs r0, #1
 ; THUMB-DISABLE-NEXT:    @ InlineAsm Start
 ; THUMB-DISABLE-NEXT:    add.w r4, r4, #1
 ; THUMB-DISABLE-NEXT:    @ InlineAsm End
 ; THUMB-DISABLE-NEXT:    bne LBB6_2
 ; THUMB-DISABLE-NEXT:  @ %bb.3: @ %for.exit
 ; THUMB-DISABLE-NEXT:    movs r0, #0
 ; THUMB-DISABLE-NEXT:    @ InlineAsm Start
 ; THUMB-DISABLE-NEXT:    nop
 ; THUMB-DISABLE-NEXT:    @ InlineAsm End
 ; THUMB-DISABLE-NEXT:    pop {r4, r7, pc}
 ; THUMB-DISABLE-NEXT:  LBB6_4: @ %if.else
 ; THUMB-DISABLE-NEXT:    lsls r0, r1, #1
 ; THUMB-DISABLE-NEXT:    pop {r4, r7, pc}
+; THUMB-DISABLE-NEXT:  Lfunc_end6:
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %for.preheader
 
 for.preheader:
   tail call void asm "nop", ""()
   br label %for.body
 

 ; Epilogue code.
 ; bx lr
 ;
 ; mov sp, r7
 ; add sp, #12
 ; pop {r7, pc}
 define i32 @callVariadicFunc(i32 %cond, i32 %N) "frame-pointer"="all" {
 ; ARM-ENABLE-LABEL: callVariadicFunc:
-; ARM-ENABLE:       @ %bb.0: @ %entry
+; ARM-ENABLE:       Lfunc_begin7:
+; ARM-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-ENABLE-NEXT:    cmp r0, #0
 ; ARM-ENABLE-NEXT:    beq LBB7_2
 ; ARM-ENABLE-NEXT:  @ %bb.1: @ %if.then
 ; ARM-ENABLE-NEXT:    push {r7, lr}
 ; ARM-ENABLE-NEXT:    mov r7, sp
 ; ARM-ENABLE-NEXT:    sub sp, sp, #12
 ; ARM-ENABLE-NEXT:    mov r0, r1
 ; ARM-ENABLE-NEXT:    mov r2, r1
 ; ARM-ENABLE-NEXT:    mov r3, r1
 ; ARM-ENABLE-NEXT:    str r1, [sp]
 ; ARM-ENABLE-NEXT:    str r1, [sp, #4]
 ; ARM-ENABLE-NEXT:    str r1, [sp, #8]
 ; ARM-ENABLE-NEXT:    bl _someVariadicFunc
 ; ARM-ENABLE-NEXT:    lsl r0, r0, #3
 ; ARM-ENABLE-NEXT:    mov sp, r7
 ; ARM-ENABLE-NEXT:    pop {r7, pc}
 ; ARM-ENABLE-NEXT:  LBB7_2: @ %if.else
 ; ARM-ENABLE-NEXT:    lsl r0, r1, #1
 ; ARM-ENABLE-NEXT:    bx lr
+; ARM-ENABLE-NEXT:  Lfunc_end7:
 ;
 ; ARM-DISABLE-LABEL: callVariadicFunc:
-; ARM-DISABLE:       @ %bb.0: @ %entry
+; ARM-DISABLE:       Lfunc_begin7:
+; ARM-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-DISABLE-NEXT:    push {r7, lr}
 ; ARM-DISABLE-NEXT:    mov r7, sp
 ; ARM-DISABLE-NEXT:    sub sp, sp, #12
 ; ARM-DISABLE-NEXT:    cmp r0, #0
 ; ARM-DISABLE-NEXT:    beq LBB7_2
 ; ARM-DISABLE-NEXT:  @ %bb.1: @ %if.then
 ; ARM-DISABLE-NEXT:    mov r0, r1
 ; ARM-DISABLE-NEXT:    mov r2, r1
 ; ARM-DISABLE-NEXT:    mov r3, r1
 ; ARM-DISABLE-NEXT:    str r1, [sp]
 ; ARM-DISABLE-NEXT:    str r1, [sp, #4]
 ; ARM-DISABLE-NEXT:    str r1, [sp, #8]
 ; ARM-DISABLE-NEXT:    bl _someVariadicFunc
 ; ARM-DISABLE-NEXT:    lsl r0, r0, #3
 ; ARM-DISABLE-NEXT:    mov sp, r7
 ; ARM-DISABLE-NEXT:    pop {r7, pc}
 ; ARM-DISABLE-NEXT:  LBB7_2: @ %if.else
 ; ARM-DISABLE-NEXT:    lsl r0, r1, #1
 ; ARM-DISABLE-NEXT:    mov sp, r7
 ; ARM-DISABLE-NEXT:    pop {r7, pc}
+; ARM-DISABLE-NEXT:  Lfunc_end7:
 ;
 ; THUMB-ENABLE-LABEL: callVariadicFunc:
-; THUMB-ENABLE:       @ %bb.0: @ %entry
+; THUMB-ENABLE:       Lfunc_begin7:
+; THUMB-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-ENABLE-NEXT:    cbz r0, LBB7_2
 ; THUMB-ENABLE-NEXT:  @ %bb.1: @ %if.then
 ; THUMB-ENABLE-NEXT:    push {r7, lr}
 ; THUMB-ENABLE-NEXT:    mov r7, sp
 ; THUMB-ENABLE-NEXT:    sub sp, #12
 ; THUMB-ENABLE-NEXT:    mov r0, r1
 ; THUMB-ENABLE-NEXT:    mov r2, r1
 ; THUMB-ENABLE-NEXT:    mov r3, r1
 ; THUMB-ENABLE-NEXT:    strd r1, r1, [sp]
 ; THUMB-ENABLE-NEXT:    str r1, [sp, #8]
 ; THUMB-ENABLE-NEXT:    bl _someVariadicFunc
 ; THUMB-ENABLE-NEXT:    lsls r0, r0, #3
 ; THUMB-ENABLE-NEXT:    add sp, #12
 ; THUMB-ENABLE-NEXT:    pop {r7, pc}
 ; THUMB-ENABLE-NEXT:  LBB7_2: @ %if.else
 ; THUMB-ENABLE-NEXT:    lsls r0, r1, #1
 ; THUMB-ENABLE-NEXT:    bx lr
+; THUMB-ENABLE-NEXT:  Lfunc_end7:
 ;
 ; THUMB-DISABLE-LABEL: callVariadicFunc:
-; THUMB-DISABLE:       @ %bb.0: @ %entry
+; THUMB-DISABLE:       Lfunc_begin7:
+; THUMB-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-DISABLE-NEXT:    push {r7, lr}
 ; THUMB-DISABLE-NEXT:    mov r7, sp
 ; THUMB-DISABLE-NEXT:    sub sp, #12
 ; THUMB-DISABLE-NEXT:    cbz r0, LBB7_2
 ; THUMB-DISABLE-NEXT:  @ %bb.1: @ %if.then
 ; THUMB-DISABLE-NEXT:    mov r0, r1
 ; THUMB-DISABLE-NEXT:    mov r2, r1
 ; THUMB-DISABLE-NEXT:    mov r3, r1
 ; THUMB-DISABLE-NEXT:    strd r1, r1, [sp]
 ; THUMB-DISABLE-NEXT:    str r1, [sp, #8]
 ; THUMB-DISABLE-NEXT:    bl _someVariadicFunc
 ; THUMB-DISABLE-NEXT:    lsls r0, r0, #3
 ; THUMB-DISABLE-NEXT:    add sp, #12
 ; THUMB-DISABLE-NEXT:    pop {r7, pc}
 ; THUMB-DISABLE-NEXT:  LBB7_2: @ %if.else
 ; THUMB-DISABLE-NEXT:    lsls r0, r1, #1
 ; THUMB-DISABLE-NEXT:    add sp, #12
 ; THUMB-DISABLE-NEXT:    pop {r7, pc}
+; THUMB-DISABLE-NEXT:  Lfunc_end7:
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %if.then
 
 if.then:                                          ; preds = %entry
   %call = tail call i32 (i32, ...) @someVariadicFunc(i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N)
   %shl = shl i32 %call, 3
   br label %if.end

 ; [[ABORT]]: @ %if.abort
 ;
 ; push
 ;
 ; bl{{x?}} _abort
 ; pop
 define i32 @noreturn(i8 signext %bad_thing) "frame-pointer"="all" {
 ; ARM-ENABLE-LABEL: noreturn:
-; ARM-ENABLE:       @ %bb.0: @ %entry
+; ARM-ENABLE:       Lfunc_begin8:
+; ARM-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-ENABLE-NEXT:    cmp r0, #0
 ; ARM-ENABLE-NEXT:    bne LBB8_2
 ; ARM-ENABLE-NEXT:  @ %bb.1: @ %if.end
 ; ARM-ENABLE-NEXT:    mov r0, #42
 ; ARM-ENABLE-NEXT:    bx lr
 ; ARM-ENABLE-NEXT:  LBB8_2: @ %if.abort
 ; ARM-ENABLE-NEXT:    push {r4, r7, lr}
 ; ARM-ENABLE-NEXT:    add r7, sp, #4
 ; ARM-ENABLE-NEXT:    @ InlineAsm Start
 ; ARM-ENABLE-NEXT:    mov r0, #1
 ; ARM-ENABLE-NEXT:    @ InlineAsm End
 ; ARM-ENABLE-NEXT:    bl _abort
+; ARM-ENABLE-NEXT:  Lfunc_end8:
 ;
 ; ARM-DISABLE-LABEL: noreturn:
-; ARM-DISABLE:       @ %bb.0: @ %entry
+; ARM-DISABLE:       Lfunc_begin8:
+; ARM-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-DISABLE-NEXT:    push {r4, r7, lr}
 ; ARM-DISABLE-NEXT:    add r7, sp, #4
 ; ARM-DISABLE-NEXT:    cmp r0, #0
 ; ARM-DISABLE-NEXT:    bne LBB8_2
 ; ARM-DISABLE-NEXT:  @ %bb.1: @ %if.end
 ; ARM-DISABLE-NEXT:    mov r0, #42
 ; ARM-DISABLE-NEXT:    pop {r4, r7, pc}
 ; ARM-DISABLE-NEXT:  LBB8_2: @ %if.abort
 ; ARM-DISABLE-NEXT:    @ InlineAsm Start
 ; ARM-DISABLE-NEXT:    mov r0, #1
 ; ARM-DISABLE-NEXT:    @ InlineAsm End
 ; ARM-DISABLE-NEXT:    bl _abort
+; ARM-DISABLE-NEXT:  Lfunc_end8:
 ;
 ; THUMB-ENABLE-LABEL: noreturn:
-; THUMB-ENABLE:       @ %bb.0: @ %entry
+; THUMB-ENABLE:       Lfunc_begin8:
+; THUMB-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-ENABLE-NEXT:    cbnz r0, LBB8_2
 ; THUMB-ENABLE-NEXT:  @ %bb.1: @ %if.end
 ; THUMB-ENABLE-NEXT:    movs r0, #42
 ; THUMB-ENABLE-NEXT:    bx lr
 ; THUMB-ENABLE-NEXT:  LBB8_2: @ %if.abort
 ; THUMB-ENABLE-NEXT:    push {r4, r7, lr}
 ; THUMB-ENABLE-NEXT:    add r7, sp, #4
 ; THUMB-ENABLE-NEXT:    @ InlineAsm Start
 ; THUMB-ENABLE-NEXT:    mov.w r0, #1
 ; THUMB-ENABLE-NEXT:    @ InlineAsm End
 ; THUMB-ENABLE-NEXT:    bl _abort
+; THUMB-ENABLE-NEXT:  Lfunc_end8:
 ;
 ; THUMB-DISABLE-LABEL: noreturn:
-; THUMB-DISABLE:       @ %bb.0: @ %entry
+; THUMB-DISABLE:       Lfunc_begin8:
+; THUMB-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-DISABLE-NEXT:    push {r4, r7, lr}
 ; THUMB-DISABLE-NEXT:    add r7, sp, #4
 ; THUMB-DISABLE-NEXT:    cbnz r0, LBB8_2
 ; THUMB-DISABLE-NEXT:  @ %bb.1: @ %if.end
 ; THUMB-DISABLE-NEXT:    movs r0, #42
 ; THUMB-DISABLE-NEXT:    pop {r4, r7, pc}
 ; THUMB-DISABLE-NEXT:  LBB8_2: @ %if.abort
 ; THUMB-DISABLE-NEXT:    @ InlineAsm Start
 ; THUMB-DISABLE-NEXT:    mov.w r0, #1
 ; THUMB-DISABLE-NEXT:    @ InlineAsm End
 ; THUMB-DISABLE-NEXT:    bl _abort
+; THUMB-DISABLE-NEXT:  Lfunc_end8:
 entry:
   %tobool = icmp eq i8 %bad_thing, 0
   br i1 %tobool, label %if.end, label %if.abort
 
 if.abort:
   %call = tail call i32 asm sideeffect "mov $0, #1", "=r,~{r4}"()
   tail call void @abort() #0
   unreachable

 ; THUMB-NEXT:    add r1, r2
 ; THUMB-NEXT:    str r1, [r0]
 ; THUMB-NEXT:    b LBB9_2
 ; THUMB-NEXT:  LBB9_3: @ %if.end
 ; THUMB-NEXT:    sub.w r4, r7, #8
 ; THUMB-NEXT:    mov sp, r4
 ; THUMB-NEXT:    pop {r4, r5, r7, pc}
 ; ARM-ENABLE-LABEL: infiniteloop:
-; ARM-ENABLE:       @ %bb.0: @ %entry
+; ARM-ENABLE:       Lfunc_begin9:
+; ARM-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-ENABLE-NEXT:    push {r4, r5, r7, lr}
 ; ARM-ENABLE-NEXT:    add r7, sp, #8
 ; ARM-ENABLE-NEXT:    mov r0, #0
 ; ARM-ENABLE-NEXT:    cmp r0, #0
 ; ARM-ENABLE-NEXT:    bne LBB9_3
 ; ARM-ENABLE-NEXT:  @ %bb.1: @ %if.then
 ; ARM-ENABLE-NEXT:    sub r1, sp, #16
 ; ARM-ENABLE-NEXT:    mov sp, r1
 ; ARM-ENABLE-NEXT:  LBB9_2: @ %for.body
 ; ARM-ENABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; ARM-ENABLE-NEXT:    @ InlineAsm Start
 ; ARM-ENABLE-NEXT:    mov r2, #1
 ; ARM-ENABLE-NEXT:    @ InlineAsm End
 ; ARM-ENABLE-NEXT:    add r0, r2, r0
 ; ARM-ENABLE-NEXT:    str r0, [r1]
 ; ARM-ENABLE-NEXT:    b LBB9_2
 ; ARM-ENABLE-NEXT:  LBB9_3: @ %if.end
 ; ARM-ENABLE-NEXT:    sub sp, r7, #8
 ; ARM-ENABLE-NEXT:    pop {r4, r5, r7, pc}
+; ARM-ENABLE-NEXT:  Lfunc_end9:
 ;
 ; ARM-DISABLE-LABEL: infiniteloop:
-; ARM-DISABLE:       @ %bb.0: @ %entry
+; ARM-DISABLE:       Lfunc_begin9:
+; ARM-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-DISABLE-NEXT:    push {r4, r5, r7, lr}
 ; ARM-DISABLE-NEXT:    add r7, sp, #8
 ; ARM-DISABLE-NEXT:    mov r0, #0
 ; ARM-DISABLE-NEXT:    cmp r0, #0
 ; ARM-DISABLE-NEXT:    bne LBB9_3
 ; ARM-DISABLE-NEXT:  @ %bb.1: @ %if.then
 ; ARM-DISABLE-NEXT:    sub r1, sp, #16
 ; ARM-DISABLE-NEXT:    mov sp, r1
 ; ARM-DISABLE-NEXT:  LBB9_2: @ %for.body
 ; ARM-DISABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; ARM-DISABLE-NEXT:    @ InlineAsm Start
 ; ARM-DISABLE-NEXT:    mov r2, #1
 ; ARM-DISABLE-NEXT:    @ InlineAsm End
 ; ARM-DISABLE-NEXT:    add r0, r2, r0
 ; ARM-DISABLE-NEXT:    str r0, [r1]
 ; ARM-DISABLE-NEXT:    b LBB9_2
 ; ARM-DISABLE-NEXT:  LBB9_3: @ %if.end
 ; ARM-DISABLE-NEXT:    sub sp, r7, #8
 ; ARM-DISABLE-NEXT:    pop {r4, r5, r7, pc}
+; ARM-DISABLE-NEXT:  Lfunc_end9:
 ;
 ; THUMB-ENABLE-LABEL: infiniteloop:
-; THUMB-ENABLE:       @ %bb.0: @ %entry
+; THUMB-ENABLE:       Lfunc_begin9:
+; THUMB-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-ENABLE-NEXT:    push {r4, r5, r7, lr}
 ; THUMB-ENABLE-NEXT:    add r7, sp, #8
 ; THUMB-ENABLE-NEXT:    movs r0, #0
 ; THUMB-ENABLE-NEXT:    cbnz r0, LBB9_3
 ; THUMB-ENABLE-NEXT:  @ %bb.1: @ %if.then
 ; THUMB-ENABLE-NEXT:    sub.w r0, sp, #16
 ; THUMB-ENABLE-NEXT:    mov sp, r0
 ; THUMB-ENABLE-NEXT:    movs r1, #0
 ; THUMB-ENABLE-NEXT:  LBB9_2: @ %for.body
 ; THUMB-ENABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; THUMB-ENABLE-NEXT:    @ InlineAsm Start
 ; THUMB-ENABLE-NEXT:    mov.w r2, #1
 ; THUMB-ENABLE-NEXT:    @ InlineAsm End
 ; THUMB-ENABLE-NEXT:    add r1, r2
 ; THUMB-ENABLE-NEXT:    str r1, [r0]
 ; THUMB-ENABLE-NEXT:    b LBB9_2
 ; THUMB-ENABLE-NEXT:  LBB9_3: @ %if.end
 ; THUMB-ENABLE-NEXT:    sub.w r4, r7, #8
 ; THUMB-ENABLE-NEXT:    mov sp, r4
 ; THUMB-ENABLE-NEXT:    pop {r4, r5, r7, pc}
+; THUMB-ENABLE-NEXT:  Lfunc_end9:
 ;
 ; THUMB-DISABLE-LABEL: infiniteloop:
-; THUMB-DISABLE:       @ %bb.0: @ %entry
+; THUMB-DISABLE:       Lfunc_begin9:
+; THUMB-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-DISABLE-NEXT:    push {r4, r5, r7, lr}
 ; THUMB-DISABLE-NEXT:    add r7, sp, #8
 ; THUMB-DISABLE-NEXT:    movs r0, #0
 ; THUMB-DISABLE-NEXT:    cbnz r0, LBB9_3
 ; THUMB-DISABLE-NEXT:  @ %bb.1: @ %if.then
 ; THUMB-DISABLE-NEXT:    sub.w r0, sp, #16
 ; THUMB-DISABLE-NEXT:    mov sp, r0
 ; THUMB-DISABLE-NEXT:    movs r1, #0
 ; THUMB-DISABLE-NEXT:  LBB9_2: @ %for.body
 ; THUMB-DISABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; THUMB-DISABLE-NEXT:    @ InlineAsm Start
 ; THUMB-DISABLE-NEXT:    mov.w r2, #1
 ; THUMB-DISABLE-NEXT:    @ InlineAsm End
 ; THUMB-DISABLE-NEXT:    add r1, r2
 ; THUMB-DISABLE-NEXT:    str r1, [r0]
 ; THUMB-DISABLE-NEXT:    b LBB9_2
 ; THUMB-DISABLE-NEXT:  LBB9_3: @ %if.end
 ; THUMB-DISABLE-NEXT:    sub.w r4, r7, #8
 ; THUMB-DISABLE-NEXT:    mov sp, r4
 ; THUMB-DISABLE-NEXT:    pop {r4, r5, r7, pc}
+; THUMB-DISABLE-NEXT:  Lfunc_end9:
 entry:
   br i1 undef, label %if.then, label %if.end
 
 if.then:
   %ptr = alloca i32, i32 4
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
   %sum.03 = phi i32 [ 0, %if.then ], [ %add, %for.body ]
   %call = tail call i32 asm sideeffect "mov $0, #1", "=r,~{r4}"()
   %add = add nsw i32 %call, %sum.03
   store i32 %add, ptr %ptr
   br label %for.body
 
 if.end:
   ret void
 }
 
 ; Another infinite loop test this time with a body bigger than just one block.
 ; infiniteloop2
 ; pop
 define void @infiniteloop2() "frame-pointer"="all" {
+; ARM-ENABLE-LABEL: infiniteloop2:
+; ARM-ENABLE:       Lfunc_begin10:
+; ARM-ENABLE-NEXT:  @ %bb.0: @ %entry
+; ARM-ENABLE-NEXT:    push {r4, r5, r7, lr}
+; ARM-ENABLE-NEXT:    add r7, sp, #8
+; ARM-ENABLE-NEXT:    mov r0, #0
+; ARM-ENABLE-NEXT:    cmp r0, #0
+; ARM-ENABLE-NEXT:    bne LBB10_3
+; ARM-ENABLE-NEXT:  @ %bb.1: @ %if.then
+; ARM-ENABLE-NEXT:    sub r1, sp, #16
+; ARM-ENABLE-NEXT:    mov sp, r1
+; ARM-ENABLE-NEXT:    @ InlineAsm Start
+; ARM-ENABLE-NEXT:    mov r2, #0
+; ARM-ENABLE-NEXT:    @ InlineAsm End
+; ARM-ENABLE-NEXT:  LBB10_2: @ %for.body
+; ARM-ENABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
+; ARM-ENABLE-NEXT:    add r0, r2, r0
+; ARM-ENABLE-NEXT:    str r0, [r1]
+; ARM-ENABLE-NEXT:    @ InlineAsm Start
+; ARM-ENABLE-NEXT:    nop
+; ARM-ENABLE-NEXT:    @ InlineAsm End
+; ARM-ENABLE-NEXT:    mov r0, #1
+; ARM-ENABLE-NEXT:    b LBB10_2
+; ARM-ENABLE-NEXT:  LBB10_3: @ %if.end
+; ARM-ENABLE-NEXT:    sub sp, r7, #8
+; ARM-ENABLE-NEXT:    pop {r4, r5, r7, pc}
+; ARM-ENABLE-NEXT:  Lfunc_end10:
+;
+; ARM-DISABLE-LABEL: infiniteloop2:
+; ARM-DISABLE:       Lfunc_begin10:
+; ARM-DISABLE-NEXT:  @ %bb.0: @ %entry
+; ARM-DISABLE-NEXT:    push {r4, r5, r7, lr}
+; ARM-DISABLE-NEXT:    add r7, sp, #8
+; ARM-DISABLE-NEXT:    mov r0, #0
+; ARM-DISABLE-NEXT:    cmp r0, #0
+; ARM-DISABLE-NEXT:    bne LBB10_3
+; ARM-DISABLE-NEXT:  @ %bb.1: @ %if.then
+; ARM-DISABLE-NEXT:    sub r1, sp, #16
+; ARM-DISABLE-NEXT:    mov sp, r1
+; ARM-DISABLE-NEXT:    @ InlineAsm Start
+; ARM-DISABLE-NEXT:    mov r2, #0
+; ARM-DISABLE-NEXT:    @ InlineAsm End
+; ARM-DISABLE-NEXT:  LBB10_2: @ %for.body
+; ARM-DISABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
+; ARM-DISABLE-NEXT:    add r0, r2, r0
+; ARM-DISABLE-NEXT:    str r0, [r1]
+; ARM-DISABLE-NEXT:    @ InlineAsm Start
+; ARM-DISABLE-NEXT:    nop
+; ARM-DISABLE-NEXT:    @ InlineAsm End
+; ARM-DISABLE-NEXT:    mov r0, #1
+; ARM-DISABLE-NEXT:    b LBB10_2
+; ARM-DISABLE-NEXT:  LBB10_3: @ %if.end
+; ARM-DISABLE-NEXT:    sub sp, r7, #8
+; ARM-DISABLE-NEXT:    pop {r4, r5, r7, pc}
+; ARM-DISABLE-NEXT:  Lfunc_end10:
+;
+; THUMB-ENABLE-LABEL: infiniteloop2:
+; THUMB-ENABLE:       Lfunc_begin10:
+; THUMB-ENABLE-NEXT:  @ %bb.0: @ %entry
+; THUMB-ENABLE-NEXT:    push {r4, r5, r7, lr}
+; THUMB-ENABLE-NEXT:    add r7, sp, #8
+; THUMB-ENABLE-NEXT:    movs r0, #0
+; THUMB-ENABLE-NEXT:    cbnz r0, LBB10_3
+; THUMB-ENABLE-NEXT:  @ %bb.1: @ %if.then
+; THUMB-ENABLE-NEXT:    sub.w r0, sp, #16
+; THUMB-ENABLE-NEXT:    mov sp, r0
+; THUMB-ENABLE-NEXT:    movs r1, #0
+; THUMB-ENABLE-NEXT:    @ InlineAsm Start
+; THUMB-ENABLE-NEXT:    mov.w r2, #0
+; THUMB-ENABLE-NEXT:    @ InlineAsm End
+; THUMB-ENABLE-NEXT:  LBB10_2: @ %for.body
+; THUMB-ENABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
+; THUMB-ENABLE-NEXT:    add r1, r2
+; THUMB-ENABLE-NEXT:    str r1, [r0]
+; THUMB-ENABLE-NEXT:    @ InlineAsm Start
+; THUMB-ENABLE-NEXT:    nop
+; THUMB-ENABLE-NEXT:    @ InlineAsm End
+; THUMB-ENABLE-NEXT:    movs r1, #1
+; THUMB-ENABLE-NEXT:    b LBB10_2
+; THUMB-ENABLE-NEXT:  LBB10_3: @ %if.end
+; THUMB-ENABLE-NEXT:    sub.w r4, r7, #8
+; THUMB-ENABLE-NEXT:    mov sp, r4
+; THUMB-ENABLE-NEXT:    pop {r4, r5, r7, pc}
+; THUMB-ENABLE-NEXT:  Lfunc_end10:
+;
+; THUMB-DISABLE-LABEL: infiniteloop2:
+; THUMB-DISABLE:       Lfunc_begin10:
+; THUMB-DISABLE-NEXT:  @ %bb.0: @ %entry
+; THUMB-DISABLE-NEXT:    push {r4, r5, r7, lr}
+; THUMB-DISABLE-NEXT:    add r7, sp, #8
+; THUMB-DISABLE-NEXT:    movs r0, #0
+; THUMB-DISABLE-NEXT:    cbnz r0, LBB10_3
+; THUMB-DISABLE-NEXT:  @ %bb.1: @ %if.then
+; THUMB-DISABLE-NEXT:    sub.w r0, sp, #16
+; THUMB-DISABLE-NEXT:    mov sp, r0
+; THUMB-DISABLE-NEXT:    movs r1, #0
+; THUMB-DISABLE-NEXT:    @ InlineAsm Start
+; THUMB-DISABLE-NEXT:    mov.w r2, #0
+; THUMB-DISABLE-NEXT:    @ InlineAsm End
+; THUMB-DISABLE-NEXT:  LBB10_2: @ %for.body
+; THUMB-DISABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
+; THUMB-DISABLE-NEXT:    add r1, r2
+; THUMB-DISABLE-NEXT:    str r1, [r0]
+; THUMB-DISABLE-NEXT:    @ InlineAsm Start
+; THUMB-DISABLE-NEXT:    nop
+; THUMB-DISABLE-NEXT:    @ InlineAsm End
+; THUMB-DISABLE-NEXT:    movs r1, #1
+; THUMB-DISABLE-NEXT:    b LBB10_2
+; THUMB-DISABLE-NEXT:  LBB10_3: @ %if.end
+; THUMB-DISABLE-NEXT:    sub.w r4, r7, #8
+; THUMB-DISABLE-NEXT:    mov sp, r4
+; THUMB-DISABLE-NEXT:    pop {r4, r5, r7, pc}
+; THUMB-DISABLE-NEXT:  Lfunc_end10:
 entry:
   br i1 undef, label %if.then, label %if.end
 
 if.then:
   %ptr = alloca i32, i32 4
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry

 ; THUMB-NEXT:  @ %bb.4: @ in Loop: Header=BB11_3 Depth=1
 ; THUMB-NEXT:    mov r0, r1
 ; THUMB-NEXT:    mov r1, r3
 ; THUMB-NEXT:    mov r2, r0
 ; THUMB-NEXT:    b LBB11_3
 ; THUMB-NEXT:  LBB11_5: @ %end
 ; THUMB-NEXT:    bx lr
 ; ARM-ENABLE-LABEL: infiniteloop3:
-; ARM-ENABLE:       @ %bb.0: @ %entry
+; ARM-ENABLE:       Lfunc_begin11:
+; ARM-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-ENABLE-NEXT:    mov r0, #0
 ; ARM-ENABLE-NEXT:    cmp r0, #0
 ; ARM-ENABLE-NEXT:    bne LBB11_5
 ; ARM-ENABLE-NEXT:  @ %bb.1: @ %loop2a.preheader
 ; ARM-ENABLE-NEXT:    mov r1, #0
 ; ARM-ENABLE-NEXT:    mov r2, r0
 ; ARM-ENABLE-NEXT:    b LBB11_3
 ; ARM-ENABLE-NEXT:  LBB11_2: @ %loop2b
 ; ARM-ENABLE-NEXT:    @ in Loop: Header=BB11_3 Depth=1
 ; ARM-ENABLE-NEXT:    str r1, [r2]
 ; ARM-ENABLE-NEXT:    mov r2, r1
 ; ARM-ENABLE-NEXT:    mov r1, r3
 ; ARM-ENABLE-NEXT:  LBB11_3: @ %loop1
 ; ARM-ENABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; ARM-ENABLE-NEXT:    ldr r3, [r0]
 ; ARM-ENABLE-NEXT:    cmp r0, #0
 ; ARM-ENABLE-NEXT:    bne LBB11_2
 ; ARM-ENABLE-NEXT:  @ %bb.4: @ in Loop: Header=BB11_3 Depth=1
 ; ARM-ENABLE-NEXT:    mov r0, r1
 ; ARM-ENABLE-NEXT:    mov r1, r3
 ; ARM-ENABLE-NEXT:    mov r2, r0
 ; ARM-ENABLE-NEXT:    b LBB11_3
 ; ARM-ENABLE-NEXT:  LBB11_5: @ %end
 ; ARM-ENABLE-NEXT:    bx lr
+; ARM-ENABLE-NEXT:  Lfunc_end11:
 ;
 ; ARM-DISABLE-LABEL: infiniteloop3:
-; ARM-DISABLE:       @ %bb.0: @ %entry
+; ARM-DISABLE:       Lfunc_begin11:
+; ARM-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; ARM-DISABLE-NEXT:    mov r0, #0
 ; ARM-DISABLE-NEXT:    cmp r0, #0
 ; ARM-DISABLE-NEXT:    bne LBB11_5
 ; ARM-DISABLE-NEXT:  @ %bb.1: @ %loop2a.preheader
 ; ARM-DISABLE-NEXT:    mov r1, #0
 ; ARM-DISABLE-NEXT:    mov r2, r0
 ; ARM-DISABLE-NEXT:    b LBB11_3
 ; ARM-DISABLE-NEXT:  LBB11_2: @ %loop2b
 ; ARM-DISABLE-NEXT:    @ in Loop: Header=BB11_3 Depth=1
 ; ARM-DISABLE-NEXT:    str r1, [r2]
 ; ARM-DISABLE-NEXT:    mov r2, r1
 ; ARM-DISABLE-NEXT:    mov r1, r3
 ; ARM-DISABLE-NEXT:  LBB11_3: @ %loop1
 ; ARM-DISABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; ARM-DISABLE-NEXT:    ldr r3, [r0]
 ; ARM-DISABLE-NEXT:    cmp r0, #0
 ; ARM-DISABLE-NEXT:    bne LBB11_2
 ; ARM-DISABLE-NEXT:  @ %bb.4: @ in Loop: Header=BB11_3 Depth=1
 ; ARM-DISABLE-NEXT:    mov r0, r1
 ; ARM-DISABLE-NEXT:    mov r1, r3
 ; ARM-DISABLE-NEXT:    mov r2, r0
 ; ARM-DISABLE-NEXT:    b LBB11_3
 ; ARM-DISABLE-NEXT:  LBB11_5: @ %end
 ; ARM-DISABLE-NEXT:    bx lr
+; ARM-DISABLE-NEXT:  Lfunc_end11:
 ;
 ; THUMB-ENABLE-LABEL: infiniteloop3:
-; THUMB-ENABLE:       @ %bb.0: @ %entry
+; THUMB-ENABLE:       Lfunc_begin11:
+; THUMB-ENABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-ENABLE-NEXT:    movs r0, #0
 ; THUMB-ENABLE-NEXT:    cbnz r0, LBB11_5
 ; THUMB-ENABLE-NEXT:  @ %bb.1: @ %loop2a.preheader
 ; THUMB-ENABLE-NEXT:    movs r1, #0
 ; THUMB-ENABLE-NEXT:    mov r2, r0
 ; THUMB-ENABLE-NEXT:    b LBB11_3
 ; THUMB-ENABLE-NEXT:  LBB11_2: @ %loop2b
 ; THUMB-ENABLE-NEXT:    @ in Loop: Header=BB11_3 Depth=1
 ; THUMB-ENABLE-NEXT:    str r1, [r2]
 ; THUMB-ENABLE-NEXT:    mov r2, r1
 ; THUMB-ENABLE-NEXT:    mov r1, r3
 ; THUMB-ENABLE-NEXT:  LBB11_3: @ %loop1
 ; THUMB-ENABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; THUMB-ENABLE-NEXT:    ldr r3, [r0]
 ; THUMB-ENABLE-NEXT:    cmp r0, #0
 ; THUMB-ENABLE-NEXT:    bne LBB11_2
 ; THUMB-ENABLE-NEXT:  @ %bb.4: @ in Loop: Header=BB11_3 Depth=1
 ; THUMB-ENABLE-NEXT:    mov r0, r1
 ; THUMB-ENABLE-NEXT:    mov r1, r3
 ; THUMB-ENABLE-NEXT:    mov r2, r0
 ; THUMB-ENABLE-NEXT:    b LBB11_3
 ; THUMB-ENABLE-NEXT:  LBB11_5: @ %end
 ; THUMB-ENABLE-NEXT:    bx lr
+; THUMB-ENABLE-NEXT:  Lfunc_end11:
 ;
 ; THUMB-DISABLE-LABEL: infiniteloop3:
-; THUMB-DISABLE:       @ %bb.0: @ %entry
+; THUMB-DISABLE:       Lfunc_begin11:
+; THUMB-DISABLE-NEXT:  @ %bb.0: @ %entry
 ; THUMB-DISABLE-NEXT:    movs r0, #0
 ; THUMB-DISABLE-NEXT:    cbnz r0, LBB11_5
 ; THUMB-DISABLE-NEXT:  @ %bb.1: @ %loop2a.preheader
 ; THUMB-DISABLE-NEXT:    movs r1, #0
 ; THUMB-DISABLE-NEXT:    mov r2, r0
 ; THUMB-DISABLE-NEXT:    b LBB11_3
 ; THUMB-DISABLE-NEXT:  LBB11_2: @ %loop2b
 ; THUMB-DISABLE-NEXT:    @ in Loop: Header=BB11_3 Depth=1
 ; THUMB-DISABLE-NEXT:    str r1, [r2]
 ; THUMB-DISABLE-NEXT:    mov r2, r1
 ; THUMB-DISABLE-NEXT:    mov r1, r3
 ; THUMB-DISABLE-NEXT:  LBB11_3: @ %loop1
 ; THUMB-DISABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; THUMB-DISABLE-NEXT:    ldr r3, [r0]
 ; THUMB-DISABLE-NEXT:    cmp r0, #0
 ; THUMB-DISABLE-NEXT:    bne LBB11_2
 ; THUMB-DISABLE-NEXT:  @ %bb.4: @ in Loop: Header=BB11_3 Depth=1
 ; THUMB-DISABLE-NEXT:    mov r0, r1
 ; THUMB-DISABLE-NEXT:    mov r1, r3
 ; THUMB-DISABLE-NEXT:    mov r2, r0
 ; THUMB-DISABLE-NEXT:    b LBB11_3
 ; THUMB-DISABLE-NEXT:  LBB11_5: @ %end
 ; THUMB-DISABLE-NEXT:    bx lr
+; THUMB-DISABLE-NEXT:  Lfunc_end11:
 entry:
   br i1 undef, label %loop2a, label %body
 
 body:                                             ; preds = %entry
   br i1 undef, label %loop2a, label %end
 
 loop1:                                            ; preds = %loop2a, %loop2b
   %var.phi = phi ptr [ %next.phi, %loop2b ], [ %var, %loop2a ]

 ; pop
 ;
 ; FIXME: This is flakey passing by finding 'bl' somewhere amongst the debug
 ; info (like labels named 'line_table) not because it's found a bl instruction.
 ;
 ; bl
 define float @debug_info(float %gamma, float %slopeLimit, i1 %or.cond, double %tmp) "frame-pointer"="all" {
 ; ARM-ENABLE-LABEL: debug_info:
-; ARM-ENABLE:       @ %bb.0: @ %bb
+; ARM-ENABLE:       Lfunc_begin12:
+; ARM-ENABLE-NEXT:  @ %bb.0: @ %bb
 ; ARM-ENABLE-NEXT:    push {r4, r7, lr}
 ; ARM-ENABLE-NEXT:    add r7, sp, #4
 ; ARM-ENABLE-NEXT:    sub r4, sp, #16
 ; ARM-ENABLE-NEXT:    bfc r4, #0, #4
 ; ARM-ENABLE-NEXT:    mov sp, r4
 ; ARM-ENABLE-NEXT:    tst r2, #1
 ; ARM-ENABLE-NEXT:    vst1.64 {d8, d9}, [r4:128]
 ; ARM-ENABLE-NEXT:    beq LBB12_2

 ; ARM-ENABLE-NEXT:    sub sp, r7, #4
 ; ARM-ENABLE-NEXT:    pop {r4, r7, pc}
 ; ARM-ENABLE-NEXT:    .p2align 2
 ; ARM-ENABLE-NEXT:  @ %bb.4:
 ; ARM-ENABLE-NEXT:    .data_region
 ; ARM-ENABLE-NEXT:  LCPI12_0:
 ; ARM-ENABLE-NEXT:    .long 0x00000000 @ float 0
 ; ARM-ENABLE-NEXT:    .end_data_region
+; ARM-ENABLE-NEXT:  Lfunc_end12:
 ;
 ; ARM-DISABLE-LABEL: debug_info:
-; ARM-DISABLE:       @ %bb.0: @ %bb
+; ARM-DISABLE:       Lfunc_begin12:
+; ARM-DISABLE-NEXT:  @ %bb.0: @ %bb
 ; ARM-DISABLE-NEXT:    push {r4, r7, lr}
 ; ARM-DISABLE-NEXT:    add r7, sp, #4
 ; ARM-DISABLE-NEXT:    sub r4, sp, #16
 ; ARM-DISABLE-NEXT:    bfc r4, #0, #4
 ; ARM-DISABLE-NEXT:    mov sp, r4
 ; ARM-DISABLE-NEXT:    tst r2, #1
 ; ARM-DISABLE-NEXT:    vst1.64 {d8, d9}, [r4:128]
 ; ARM-DISABLE-NEXT:    beq LBB12_2

 ; ARM-DISABLE-NEXT:    sub sp, r7, #4
 ; ARM-DISABLE-NEXT:    pop {r4, r7, pc}
 ; ARM-DISABLE-NEXT:    .p2align 2
 ; ARM-DISABLE-NEXT:  @ %bb.4:
 ; ARM-DISABLE-NEXT:    .data_region
 ; ARM-DISABLE-NEXT:  LCPI12_0:
 ; ARM-DISABLE-NEXT:    .long 0x00000000 @ float 0
 ; ARM-DISABLE-NEXT:    .end_data_region
+; ARM-DISABLE-NEXT:  Lfunc_end12:
 ;
 ; THUMB-ENABLE-LABEL: debug_info:
-; THUMB-ENABLE:       @ %bb.0: @ %bb
+; THUMB-ENABLE:       Lfunc_begin12:
+; THUMB-ENABLE-NEXT:  @ %bb.0: @ %bb
 ; THUMB-ENABLE-NEXT:    push {r4, r7, lr}
 ; THUMB-ENABLE-NEXT:    add r7, sp, #4
 ; THUMB-ENABLE-NEXT:    sub.w r4, sp, #16
 ; THUMB-ENABLE-NEXT:    bfc r4, #0, #4
 ; THUMB-ENABLE-NEXT:    mov sp, r4
 ; THUMB-ENABLE-NEXT:    lsls r1, r2, #31
 ; THUMB-ENABLE-NEXT:    vst1.64 {d8, d9}, [r4:128]
 ; THUMB-ENABLE-NEXT:    beq LBB12_2

 ; THUMB-ENABLE-NEXT:    mov sp, r4
 ; THUMB-ENABLE-NEXT:    pop {r4, r7, pc}
 ; THUMB-ENABLE-NEXT:    .p2align 2
 ; THUMB-ENABLE-NEXT:  @ %bb.4:
 ; THUMB-ENABLE-NEXT:    .data_region
 ; THUMB-ENABLE-NEXT:  LCPI12_0:
 ; THUMB-ENABLE-NEXT:    .long 0x00000000 @ float 0
 ; THUMB-ENABLE-NEXT:    .end_data_region
+; THUMB-ENABLE-NEXT:  Lfunc_end12:
 ;
 ; THUMB-DISABLE-LABEL: debug_info:
-; THUMB-DISABLE:       @ %bb.0: @ %bb
+; THUMB-DISABLE:       Lfunc_begin12:
+; THUMB-DISABLE-NEXT:  @ %bb.0: @ %bb
 ; THUMB-DISABLE-NEXT:    push {r4, r7, lr}
 ; THUMB-DISABLE-NEXT:    add r7, sp, #4
 ; THUMB-DISABLE-NEXT:    sub.w r4, sp, #16
 ; THUMB-DISABLE-NEXT:    bfc r4, #0, #4
 ; THUMB-DISABLE-NEXT:    mov sp, r4
 ; THUMB-DISABLE-NEXT:    lsls r1, r2, #31
 ; THUMB-DISABLE-NEXT:    vst1.64 {d8, d9}, [r4:128]
 ; THUMB-DISABLE-NEXT:    beq LBB12_2

 ; THUMB-DISABLE-NEXT:    mov sp, r4
 ; THUMB-DISABLE-NEXT:    pop {r4, r7, pc}
 ; THUMB-DISABLE-NEXT:    .p2align 2
 ; THUMB-DISABLE-NEXT:  @ %bb.4:
 ; THUMB-DISABLE-NEXT:    .data_region
 ; THUMB-DISABLE-NEXT:  LCPI12_0:
 ; THUMB-DISABLE-NEXT:    .long 0x00000000 @ float 0
 ; THUMB-DISABLE-NEXT:    .end_data_region
+; THUMB-DISABLE-NEXT:  Lfunc_end12:
 bb:
   br i1 %or.cond, label %bb3, label %bb13
 
 bb3:                                              ; preds = %bb
   %tmp4 = fcmp ogt float %gamma, 1.000000e+00
   %tmp5 = fadd double 1.000000e+00, %tmp
   %tmp6 = select i1 %tmp4, double %tmp5, double %tmp
   %tmp10 = tail call double @llvm.pow.f64(double %tmp, double %tmp)

llvm/test/CodeGen/PowerPC/BreakableToken-reduced.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-shrink-wrap=true %s -o - | FileCheck %s
 ;
-; Test the use of a non-R0 register to save/restore the LR in function 
+; Test the use of a non-R0 register to save/restore the LR in function
 ; prologue/epilogue.
 ; This problem can occur as a result of shrink wrapping, where the function
 ; prologue and epilogue are moved from the beginning/ending of the function. If
 ; register R0 is used before the prologue/epilogue blocks, then it cannot be
 ; used to save/restore the LR.
 ;
 ; TODO: Convert this to an MIR test once the infrastructure can support it.
 ;       To convert this to an MIR pass, generate MIR after register allocation
 ;       but before shrink wrapping and verify that has been used in the body of
-;       the function. This can be done with something like: 
+;       the function. This can be done with something like:
 ;         llc -stop-after stack-slot-coloring BreakableToken-reduced.ll > BreakableToken-reduced.mir
 ;
 ;       The resulting MIR file can then be used as input to llc, and only run
 ;       shrink wrapping and Prologue/Epilogue insertion on it. For example:
 ;         llc -start-after stack-slot-coloring -stop-after prologepilog BreakableToken-reduced.mir
-;       
+;
 ;       Verify in the resulting code that R0 is not used in the prologue/epilogue.
 ;
 ;       This currently cannot be done because the PrologEpilogInserter pass has
 ;       a dependency on the TargetPassConfig and StackProtector classes, which
 ;       are currently not serialized when generating the MIR.
 ;
 
 ; ModuleID = 'BreakableToken.cpp'

 %"struct.llvm::AlignedCharArrayUnion.143" = type { %"struct.llvm::AlignedCharArray.104" }
 %"struct.llvm::SmallVectorStorage.144" = type { [1 x %"struct.llvm::AlignedCharArrayUnion.143"] }
 %"class.std::set" = type { %"class.std::_Rb_tree.145" }
 %"class.std::_Rb_tree.145" = type { %"struct.std::_Rb_tree<clang::tooling::Replacement, clang::tooling::Replacement, std::_Identity<clang::tooling::Replacement>, std::less<clang::tooling::Replacement>, std::allocator<clang::tooling::Replacement> >::_Rb_tree_impl" }
 %"struct.std::_Rb_tree<clang::tooling::Replacement, clang::tooling::Replacement, std::_Identity<clang::tooling::Replacement>, std::less<clang::tooling::Replacement>, std::allocator<clang::tooling::Replacement> >::_Rb_tree_impl" = type { %"struct.std::less.149", %"struct.std::_Rb_tree_node_base", i64 }
 %"struct.std::less.149" = type { i8 }
 
 
-; Function Attrs: nounwind
-; CHECK-LABEL: @_ZN5clang6format22BreakableStringLiteral11insertBreakEjjSt4pairImjERNS0_17WhitespaceManagerE
-
-; Load a value into R0 before saving the LR
-; CHECK: lwz 0, {{[0-9]+([0-9]+)}}
-
-; Ensure the LR is saved using a different register - edit:D63152 prevents stack pop befor loads and stores
-; CHECK-NOT: mflr {{[1-9]+}}
-
-; Ensure the LR is restored using a different register
-; CHECK: mtlr {{[0-9]+}}
-; CHECK: blr
 define void @_ZN5clang6format22BreakableStringLiteral11insertBreakEjjSt4pairImjERNS0_17WhitespaceManagerE(ptr nocapture readonly %this, i32 zeroext %LineIndex, i32 zeroext %TailOffset, [2 x i64] %Split.coerce, ptr dereferenceable(1504) %Whitespaces) unnamed_addr #1 align 2 {
+; CHECK-LABEL: _ZN5clang6format22BreakableStringLiteral11insertBreakEjjSt4pairImjERNS0_17WhitespaceManagerE:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    .cfi_def_cfa_offset 160
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    .cfi_offset r28, -32
+; CHECK-NEXT:    .cfi_offset r29, -24
+; CHECK-NEXT:    .cfi_offset r30, -16
+; CHECK-NEXT:    std 28, -32(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 29, -24(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 30, -16(1) # 8-byte Folded Spill
+; CHECK-NEXT:    stdu 1, -160(1)
+; CHECK-NEXT:    std 0, 176(1)
+; CHECK-NEXT:    mr 12, 8
+; CHECK-NEXT:    ld 10, 56(3)
+; CHECK-NEXT:    lwz 0, 40(3)
+; CHECK-NEXT:    cmpldi 10, 0
+; CHECK-NEXT:    beq 0, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %if.end.i.i
+; CHECK-NEXT:    ld 9, 48(3)
+; CHECK-NEXT:    lbz 4, 0(9)
+; CHECK-NEXT:    cmpwi 4, 64
+; CHECK-NEXT:    b .LBB0_3
+; CHECK-NEXT:  .LBB0_2: # %entry._ZNK4llvm9StringRef10startswithES0_.exit_crit_edge
+; CHECK-NEXT:    ld 9, 48(3)
+; CHECK-NEXT:    crxor 2, 2, 2
+; CHECK-NEXT:  .LBB0_3: # %_ZNK4llvm9StringRef10startswithES0_.exit
+; CHECK-NEXT:    li 8, 0
+; CHECK-NEXT:    li 11, 1
+; CHECK-NEXT:    add 5, 6, 5
+; CHECK-NEXT:    lbz 29, 20(3)
+; CHECK-NEXT:    lwz 28, 16(3)
+; CHECK-NEXT:    ld 4, 8(3)
+; CHECK-NEXT:    iseleq 30, 11, 8
+; CHECK-NEXT:    ld 11, 64(3)
+; CHECK-NEXT:    ld 8, 72(3)
+; CHECK-NEXT:    add 5, 5, 10
+; CHECK-NEXT:    sub 3, 0, 30
+; CHECK-NEXT:    clrldi 5, 5, 32
+; CHECK-NEXT:    li 0, 1
+; CHECK-NEXT:    clrldi 6, 7, 32
+; CHECK-NEXT:    extsw 30, 3
+; CHECK-NEXT:    mr 3, 12
+; CHECK-NEXT:    mr 7, 11
+; CHECK-NEXT:    std 28, 112(1)
+; CHECK-NEXT:    std 0, 104(1)
+; CHECK-NEXT:    std 29, 96(1)
+; CHECK-NEXT:    std 30, 120(1)
+; CHECK-NEXT:    bl _ZN5clang6format17WhitespaceManager24replaceWhitespaceInTokenERKNS0_11FormatTokenEjjN4llvm9StringRefES6_bjji
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    addi 1, 1, 160
+; CHECK-NEXT:    ld 0, 16(1)
+; CHECK-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 29, -24(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 28, -32(1) # 8-byte Folded Reload
+; CHECK-NEXT:    mtlr 0
+; CHECK-NEXT:    blr
 entry:
   %Split.coerce.fca.0.extract = extractvalue [2 x i64] %Split.coerce, 0
   %Split.coerce.fca.1.extract = extractvalue [2 x i64] %Split.coerce, 1
   %StartColumn = getelementptr inbounds %"class.clang::format::BreakableStringLiteral", ptr %this, i64 0, i32 0, i32 1
   %0 = load i32, ptr %StartColumn, align 8, !tbaa !2
   %Prefix = getelementptr inbounds %"class.clang::format::BreakableStringLiteral", ptr %this, i64 0, i32 0, i32 2
   %Length.i.19 = getelementptr inbounds %"class.clang::format::BreakableStringLiteral", ptr %this, i64 0, i32 0, i32 2, i32 1
   %1 = load i64, ptr %Length.i.19, align 8, !tbaa !10

llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32SMALL-MIR %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32LARGE-MIR %s
 

 ; RUN: --check-prefixes=64LARGE-ASM,LARGE-ASM %s
 
 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -function-sections < %s | FileCheck \
 ; RUN: --check-prefix=FUNC-ASM %s
 
 ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -function-sections < %s | FileCheck \
 ; RUN: --check-prefix=FUNC-ASM %s
 
-  define i32 @jump_table(i32 %a) {
-  entry:
-    switch i32 %a, label %sw.epilog [
-      i32 1, label %sw.bb
-      i32 2, label %sw.bb1
-      i32 3, label %sw.bb2
-      i32 4, label %sw.bb3
-    ]
+; 32SMALL-ASM-LABEL: jump_table:
+; 32SMALL-ASM:       # %bb.0: # %entry
+; 32SMALL-ASM-NEXT:    addi 3, 3, -1
+; 32SMALL-ASM-NEXT:    cmplwi 3, 3
+; 32SMALL-ASM-NEXT:    bgt 0, L..BB0_6
+; 32SMALL-ASM-NEXT:  # %bb.1: # %entry
+; 32SMALL-ASM-NEXT:    lwz 4, L..C0(2) # %jump-table.0
+; 32SMALL-ASM-NEXT:    slwi 3, 3, 2
+; 32SMALL-ASM-NEXT:    lwzx 3, 3, 4
+; 32SMALL-ASM-NEXT:    add 3, 3, 4
+; 32SMALL-ASM-NEXT:    mtctr 3
+; 32SMALL-ASM-NEXT:    bctr
+; 32SMALL-ASM-NEXT:  L..BB0_2: # %sw.bb
+; 32SMALL-ASM-NEXT:    li 3, 0
+; 32SMALL-ASM-NEXT:    #APP
+; 32SMALL-ASM-NEXT:    #NO_APP
+; 32SMALL-ASM-NEXT:    blr
+; 32SMALL-ASM-NEXT:  L..BB0_3: # %sw.bb1
+; 32SMALL-ASM-NEXT:    li 3, 0
+; 32SMALL-ASM-NEXT:    #APP
+; 32SMALL-ASM-NEXT:    #NO_APP
+; 32SMALL-ASM-NEXT:    blr
+; 32SMALL-ASM-NEXT:  L..BB0_4: # %sw.bb2
+; 32SMALL-ASM-NEXT:    li 3, 0
+; 32SMALL-ASM-NEXT:    #APP
+; 32SMALL-ASM-NEXT:    #NO_APP
+; 32SMALL-ASM-NEXT:    blr
+; 32SMALL-ASM-NEXT:  L..BB0_5: # %sw.bb3
+; 32SMALL-ASM-NEXT:    #APP
+; 32SMALL-ASM-NEXT:    #NO_APP
+; 32SMALL-ASM-NEXT:  L..BB0_6: # %sw.epilog
+; 32SMALL-ASM-NEXT:    li 3, 0
+; 32SMALL-ASM-NEXT:    blr
+;
+; 32LARGE-ASM-LABEL: jump_table:
+; 32LARGE-ASM:       # %bb.0: # %entry
+; 32LARGE-ASM-NEXT:    addi 3, 3, -1
+; 32LARGE-ASM-NEXT:    cmplwi 3, 3
+; 32LARGE-ASM-NEXT:    bgt 0, L..BB0_6
+; 32LARGE-ASM-NEXT:  # %bb.1: # %entry
+; 32LARGE-ASM-NEXT:    addis 4, L..C0@u(2)
+; 32LARGE-ASM-NEXT:    slwi 3, 3, 2
+; 32LARGE-ASM-NEXT:    lwz 4, L..C0@l(4)
+; 32LARGE-ASM-NEXT:    lwzx 3, 3, 4
+; 32LARGE-ASM-NEXT:    add 3, 3, 4
+; 32LARGE-ASM-NEXT:    mtctr 3
+; 32LARGE-ASM-NEXT:    bctr
+; 32LARGE-ASM-NEXT:  L..BB0_2: # %sw.bb
+; 32LARGE-ASM-NEXT:    li 3, 0
+; 32LARGE-ASM-NEXT:    #APP
+; 32LARGE-ASM-NEXT:    #NO_APP
+; 32LARGE-ASM-NEXT:    blr
+; 32LARGE-ASM-NEXT:  L..BB0_3: # %sw.bb1
+; 32LARGE-ASM-NEXT:    li 3, 0
+; 32LARGE-ASM-NEXT:    #APP
+; 32LARGE-ASM-NEXT:    #NO_APP
+; 32LARGE-ASM-NEXT:    blr
+; 32LARGE-ASM-NEXT:  L..BB0_4: # %sw.bb2
+; 32LARGE-ASM-NEXT:    li 3, 0
+; 32LARGE-ASM-NEXT:    #APP
+; 32LARGE-ASM-NEXT:    #NO_APP
+; 32LARGE-ASM-NEXT:    blr
+; 32LARGE-ASM-NEXT:  L..BB0_5: # %sw.bb3
+; 32LARGE-ASM-NEXT:    #APP
+; 32LARGE-ASM-NEXT:    #NO_APP
+; 32LARGE-ASM-NEXT:  L..BB0_6: # %sw.epilog
+; 32LARGE-ASM-NEXT:    li 3, 0
+; 32LARGE-ASM-NEXT:    blr
+;
+; 64SMALL-ASM-LABEL: jump_table:
+; 64SMALL-ASM:       # %bb.0: # %entry
+; 64SMALL-ASM-NEXT:    addi 3, 3, -1
+; 64SMALL-ASM-NEXT:    cmplwi 3, 3
+; 64SMALL-ASM-NEXT:    bgt 0, L..BB0_6
+; 64SMALL-ASM-NEXT:  # %bb.1: # %entry
+; 64SMALL-ASM-NEXT:    ld 4, L..C0(2) # %jump-table.0
+; 64SMALL-ASM-NEXT:    rldic 3, 3, 2, 30
+; 64SMALL-ASM-NEXT:    lwax 3, 3, 4
+; 64SMALL-ASM-NEXT:    add 3, 3, 4
+; 64SMALL-ASM-NEXT:    mtctr 3
+; 64SMALL-ASM-NEXT:    bctr
+; 64SMALL-ASM-NEXT:  L..BB0_2: # %sw.bb
+; 64SMALL-ASM-NEXT:    li 3, 0
+; 64SMALL-ASM-NEXT:    #APP
+; 64SMALL-ASM-NEXT:    #NO_APP
+; 64SMALL-ASM-NEXT:    blr
+; 64SMALL-ASM-NEXT:  L..BB0_3: # %sw.bb1
+; 64SMALL-ASM-NEXT:    li 3, 0
+; 64SMALL-ASM-NEXT:    #APP
+; 64SMALL-ASM-NEXT:    #NO_APP
+; 64SMALL-ASM-NEXT:    blr
+; 64SMALL-ASM-NEXT:  L..BB0_4: # %sw.bb2
+; 64SMALL-ASM-NEXT:    li 3, 0
+; 64SMALL-ASM-NEXT:    #APP
+; 64SMALL-ASM-NEXT:    #NO_APP
+; 64SMALL-ASM-NEXT:    blr
+; 64SMALL-ASM-NEXT:  L..BB0_5: # %sw.bb3
+; 64SMALL-ASM-NEXT:    #APP
+; 64SMALL-ASM-NEXT:    #NO_APP
+; 64SMALL-ASM-NEXT:  L..BB0_6: # %sw.epilog
+; 64SMALL-ASM-NEXT:    li 3, 0
+; 64SMALL-ASM-NEXT:    blr
+;
+; 64LARGE-ASM-LABEL: jump_table:
+; 64LARGE-ASM:       # %bb.0: # %entry
+; 64LARGE-ASM-NEXT:    addi 3, 3, -1
+; 64LARGE-ASM-NEXT:    cmplwi 3, 3
+; 64LARGE-ASM-NEXT:    bgt 0, L..BB0_6
+; 64LARGE-ASM-NEXT:  # %bb.1: # %entry
+; 64LARGE-ASM-NEXT:    addis 4, L..C0@u(2)
+; 64LARGE-ASM-NEXT:    rldic 3, 3, 2, 30
+; 64LARGE-ASM-NEXT:    ld 4, L..C0@l(4)
+; 64LARGE-ASM-NEXT:    lwax 3, 3, 4
+; 64LARGE-ASM-NEXT:    add 3, 3, 4
+; 64LARGE-ASM-NEXT:    mtctr 3
+; 64LARGE-ASM-NEXT:    bctr
+; 64LARGE-ASM-NEXT:  L..BB0_2: # %sw.bb
+; 64LARGE-ASM-NEXT:    li 3, 0
+; 64LARGE-ASM-NEXT:    #APP
+; 64LARGE-ASM-NEXT:    #NO_APP
+; 64LARGE-ASM-NEXT:    blr
+; 64LARGE-ASM-NEXT:  L..BB0_3: # %sw.bb1
+; 64LARGE-ASM-NEXT:    li 3, 0
+; 64LARGE-ASM-NEXT:    #APP
+; 64LARGE-ASM-NEXT:    #NO_APP
+; 64LARGE-ASM-NEXT:    blr
+; 64LARGE-ASM-NEXT:  L..BB0_4: # %sw.bb2
+; 64LARGE-ASM-NEXT:    li 3, 0
+; 64LARGE-ASM-NEXT:    #APP
+; 64LARGE-ASM-NEXT:    #NO_APP
+; 64LARGE-ASM-NEXT:    blr
+; 64LARGE-ASM-NEXT:  L..BB0_5: # %sw.bb3
+; 64LARGE-ASM-NEXT:    #APP
+; 64LARGE-ASM-NEXT:    #NO_APP
+; 64LARGE-ASM-NEXT:  L..BB0_6: # %sw.epilog
+; 64LARGE-ASM-NEXT:    li 3, 0
+; 64LARGE-ASM-NEXT:    blr
 
-  sw.bb:
-    tail call void asm sideeffect "", ""()
-    br label %sw.epilog
 
-  sw.bb1:
-    tail call void asm sideeffect "", ""()
-    br label %sw.epilog
 
-  sw.bb2:
-    tail call void asm sideeffect "", ""()
-    br label %sw.epilog
 
-  sw.bb3:
-    tail call void asm sideeffect "", ""()
-    br label %sw.epilog
 
-  sw.epilog:
-    ret i32 0
-  }
-
-
-; 32SMALL-MIR: renamable $r[[REG1:[0-9]+]] = LWZtoc %jump-table.0, $r2 :: (load (s32) from got)
-; 32SMALL-MIR: renamable $r[[REG3:[0-9]+]] = RLWINM killed renamable $r[[REG2:[0-9]+]], 2, 0, 29
-; 32SMALL-MIR: renamable $r[[REG4:[0-9]+]] = LWZX killed renamable $r[[REG3]], renamable $r[[REG1]] :: (load (s32) from jump-table)
-; 32SMALL-MIR: renamable $r[[REG5:[0-9]+]] = ADD4 killed renamable $r[[REG4]], killed renamable $r[[REG1]]
-
-; 32LARGE-MIR: renamable $r[[REG1:[0-9]+]] = ADDIStocHA $r2, %jump-table.0
-; 32LARGE-MIR: renamable $r[[REG2:[0-9]+]] = LWZtocL %jump-table.0, killed renamable $r[[REG1]], implicit $r2 :: (load (s32) from got)
-; 32LARGE-MIR: renamable $r[[REG4:[0-9]+]] = RLWINM killed renamable $r[[REG3:[0-9]+]], 2, 0, 29
-; 32LARGE-MIR: renamable $r[[REG5:[0-9]+]] = LWZX killed renamable $r[[REG4]], renamable $r[[REG2]] :: (load (s32) from jump-table)
-; 32LARGE-MIR: renamable $r[[REG6:[0-9]+]] = ADD4 killed renamable $r[[REG5]], killed renamable $r[[REG2]]
-
-; 64SMALL-MIR: renamable $x[[REG1:[0-9]+]] = LDtocJTI %jump-table.0, $x2 :: (load (s64) from got)
-; 64SMALL-MIR: renamable $x[[REG3:[0-9]+]] = RLDIC killed renamable $x[[REG2:[0-9]+]], 2, 30
-; 64SMALL-MIR: renamable $x[[REG4:[0-9]+]] = LWAX killed renamable $x[[REG3]], renamable $x[[REG1]] :: (load (s32) from jump-table)
-; 64SMALL-MIR: renamable $x[[REG6:[0-9]+]] = ADD8 killed renamable $x[[REG4]], killed renamable $x[[REG1]]
-
-; 64LARGE-MIR: renamable $x[[REG1:[0-9]+]] = ADDIStocHA8 $x2, %jump-table.0
-; 64LARGE-MIR: renamable $x[[REG2:[0-9]+]] = LDtocL %jump-table.0, killed renamable $x[[REG1]], implicit $x2 :: (load (s64) from got)
-; 64LARGE-MIR: renamable $x[[REG4:[0-9]+]] = RLDIC killed renamable $x[[REG3:[0-9]+]], 2, 30
-; 64LARGE-MIR: renamable $x[[REG5:[0-9]+]] = LWAX killed renamable $x[[REG4]], renamable $x[[REG2]] :: (load (s32) from jump-table)
-; 64LARGE-MIR: renamable $x[[REG6:[0-9]+]] = ADD8 killed renamable $x[[REG5]], killed renamable $x[[REG2]]
-
-; 32SMALL-ASM-LABEL: jump_table
-; 32SMALL-ASM: .jump_table:
-; 32SMALL-ASM:      addi 3, 3, -1
-; 32SMALL-ASM:      cmplwi 3, 3
-; 32SMALL-ASM:      bgt 0, L..BB0_6
-; 32SMALL-ASM:      lwz 4, L..C0(2)
-; 32SMALL-ASM:      slwi 3, 3, 2
-; 32SMALL-ASM:      lwzx 3, 3, 4
-; 32SMALL-ASM:      add 3, 3, 4
-; 32SMALL-ASM:      mtctr 3
-; 32SMALL-ASM:      bctr
-; 32SMALL-ASM: L..BB0_2:
-; 32SMALL-ASM: L..BB0_3:
-; 32SMALL-ASM: L..BB0_4:
-; 32SMALL-ASM: L..BB0_5:
-; 32SMALL-ASM: L..BB0_6:
-; 32SMALL-ASM:      li 3, 0
-; 32SMALL-ASM:      blr
-; 32SMALL-ASM:      .csect .rodata[RO],2
-; 32SMALL-ASM:      .align  2
-; 32SMALL-ASM: L..JTI0_0:
-; 32SMALL-ASM:      .vbyte  4, L..BB0_2-L..JTI0_0
-; 32SMALL-ASM:      .vbyte  4, L..BB0_3-L..JTI0_0
-; 32SMALL-ASM:      .vbyte  4, L..BB0_4-L..JTI0_0
-; 32SMALL-ASM:      .vbyte  4, L..BB0_5-L..JTI0_0
-
-; 32LARGE-ASM-LABEL: jump_table
-; 32LARGE-ASM: .jump_table:
-; 32LARGE-ASM:      addi 3, 3, -1
-; 32LARGE-ASM:      cmplwi  3, 3
-; 32LARGE-ASM:      bgt     0, L..BB0_6
-; 32LARGE-ASM:      addis 4, L..C0@u(2)
-; 32LARGE-ASM:      slwi 3, 3, 2
-; 32LARGE-ASM:      lwz 4, L..C0@l(4)
-; 32LARGE-ASM:      lwzx 3, 3, 4
-; 32LARGE-ASM:      add 3, 3, 4
-; 32LARGE-ASM:      mtctr 3
-; 32LARGE-ASM:      bctr
-; 32LARGE-ASM: L..BB0_2:
-; 32LARGE-ASM: L..BB0_3:
-; 32LARGE-ASM: L..BB0_4:
-; 32LARGE-ASM: L..BB0_5:
-; 32LARGE-ASM: L..BB0_6:
-; 32LARGE-ASM:      li 3, 0
-; 32LARGE-ASM:      blr
-; 32LARGE-ASM:      .csect .rodata[RO],2
-; 32LARGE-ASM:      .align  2
-; 32LARGE-ASM: L..JTI0_0:
-; 32LARGE-ASM:      .vbyte  4, L..BB0_2-L..JTI0_0
-; 32LARGE-ASM:      .vbyte  4, L..BB0_3-L..JTI0_0
-; 32LARGE-ASM:      .vbyte  4, L..BB0_4-L..JTI0_0
-; 32LARGE-ASM:      .vbyte  4, L..BB0_5-L..JTI0_0
-
-; 64SMALL-ASM-LABEL: jump_table
-; 64SMALL-ASM: .jump_table:
-; 64SMALL-ASM:      addi 3, 3, -1
-; 64SMALL-ASM:      cmplwi  3, 3
-; 64SMALL-ASM:      bgt     0, L..BB0_6
-; 64SMALL-ASM:      ld 4, L..C0(2)
-; 64SMALL-ASM:      rldic 3, 3, 2, 30
-; 64SMALL-ASM:      lwax 3, 3, 4
-; 64SMALL-ASM:      add 3, 3, 4
-; 64SMALL-ASM:      mtctr 3
-; 64SMALL-ASM:      bctr
-; 64SMALL-ASM: L..BB0_2:
-; 64SMALL-ASM: L..BB0_3:
-; 64SMALL-ASM: L..BB0_4:
-; 64SMALL-ASM: L..BB0_5:
-; 64SMALL-ASM: L..BB0_6:
-; 64SMALL-ASM:      li 3, 0
-; 64SMALL-ASM:      blr
-; 64SMALL-ASM:      .csect .rodata[RO],2
-; 64SMALL-ASM:      .align  2
-; 64SMALL-ASM: L..JTI0_0:
-; 64SMALL-ASM:      .vbyte  4, L..BB0_2-L..JTI0_0
-; 64SMALL-ASM:      .vbyte  4, L..BB0_3-L..JTI0_0
-; 64SMALL-ASM:      .vbyte  4, L..BB0_4-L..JTI0_0
-; 64SMALL-ASM:      .vbyte  4, L..BB0_5-L..JTI0_0
-
-; 64LARGE-ASM-LABEL: jump_table
-; 64LARGE-ASM: .jump_table:
-; 64LARGE-ASM:      addi 3, 3, -1
-; 64LARGE-ASM:      cmplwi  3, 3
-; 64LARGE-ASM:      bgt     0, L..BB0_6
-; 64LARGE-ASM:      addis 4, L..C0@u(2)
-; 64LARGE-ASM:      rldic 3, 3, 2, 30
-; 64LARGE-ASM:      ld 4, L..C0@l(4)
-; 64LARGE-ASM:      lwax 3, 3, 4
-; 64LARGE-ASM:      add 3, 3, 4
-; 64LARGE-ASM:      mtctr 3
-; 64LARGE-ASM:      bctr
-; 64LARGE-ASM: L..BB0_2:
-; 64LARGE-ASM: L..BB0_3:
-; 64LARGE-ASM: L..BB0_4:
-; 64LARGE-ASM: L..BB0_5:
-; 64LARGE-ASM: L..BB0_6:
-; 64LARGE-ASM:      li 3, 0
-; 64LARGE-ASM:      blr
-; 64LARGE-ASM:      .csect .rodata[RO],2
-; 64LARGE-ASM:      .align  2
-; 64LARGE-ASM: L..JTI0_0:
-; 64LARGE-ASM:      .vbyte  4, L..BB0_2-L..JTI0_0
-; 64LARGE-ASM:      .vbyte  4, L..BB0_3-L..JTI0_0
-; 64LARGE-ASM:      .vbyte  4, L..BB0_4-L..JTI0_0
-; 64LARGE-ASM:      .vbyte  4, L..BB0_5-L..JTI0_0
-
-; FUNC-ASM:         .csect .jump_table[PR],5
-; FUNC-ASM: L..BB0_2:
-; FUNC-ASM: L..BB0_3:
-; FUNC-ASM: L..BB0_4:
-; FUNC-ASM: L..BB0_5:
-; FUNC-ASM: L..BB0_6:
-; FUNC-ASM:         li 3, 0
-; FUNC-ASM:         blr
-; FUNC-ASM:         .csect .rodata.jmp..jump_table[RO],2
-; FUNC-ASM:         .align  2
-; FUNC-ASM: L..JTI0_0:
-; FUNC-ASM:         .vbyte  4, L..BB0_2-L..JTI0_0
-; FUNC-ASM:         .vbyte  4, L..BB0_3-L..JTI0_0
-; FUNC-ASM:         .vbyte  4, L..BB0_4-L..JTI0_0
-; FUNC-ASM:         .vbyte  4, L..BB0_5-L..JTI0_0
-
-; SMALL-ASM: .toc
-; SMALL-ASM: .tc L..JTI0_0[TC],L..JTI0_0
-
-; LARGE-ASM: .toc
-; LARGE-ASM: .tc L..JTI0_0[TE],L..JTI0_0
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; 32LARGE-MIR: {{.*}}
+; 32SMALL-MIR: {{.*}}
+; 64LARGE-MIR: {{.*}}
+; 64SMALL-MIR: {{.*}}
+; FUNC-ASM: {{.*}}
+; LARGE-ASM: {{.*}}
+; SMALL-ASM: {{.*}}

llvm/test/CodeGen/PowerPC/licm-tocReg.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck -check-prefixes=CHECK,CHECKLX %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck -check-prefixes=CHECK,CHECKAIX %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck -check-prefixes=CHECK,CHECKAIX32 %s
 
 ; The instructions ADDIStocHA8/LDtocL are used to calculate the address of
 ; globals. The ones that are in bb.3.if.end could not be hoisted by Machine
 ; LICM due to BCTRL_LDinto_toc in bb2.if.then.  This call causes the compiler
 ; to insert a save TOC to stack before the call and load into X2 to restore TOC

 ;    %3 = LWZ 0, %14 :: (volatile dereferenceable load (s32) from @ga)
 ;    %19 = CMPW killed %15, killed %18
 ;    BCC 44, killed %19, %bb.2.if.then
 ;    B %bb.3.if.end
 
 @ga = external global i32, align 4
 @gb = external global i32, align 4
 define signext i32 @test(ptr nocapture %FP) local_unnamed_addr #0 {
-; CHECK-LABEL: test:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mflr 0
-; CHECKLX:        addis 4, 2, .LC0@toc@ha
-; CHECKLX-NEXT:   addis 5, 2, .LC1@toc@ha
-; CHECKLX-NEXT:   mr 12, 3
-; CHECKLX-NEXT:   ld 4, .LC0@toc@l(4)
-; CHECKLX-NEXT:   ld 5, .LC1@toc@l(5)
-; CHECKLX-NEXT:   lwz 6, 0(4)
-; CHECKLX-NEXT:   lwz 7, 0(5)
-; CHECKLX-NEXT:   cmpw 6, 7
-; CHECKLX-NEXT:   lwz 6, 0(4)
-; CHECKLX-NEXT:   bgt 0, .LBB0_2
-; CHECKLX-NOT:    addis {{[0-9]+}}, 2, .LC0@toc@ha
-; CHECKLX-NOT:    addis {{[0-9]+}}, 2, .LC1@toc@ha
-; CHECKLX-NEXT:   .p2align 5
-; CHECKLX-NEXT: .LBB0_1: # %if.end
-; CHECKLX-NOT:    addis {{[0-9]+}}, 2, .LC0@toc@ha
-; CHECKLX-NOT:    addis {{[0-9]+}}, 2, .LC1@toc@ha
-; CHECKAIX:        ld 5, L..C0(2)
-; CHECKAIX-NEXT:   ld 6, L..C1(2)
-; CHECKAIX-NEXT: L..BB0_1: # %if.end
-; CHECKAIX-NOT:    ld {{[0-9]+}}, L..C0(2)
-; CHECKAIX-NOT:    ld {{[0-9]+}}, L..C1(2)
-; CHECKAIX32:        lwz 5, L..C0(2)
-; CHECKAIX32-NEXT:   lwz 6, L..C1(2)
-; CHECKAIX32-NEXT: L..BB0_1: # %if.end
-; CHECKAIX32-NOT:    lwz 5, L..C0(2)
-; CHECKAIX32-NOT:    lwz 6, L..C1(2)
-; CHECK:    blr
+; CHECKLX-LABEL: test:
+; CHECKLX:       # %bb.0: # %entry
+; CHECKLX-NEXT:    mflr 0
+; CHECKLX-NEXT:    stdu 1, -32(1)
+; CHECKLX-NEXT:    std 2, 24(1)
+; CHECKLX-NEXT:    std 0, 48(1)
+; CHECKLX-NEXT:    .cfi_def_cfa_offset 32
+; CHECKLX-NEXT:    .cfi_offset lr, 16
+; CHECKLX-NEXT:    addis 4, 2, .LC0@toc@ha
+; CHECKLX-NEXT:    addis 5, 2, .LC1@toc@ha
+; CHECKLX-NEXT:    mr 12, 3
+; CHECKLX-NEXT:    ld 4, .LC0@toc@l(4)
+; CHECKLX-NEXT:    ld 5, .LC1@toc@l(5)
+; CHECKLX-NEXT:    lwz 6, 0(4)
+; CHECKLX-NEXT:    lwz 7, 0(5)
+; CHECKLX-NEXT:    cmpw 6, 7
+; CHECKLX-NEXT:    lwz 6, 0(4)
+; CHECKLX-NEXT:    bgt 0, .LBB0_2
+; CHECKLX-NEXT:    .p2align 5
+; CHECKLX-NEXT:  .LBB0_1: # %if.end
+; CHECKLX-NEXT:    #
+; CHECKLX-NEXT:    addi 3, 6, 1
+; CHECKLX-NEXT:    stw 3, 0(4)
+; CHECKLX-NEXT:    lwz 3, 0(4)
+; CHECKLX-NEXT:    lwz 6, 0(5)
+; CHECKLX-NEXT:    cmpw 3, 6
+; CHECKLX-NEXT:    lwz 6, 0(4)
+; CHECKLX-NEXT:    ble 0, .LBB0_1
+; CHECKLX-NEXT:  .LBB0_2: # %if.then
+; CHECKLX-NEXT:    extsw 3, 6
+; CHECKLX-NEXT:    mtctr 12
+; CHECKLX-NEXT:    bctrl
+; CHECKLX-NEXT:    ld 2, 24(1)
+; CHECKLX-NEXT:    addi 1, 1, 32
+; CHECKLX-NEXT:    ld 0, 16(1)
+; CHECKLX-NEXT:    mtlr 0
+; CHECKLX-NEXT:    blr
+;
+; CHECKAIX-LABEL: test:
+; CHECKAIX:       # %bb.0: # %entry
+; CHECKAIX-NEXT:    mflr 0
+; CHECKAIX-NEXT:    stdu 1, -112(1)
+; CHECKAIX-NEXT:    std 0, 128(1)
+; CHECKAIX-NEXT:    ld 5, L..C0(2) # @ga
+; CHECKAIX-NEXT:    ld 6, L..C1(2) # @gb
+; CHECKAIX-NEXT:  L..BB0_1: # %if.end
+; CHECKAIX-NEXT:    #
+; CHECKAIX-NEXT:    lwz 4, 0(5)
+; CHECKAIX-NEXT:    lwz 7, 0(6)
+; CHECKAIX-NEXT:    cmpw 4, 7
+; CHECKAIX-NEXT:    lwz 4, 0(5)
+; CHECKAIX-NEXT:    bgt 0, L..BB0_3
+; CHECKAIX-NEXT:  # %bb.2: # %if.end
+; CHECKAIX-NEXT:    #
+; CHECKAIX-NEXT:    addi 4, 4, 1
+; CHECKAIX-NEXT:    stw 4, 0(5)
+; CHECKAIX-NEXT:    b L..BB0_1
+; CHECKAIX-NEXT:  L..BB0_3: # %if.then
+; CHECKAIX-NEXT:    ld 5, 0(3)
+; CHECKAIX-NEXT:    ld 11, 16(3)
+; CHECKAIX-NEXT:    std 2, 40(1)
+; CHECKAIX-NEXT:    ld 2, 8(3)
+; CHECKAIX-NEXT:    extsw 3, 4
+; CHECKAIX-NEXT:    mtctr 5
+; CHECKAIX-NEXT:    bctrl
+; CHECKAIX-NEXT:    ld 2, 40(1)
+; CHECKAIX-NEXT:    addi 1, 1, 112
+; CHECKAIX-NEXT:    ld 0, 16(1)
+; CHECKAIX-NEXT:    mtlr 0
+; CHECKAIX-NEXT:    blr
+;
+; CHECKAIX32-LABEL: test:
+; CHECKAIX32:       # %bb.0: # %entry
+; CHECKAIX32-NEXT:    mflr 0
+; CHECKAIX32-NEXT:    stwu 1, -64(1)
+; CHECKAIX32-NEXT:    stw 0, 72(1)
+; CHECKAIX32-NEXT:    lwz 5, L..C0(2) # @ga
+; CHECKAIX32-NEXT:    lwz 6, L..C1(2) # @gb
+; CHECKAIX32-NEXT:  L..BB0_1: # %if.end
+; CHECKAIX32-NEXT:    #
+; CHECKAIX32-NEXT:    lwz 4, 0(5)
+; CHECKAIX32-NEXT:    lwz 7, 0(6)
+; CHECKAIX32-NEXT:    cmpw 4, 7
+; CHECKAIX32-NEXT:    lwz 4, 0(5)
+; CHECKAIX32-NEXT:    bgt 0, L..BB0_3
+; CHECKAIX32-NEXT:  # %bb.2: # %if.end
+; CHECKAIX32-NEXT:    #
+; CHECKAIX32-NEXT:    addi 4, 4, 1
+; CHECKAIX32-NEXT:    stw 4, 0(5)
+; CHECKAIX32-NEXT:    b L..BB0_1
+; CHECKAIX32-NEXT:  L..BB0_3: # %if.then
+; CHECKAIX32-NEXT:    lwz 5, 0(3)
+; CHECKAIX32-NEXT:    stw 2, 20(1)
+; CHECKAIX32-NEXT:    lwz 11, 8(3)
+; CHECKAIX32-NEXT:    mtctr 5
+; CHECKAIX32-NEXT:    lwz 2, 4(3)
+; CHECKAIX32-NEXT:    mr 3, 4
+; CHECKAIX32-NEXT:    bctrl
+; CHECKAIX32-NEXT:    lwz 2, 20(1)
+; CHECKAIX32-NEXT:    addi 1, 1, 64
+; CHECKAIX32-NEXT:    lwz 0, 8(1)
+; CHECKAIX32-NEXT:    mtlr 0
+; CHECKAIX32-NEXT:    blr
 entry:
   %0 = load volatile i32, ptr @ga, align 4
   %1 = load volatile i32, ptr @gb, align 4
   %cmp1 = icmp sgt i32 %0, %1
   %2 = load volatile i32, ptr @ga, align 4
   br i1 %cmp1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %if.end, %entry
   %.lcssa = phi i32 [ %2, %entry ], [ %6, %if.end ]
   %call = tail call signext i32 %FP(i32 signext %.lcssa) #1
   ret i32 %call
 
 if.end:                                           ; preds = %entry, %if.end
   %3 = phi i32 [ %6, %if.end ], [ %2, %entry ]
   %inc = add nsw i32 %3, 1
   store volatile i32 %inc, ptr @ga, align 4
   %4 = load volatile i32, ptr @ga, align 4
   %5 = load volatile i32, ptr @gb, align 4
   %cmp = icmp sgt i32 %4, %5
   %6 = load volatile i32, ptr @ga, align 4
   br i1 %cmp, label %if.then, label %if.end
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}

llvm/test/CodeGen/X86/callbr-asm-label-addr.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
 
 define i32 @test1(i32 %x) {
 ; CHECK-LABEL: test1:
-; CHECK:         .quad .Ltmp0
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    .quad .Ltmp0
 ; CHECK-NEXT:    .quad .LBB0_1
-; CHECK:         .LBB0_1: # Block address taken
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:  .LBB0_1: # Block address taken
 ; CHECK-NEXT:    # %bar
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    callq foo
-; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT:    callq foo@PLT
+; CHECK-NEXT:  .Ltmp0: # Block address taken
 ; CHECK-NEXT:  # %bb.2: # %baz
+; CHECK-NEXT:    movl %eax, %edi
+; CHECK-NEXT:    popq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    jmp mux@PLT # TAILCALL
 entry:
   callbr void asm sideeffect ".quad ${0:l}\0A\09.quad ${1:l}", "i,!i,~{dirflag},~{fpsr},~{flags}"(ptr blockaddress(@test1, %baz))
           to label %asm.fallthrough [label %bar]
 
 asm.fallthrough:
   br label %bar
 
 bar:

llvm/test/CodeGen/X86/x86-shrink-wrap-unwind.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mtriple=x86_64-apple-darwin10.6 < %s | FileCheck %s
 ; RUN: llc -mtriple=x86_64-linux < %s | FileCheck %s --check-prefix=NOCOMPACTUNWIND
 ;
 ; Note: This test cannot be merged with the shrink-wrapping tests
 ; because the booleans set on the command line take precedence on
 ; the target logic that disable shrink-wrapping.
 
 ; The current compact unwind scheme does not work when the prologue is not at
 ; the start (the instructions before the prologue cannot be described).
 ; Currently we choose to not perform shrink-wrapping for functions without FP
 ; not marked as nounwind. PR25614
 ;
 ; No shrink-wrapping should occur here, until the CFI information are fixed.
+
+define i32 @framelessUnwind(i32 %a, i32 %b) #0 {
 ; CHECK-LABEL: framelessUnwind:
-;
-; Prologue code.
-; (What we push does not matter. It should be some random sratch register.)
-; CHECK: pushq
-;
-; Compare the arguments and jump to exit.
-; After the prologue is set.
-; CHECK: movl %edi, [[ARG0CPY:%e[a-z]+]]
-; CHECK-NEXT: cmpl %esi, %edi
-; CHECK-NEXT: jge [[EXIT_LABEL:LBB[0-9_]+]]
-;
-; Store %a in the alloca.
-; CHECK: movl [[ARG0CPY]], 4(%rsp)
-; Set the alloca address in the second argument.
-; CHECK-NEXT: leaq 4(%rsp), %rsi
-; Set the first argument to zero.
-; CHECK-NEXT: xorl %edi, %edi
-; CHECK-NEXT: callq _doSomething
-;
-; CHECK: [[EXIT_LABEL]]:
-;
-; Without shrink-wrapping, epilogue is in the exit block.
-; Epilogue code. (What we pop does not matter.)
-; CHECK-NEXT: popq
-;
-; CHECK-NEXT: retq
-
-; On a platform which does not support compact unwind, shrink wrapping is enabled.
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    cmpl %esi, %edi
+; CHECK-NEXT:    jge LBB0_2
+; CHECK-NEXT:  ## %bb.1: ## %true
+; CHECK-NEXT:    movl %eax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    leaq {{[0-9]+}}(%rsp), %rsi
+; CHECK-NEXT:    xorl %edi, %edi
+; CHECK-NEXT:    callq _doSomething
+; CHECK-NEXT:  LBB0_2: ## %false
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    retq
+;
 ; NOCOMPACTUNWIND-LABEL: framelessUnwind:
-; NOCOMPACTUNWIND-NOT:     pushq
-; NOCOMPACTUNWIND:       # %bb.1:
+; NOCOMPACTUNWIND:       # %bb.0:
+; NOCOMPACTUNWIND-NEXT:    movl %edi, %eax
+; NOCOMPACTUNWIND-NEXT:    cmpl %esi, %edi
+; NOCOMPACTUNWIND-NEXT:    jge .LBB0_2
+; NOCOMPACTUNWIND-NEXT:  # %bb.1: # %true
 ; NOCOMPACTUNWIND-NEXT:    pushq %rax
-define i32 @framelessUnwind(i32 %a, i32 %b) #0 {
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa_offset 16
+; NOCOMPACTUNWIND-NEXT:    movl %eax, {{[0-9]+}}(%rsp)
+; NOCOMPACTUNWIND-NEXT:    leaq {{[0-9]+}}(%rsp), %rsi
+; NOCOMPACTUNWIND-NEXT:    xorl %edi, %edi
+; NOCOMPACTUNWIND-NEXT:    callq doSomething@PLT
+; NOCOMPACTUNWIND-NEXT:    addq $8, %rsp
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa_offset 8
+; NOCOMPACTUNWIND-NEXT:  .LBB0_2: # %false
+; NOCOMPACTUNWIND-NEXT:    retq
   %tmp = alloca i32, align 4
   %tmp2 = icmp slt i32 %a, %b
   br i1 %tmp2, label %true, label %false
 
 true:
   store i32 %a, ptr %tmp, align 4
   %tmp4 = call i32 @doSomething(i32 0, ptr %tmp)
   br label %false
 
 false:
   %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
   ret i32 %tmp.0
 }
 
 declare i32 @doSomething(i32, ptr)
 
 attributes #0 = { "frame-pointer"="none" }
 
 ; Shrink-wrapping should occur here. We have a frame pointer.
+define i32 @frameUnwind(i32 %a, i32 %b) #1 {
 ; CHECK-LABEL: frameUnwind:
-;
-; Compare the arguments and jump to exit.
-; No prologue needed.
-;
-; Compare the arguments and jump to exit.
-; After the prologue is set.
-; CHECK: movl %edi, [[ARG0CPY:%e[a-z]+]]
-; CHECK-NEXT: cmpl %esi, %edi
-; CHECK-NEXT: jge [[EXIT_LABEL:LBB[0-9_]+]]
-;
-; Prologue code.
-; CHECK: pushq %rbp
-; CHECK: movq %rsp, %rbp
-;
-; Store %a in the alloca.
-; CHECK: movl [[ARG0CPY]], -4(%rbp)
-; Set the alloca address in the second argument.
-; CHECK-NEXT: leaq -4(%rbp), %rsi
-; Set the first argument to zero.
-; CHECK-NEXT: xorl %edi, %edi
-; CHECK-NEXT: callq _doSomething
-;
-; Epilogue code. (What we pop does not matter.)
-; CHECK: popq %rbp
-;
-; CHECK: [[EXIT_LABEL]]:
-; CHECK-NEXT: retq
-define i32 @frameUnwind(i32 %a, i32 %b) #1 {
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    cmpl %esi, %edi
+; CHECK-NEXT:    jge LBB1_2
+; CHECK-NEXT:  ## %bb.1: ## %true
+; CHECK-NEXT:    pushq %rbp
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %rbp, -16
+; CHECK-NEXT:    movq %rsp, %rbp
+; CHECK-NEXT:    .cfi_def_cfa_register %rbp
+; CHECK-NEXT:    subq $16, %rsp
+; CHECK-NEXT:    movl %eax, -4(%rbp)
+; CHECK-NEXT:    leaq -4(%rbp), %rsi
+; CHECK-NEXT:    xorl %edi, %edi
+; CHECK-NEXT:    callq _doSomething
+; CHECK-NEXT:    addq $16, %rsp
+; CHECK-NEXT:    popq %rbp
+; CHECK-NEXT:  LBB1_2: ## %false
+; CHECK-NEXT:    retq
+;
+; NOCOMPACTUNWIND-LABEL: frameUnwind:
+; NOCOMPACTUNWIND:       # %bb.0:
+; NOCOMPACTUNWIND-NEXT:    movl %edi, %eax
+; NOCOMPACTUNWIND-NEXT:    cmpl %esi, %edi
+; NOCOMPACTUNWIND-NEXT:    jge .LBB1_2
+; NOCOMPACTUNWIND-NEXT:  # %bb.1: # %true
+; NOCOMPACTUNWIND-NEXT:    pushq %rbp
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa_offset 16
+; NOCOMPACTUNWIND-NEXT:    .cfi_offset %rbp, -16
+; NOCOMPACTUNWIND-NEXT:    movq %rsp, %rbp
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa_register %rbp
+; NOCOMPACTUNWIND-NEXT:    subq $16, %rsp
+; NOCOMPACTUNWIND-NEXT:    movl %eax, -4(%rbp)
+; NOCOMPACTUNWIND-NEXT:    leaq -4(%rbp), %rsi
+; NOCOMPACTUNWIND-NEXT:    xorl %edi, %edi
+; NOCOMPACTUNWIND-NEXT:    callq doSomething@PLT
+; NOCOMPACTUNWIND-NEXT:    addq $16, %rsp
+; NOCOMPACTUNWIND-NEXT:    popq %rbp
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa %rsp, 8
+; NOCOMPACTUNWIND-NEXT:    .cfi_restore %rbp
+; NOCOMPACTUNWIND-NEXT:  .LBB1_2: # %false
+; NOCOMPACTUNWIND-NEXT:    retq
   %tmp = alloca i32, align 4
   %tmp2 = icmp slt i32 %a, %b
   br i1 %tmp2, label %true, label %false
 
 true:
   store i32 %a, ptr %tmp, align 4
   %tmp4 = call i32 @doSomething(i32 0, ptr %tmp)
   br label %false
 
 false:
   %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
   ret i32 %tmp.0
 }
 
 attributes #1 = { "frame-pointer"="all" }
 
 ; Shrink-wrapping should occur here. We do not have to unwind.
+define i32 @framelessnoUnwind(i32 %a, i32 %b) #2 {
 ; CHECK-LABEL: framelessnoUnwind:
-;
-; Compare the arguments and jump to exit.
-; No prologue needed.
-;
-; Compare the arguments and jump to exit.
-; After the prologue is set.
-; CHECK: movl %edi, [[ARG0CPY:%e[a-z]+]]
-; CHECK-NEXT: cmpl %esi, %edi
-; CHECK-NEXT: jge [[EXIT_LABEL:LBB[0-9_]+]]
-;
-; Prologue code.
-; (What we push does not matter. It should be some random sratch register.)
-; CHECK: pushq
-;
-; Store %a in the alloca.
-; CHECK: movl [[ARG0CPY]], 4(%rsp)
-; Set the alloca address in the second argument.
-; CHECK-NEXT: leaq 4(%rsp), %rsi
-; Set the first argument to zero.
-; CHECK-NEXT: xorl %edi, %edi
-; CHECK-NEXT: callq _doSomething
-;
-; Epilogue code.
-; CHECK-NEXT: addq
-;
-; CHECK: [[EXIT_LABEL]]:
-; CHECK-NEXT: retq
-define i32 @framelessnoUnwind(i32 %a, i32 %b) #2 {
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    cmpl %esi, %edi
+; CHECK-NEXT:    jge LBB2_2
+; CHECK-NEXT:  ## %bb.1: ## %true
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    movl %eax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    leaq {{[0-9]+}}(%rsp), %rsi
+; CHECK-NEXT:    xorl %edi, %edi
+; CHECK-NEXT:    callq _doSomething
+; CHECK-NEXT:    addq $8, %rsp
+; CHECK-NEXT:  LBB2_2: ## %false
+; CHECK-NEXT:    retq
+;
+; NOCOMPACTUNWIND-LABEL: framelessnoUnwind:
+; NOCOMPACTUNWIND:       # %bb.0:
+; NOCOMPACTUNWIND-NEXT:    movl %edi, %eax
+; NOCOMPACTUNWIND-NEXT:    cmpl %esi, %edi
+; NOCOMPACTUNWIND-NEXT:    jge .LBB2_2
+; NOCOMPACTUNWIND-NEXT:  # %bb.1: # %true
+; NOCOMPACTUNWIND-NEXT:    pushq %rax
+; NOCOMPACTUNWIND-NEXT:    movl %eax, {{[0-9]+}}(%rsp)
+; NOCOMPACTUNWIND-NEXT:    leaq {{[0-9]+}}(%rsp), %rsi
+; NOCOMPACTUNWIND-NEXT:    xorl %edi, %edi
+; NOCOMPACTUNWIND-NEXT:    callq doSomething@PLT
+; NOCOMPACTUNWIND-NEXT:    addq $8, %rsp
+; NOCOMPACTUNWIND-NEXT:  .LBB2_2: # %false
+; NOCOMPACTUNWIND-NEXT:    retq
   %tmp = alloca i32, align 4
   %tmp2 = icmp slt i32 %a, %b
   br i1 %tmp2, label %true, label %false
 
 true:
   store i32 %a, ptr %tmp, align 4
   %tmp4 = call i32 @doSomething(i32 0, ptr %tmp)
   br label %false
 
 false:
   %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
   ret i32 %tmp.0
 }
 
 attributes #2 = { "frame-pointer"="none" nounwind }
 
 
 ; Check that we generate correct code for segmented stack.
 ; We used to emit the code at the entry point of the function
 ; instead of just before the prologue.
 ; For now, shrink-wrapping is disabled on segmented stack functions: PR26107.
-;
+define zeroext i1 @segmentedStack(ptr readonly %vk1, ptr readonly %vk2, i64 %key_size) #5 {
 ; CHECK-LABEL: segmentedStack:
-; CHECK: cmpq
-; CHECK-NEXT: jbe [[ENTRY_LABEL:LBB[0-9_]+]]
-;
-; In PR26107, we use to drop these two basic blocks, because
-; the segmentedStack entry block was jumping directly to
-; the place where the prologue is actually needed, which is
-; the call to memcmp.
-; Then, those two basic blocks did not have any predecessors
-; anymore and were removed.
-;
-; Check if vk1 is null
-; CHECK: testq %rdi, %rdi
-; CHECK-NEXT: je [[STRINGS_EQUAL:LBB[0-9_]+]]
-;
-; Check if vk2 is null
-; CHECK: testq %rsi, %rsi
-; CHECK-NEXT:  je [[STRINGS_EQUAL]]
-;
-; CHECK: [[STRINGS_EQUAL]]
-; CHECK: popq
-;
-; CHECK: [[ENTRY_LABEL]]:
-; CHECK: callq ___morestack
-; CHECK-NEXT: retq
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    cmpq %gs:816, %rsp
+; CHECK-NEXT:    jbe LBB3_7
+; CHECK-NEXT:  LBB3_1: ## %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    orq %rsi, %rax
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    testq %rdi, %rdi
+; CHECK-NEXT:    je LBB3_5
+; CHECK-NEXT:  ## %bb.2: ## %entry
+; CHECK-NEXT:    testq %rsi, %rsi
+; CHECK-NEXT:    je LBB3_5
+; CHECK-NEXT:  ## %bb.3: ## %if.end4.i
+; CHECK-NEXT:    movq 8(%rdi), %rdx
+; CHECK-NEXT:    cmpq 8(%rsi), %rdx
+; CHECK-NEXT:    jne LBB3_6
+; CHECK-NEXT:  ## %bb.4: ## %land.rhs.i.i
+; CHECK-NEXT:    movq (%rsi), %rsi
+; CHECK-NEXT:    movq (%rdi), %rdi
+; CHECK-NEXT:    callq _memcmp
+; CHECK-NEXT:    testl %eax, %eax
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:  LBB3_5: ## %__go_ptr_strings_equal.exit
+; CHECK-NEXT:    ## kill: def $al killed $al killed $eax
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  LBB3_6:
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    ## kill: def $al killed $al killed $eax
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  LBB3_7:
+; CHECK-NEXT:    movl $8, %r10d
+; CHECK-NEXT:    movl $0, %r11d
+; CHECK-NEXT:    callq ___morestack
+; CHECK-NEXT:    retq
+; CHECK-NEXT:    jmp LBB3_1
 ;
-
-define zeroext i1 @segmentedStack(ptr readonly %vk1, ptr readonly %vk2, i64 %key_size) #5 {
+; NOCOMPACTUNWIND-LABEL: segmentedStack:
+; NOCOMPACTUNWIND:       # %bb.0:
+; NOCOMPACTUNWIND-NEXT:    cmpq %fs:112, %rsp
+; NOCOMPACTUNWIND-NEXT:    jbe .LBB3_7
+; NOCOMPACTUNWIND-NEXT:  .LBB3_1: # %entry
+; NOCOMPACTUNWIND-NEXT:    pushq %rax
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa_offset 16
+; NOCOMPACTUNWIND-NEXT:    movq %rdi, %rax
+; NOCOMPACTUNWIND-NEXT:    orq %rsi, %rax
+; NOCOMPACTUNWIND-NEXT:    sete %al
+; NOCOMPACTUNWIND-NEXT:    testq %rdi, %rdi
+; NOCOMPACTUNWIND-NEXT:    je .LBB3_5
+; NOCOMPACTUNWIND-NEXT:  # %bb.2: # %entry
+; NOCOMPACTUNWIND-NEXT:    testq %rsi, %rsi
+; NOCOMPACTUNWIND-NEXT:    je .LBB3_5
+; NOCOMPACTUNWIND-NEXT:  # %bb.3: # %if.end4.i
+; NOCOMPACTUNWIND-NEXT:    movq 8(%rdi), %rdx
+; NOCOMPACTUNWIND-NEXT:    cmpq 8(%rsi), %rdx
+; NOCOMPACTUNWIND-NEXT:    jne .LBB3_6
+; NOCOMPACTUNWIND-NEXT:  # %bb.4: # %land.rhs.i.i
+; NOCOMPACTUNWIND-NEXT:    movq (%rsi), %rsi
+; NOCOMPACTUNWIND-NEXT:    movq (%rdi), %rdi
+; NOCOMPACTUNWIND-NEXT:    callq memcmp@PLT
+; NOCOMPACTUNWIND-NEXT:    testl %eax, %eax
+; NOCOMPACTUNWIND-NEXT:    sete %al
+; NOCOMPACTUNWIND-NEXT:  .LBB3_5: # %__go_ptr_strings_equal.exit
+; NOCOMPACTUNWIND-NEXT:    # kill: def $al killed $al killed $eax
+; NOCOMPACTUNWIND-NEXT:    popq %rcx
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa_offset 8
+; NOCOMPACTUNWIND-NEXT:    retq
+; NOCOMPACTUNWIND-NEXT:  .LBB3_6:
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa_offset 16
+; NOCOMPACTUNWIND-NEXT:    xorl %eax, %eax
+; NOCOMPACTUNWIND-NEXT:    # kill: def $al killed $al killed $eax
+; NOCOMPACTUNWIND-NEXT:    popq %rcx
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa_offset 8
+; NOCOMPACTUNWIND-NEXT:    retq
+; NOCOMPACTUNWIND-NEXT:  .LBB3_7:
+; NOCOMPACTUNWIND-NEXT:    movl $8, %r10d
+; NOCOMPACTUNWIND-NEXT:    movl $0, %r11d
+; NOCOMPACTUNWIND-NEXT:    callq __morestack
+; NOCOMPACTUNWIND-NEXT:    retq
+; NOCOMPACTUNWIND-NEXT:    jmp .LBB3_1
 entry:
   %cmp.i = icmp eq ptr %vk1, null
   %cmp1.i = icmp eq ptr %vk2, null
   %brmerge.i = or i1 %cmp.i, %cmp1.i
   %cmp1.mux.i = and i1 %cmp.i, %cmp1.i
   br i1 %brmerge.i, label %__go_ptr_strings_equal.exit, label %if.end4.i
 
 if.end4.i:                                        ; preds = %entry

 ; Check that correctly take into account the jumps to landing pad.
 ; We used to consider function that may throw like regular
 ; function calls.
 ; Therefore, in this example, we were happily inserting the epilogue
 ; right after the call to throw_exception. Because of that we would not
 ; execute the epilogue when an execption occur and bad things will
 ; happen.
 ; PR36513
-;
+define void @with_nounwind(i1 %cond) nounwind personality ptr @my_personality {
 ; CHECK-LABEL: with_nounwind:
-; Prologue
-; CHECK: push
-;
-; Jump to throw_exception:
-; CHECK-NEXT: .cfi_def_cfa_offset
-; CHECK-NEXT: testb $1, %dil
-; CHECK-NEXT: jne [[THROW_LABEL:LBB[0-9_]+]]
-; Else return exit
-; CHECK: popq
-; CHECK-NEXT: retq
-;
-; CHECK-NEXT: [[THROW_LABEL]]:
-; CHECK: callq  _throw_exception
-; Unreachable block...
-;
-; Epilogue must be after the landing pad.
-; CHECK-NOT: popq
-;
-; Look for the landing pad label.
-; CHECK: LBB{{[0-9_]+}}:
-; Epilogue on the landing pad
-; CHECK: popq
-; CHECK-NEXT: retq
-define void @with_nounwind(i1 %cond) nounwind personality ptr @my_personality {
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    testb $1, %dil
+; CHECK-NEXT:    jne LBB4_1
+; CHECK-NEXT:  ## %bb.4: ## %return
+; CHECK-NEXT:    popq %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  LBB4_1: ## %throw
+; CHECK-NEXT:  Ltmp0:
+; CHECK-NEXT:    callq _throw_exception
+; CHECK-NEXT:  Ltmp1:
+; CHECK-NEXT:  ## %bb.2: ## %unreachable
+; CHECK-NEXT:    ud2
+; CHECK-NEXT:  LBB4_3: ## %landing
+; CHECK-NEXT:  Ltmp2:
+; CHECK-NEXT:    popq %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  Lfunc_end0:
+;
+; NOCOMPACTUNWIND-LABEL: with_nounwind:
+; NOCOMPACTUNWIND:       # %bb.0: # %entry
+; NOCOMPACTUNWIND-NEXT:    pushq %rax
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa_offset 16
+; NOCOMPACTUNWIND-NEXT:    testb $1, %dil
+; NOCOMPACTUNWIND-NEXT:    jne .LBB4_1
+; NOCOMPACTUNWIND-NEXT:  # %bb.4: # %return
+; NOCOMPACTUNWIND-NEXT:    popq %rax
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa_offset 8
+; NOCOMPACTUNWIND-NEXT:    retq
+; NOCOMPACTUNWIND-NEXT:  .LBB4_1: # %throw
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa_offset 16
+; NOCOMPACTUNWIND-NEXT:  .Ltmp0:
+; NOCOMPACTUNWIND-NEXT:    callq throw_exception@PLT
+; NOCOMPACTUNWIND-NEXT:  .Ltmp1:
+; NOCOMPACTUNWIND-NEXT:  # %bb.2: # %unreachable
+; NOCOMPACTUNWIND-NEXT:  .LBB4_3: # %landing
+; NOCOMPACTUNWIND-NEXT:  .Ltmp2:
+; NOCOMPACTUNWIND-NEXT:    popq %rax
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa_offset 8
+; NOCOMPACTUNWIND-NEXT:    retq
 entry:
   br i1 %cond, label %throw, label %return
 
 throw:
   invoke void @throw_exception()
           to label %unreachable unwind label %landing
 
 unreachable:
   unreachable
 
 landing:
   %pad = landingpad { ptr, i32 }
           catch ptr null
   ret void
 
 return:
   ret void
 }
 
 ; Check landing pad again.
 ; This time checks that we can shrink-wrap when the epilogue does not
 ; span accross several blocks.
-;
-; CHECK-LABEL: with_nounwind_same_succ:
-;
-; Jump to throw_exception:
-; CHECK: testb $1, %dil
-; CHECK-NEXT: je [[RET_LABEL:LBB[0-9_]+]]
-;
-; Prologue
-; CHECK: push
-; CHECK: callq  _throw_exception
-;
-; Fallthrough label
-; CHECK: [[FALLTHROUGH_LABEL:LBB[0-9_]+]]
-; CHECK: nop
-; CHECK: popq
-;
-; CHECK: [[RET_LABEL]]
-; CHECK: retq
-;
-; Look for the landing pad label.
-; CHECK: LBB{{[0-9_]+}}:
-; Landing pad jumps to fallthrough
-; CHECK: jmp [[FALLTHROUGH_LABEL]]
 define void @with_nounwind_same_succ(i1 %cond) nounwind personality ptr @my_personality2 {
+; CHECK-LABEL: with_nounwind_same_succ:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    testb $1, %dil
+; CHECK-NEXT:    je LBB5_4
+; CHECK-NEXT:  ## %bb.1: ## %throw
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:  Ltmp3:
+; CHECK-NEXT:    callq _throw_exception
+; CHECK-NEXT:  Ltmp4:
+; CHECK-NEXT:  LBB5_3: ## %fallthrough
+; CHECK-NEXT:    ## InlineAsm Start
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    ## InlineAsm End
+; CHECK-NEXT:    popq %rax
+; CHECK-NEXT:  LBB5_4: ## %return
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  LBB5_2: ## %landing
+; CHECK-NEXT:  Ltmp5:
+; CHECK-NEXT:    jmp LBB5_3
+; CHECK-NEXT:  Lfunc_end1:
+;
+; NOCOMPACTUNWIND-LABEL: with_nounwind_same_succ:
+; NOCOMPACTUNWIND:       # %bb.0: # %entry
+; NOCOMPACTUNWIND-NEXT:    testb $1, %dil
+; NOCOMPACTUNWIND-NEXT:    je .LBB5_4
+; NOCOMPACTUNWIND-NEXT:  # %bb.1: # %throw
+; NOCOMPACTUNWIND-NEXT:    pushq %rax
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa_offset 16
+; NOCOMPACTUNWIND-NEXT:  .Ltmp3:
+; NOCOMPACTUNWIND-NEXT:    callq throw_exception@PLT
+; NOCOMPACTUNWIND-NEXT:  .Ltmp4:
+; NOCOMPACTUNWIND-NEXT:  .LBB5_3: # %fallthrough
+; NOCOMPACTUNWIND-NEXT:    #APP
+; NOCOMPACTUNWIND-NEXT:    nop
+; NOCOMPACTUNWIND-NEXT:    #NO_APP
+; NOCOMPACTUNWIND-NEXT:    popq %rax
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa_offset 8
+; NOCOMPACTUNWIND-NEXT:  .LBB5_4: # %return
+; NOCOMPACTUNWIND-NEXT:    retq
+; NOCOMPACTUNWIND-NEXT:  .LBB5_2: # %landing
+; NOCOMPACTUNWIND-NEXT:    .cfi_def_cfa_offset 16
+; NOCOMPACTUNWIND-NEXT:  .Ltmp5:
+; NOCOMPACTUNWIND-NEXT:    jmp .LBB5_3
 entry:
   br i1 %cond, label %throw, label %return
 
 throw:
   invoke void @throw_exception()
           to label %fallthrough unwind label %landing
 landing:
   %pad = landingpad { ptr, i32 }

llvm/test/CodeGen/X86/x86-win64-shrink-wrapping.ll

-; RUN: llc %s -o - -enable-shrink-wrap=true | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
-; RUN: llc %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc %s -o - -enable-shrink-wrap=true | FileCheck %s --check-prefix=ENABLE
+; RUN: llc %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=DISABLE
 
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 target triple = "x86_64--windows-gnu"
 
 ; The output of this function with or without shrink-wrapping
 ; shouldn't change.
 ; Indeed, the epilogue block would have been if.else, meaning
 ; after the pops, we will have additional instruction (jump, mov,
 ; etc.) prior to the return and this is forbidden for Win64.
-; CHECK-LABEL: loopInfoSaveOutsideLoop:
-; CHECK: push
-; CHECK-NOT: popq
-; CHECK: popq
-; CHECK-NOT: popq
-; CHECK-NEXT: retq
 define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) #0 {
+; ENABLE-LABEL: loopInfoSaveOutsideLoop:
+; ENABLE:       # %bb.0: # %entry
+; ENABLE-NEXT:    pushq %rbx
+; ENABLE-NEXT:    .seh_pushreg %rbx
+; ENABLE-NEXT:    .seh_endprologue
+; ENABLE-NEXT:    testl %ecx, %ecx
+; ENABLE-NEXT:    je .LBB0_4
+; ENABLE-NEXT:  # %bb.1: # %for.preheader
+; ENABLE-NEXT:    #APP
+; ENABLE-NEXT:    nop
+; ENABLE-NEXT:    #NO_APP
+; ENABLE-NEXT:    xorl %eax, %eax
+; ENABLE-NEXT:    movl $10, %ecx
+; ENABLE-NEXT:    #APP
+; ENABLE-NEXT:    movl $1, %edx
+; ENABLE-NEXT:    #NO_APP
+; ENABLE-NEXT:    .p2align 4, 0x90
+; ENABLE-NEXT:  .LBB0_2: # %for.body
+; ENABLE-NEXT:    # =>This Inner Loop Header: Depth=1
+; ENABLE-NEXT:    addl %edx, %eax
+; ENABLE-NEXT:    decl %ecx
+; ENABLE-NEXT:    jne .LBB0_2
+; ENABLE-NEXT:  # %bb.3: # %for.end
+; ENABLE-NEXT:    #APP
+; ENABLE-NEXT:    nop
+; ENABLE-NEXT:    #NO_APP
+; ENABLE-NEXT:    shll $3, %eax
+; ENABLE-NEXT:    jmp .LBB0_5
+; ENABLE-NEXT:  .LBB0_4: # %if.else
+; ENABLE-NEXT:    movl %edx, %eax
+; ENABLE-NEXT:    addl %edx, %eax
+; ENABLE-NEXT:  .LBB0_5: # %if.end
+; ENABLE-NEXT:    popq %rbx
+; ENABLE-NEXT:    retq
+; ENABLE-NEXT:    .seh_endproc
+;
+; DISABLE-LABEL: loopInfoSaveOutsideLoop:
+; DISABLE:       # %bb.0: # %entry
+; DISABLE-NEXT:    pushq %rbx
+; DISABLE-NEXT:    .seh_pushreg %rbx
+; DISABLE-NEXT:    .seh_endprologue
+; DISABLE-NEXT:    testl %ecx, %ecx
+; DISABLE-NEXT:    je .LBB0_4
+; DISABLE-NEXT:  # %bb.1: # %for.preheader
+; DISABLE-NEXT:    #APP
+; DISABLE-NEXT:    nop
+; DISABLE-NEXT:    #NO_APP
+; DISABLE-NEXT:    xorl %eax, %eax
+; DISABLE-NEXT:    movl $10, %ecx
+; DISABLE-NEXT:    #APP
+; DISABLE-NEXT:    movl $1, %edx
+; DISABLE-NEXT:    #NO_APP
+; DISABLE-NEXT:    .p2align 4, 0x90
+; DISABLE-NEXT:  .LBB0_2: # %for.body
+; DISABLE-NEXT:    # =>This Inner Loop Header: Depth=1
+; DISABLE-NEXT:    addl %edx, %eax
+; DISABLE-NEXT:    decl %ecx
+; DISABLE-NEXT:    jne .LBB0_2
+; DISABLE-NEXT:  # %bb.3: # %for.end
+; DISABLE-NEXT:    #APP
+; DISABLE-NEXT:    nop
+; DISABLE-NEXT:    #NO_APP
+; DISABLE-NEXT:    shll $3, %eax
+; DISABLE-NEXT:    jmp .LBB0_5
+; DISABLE-NEXT:  .LBB0_4: # %if.else
+; DISABLE-NEXT:    movl %edx, %eax
+; DISABLE-NEXT:    addl %edx, %eax
+; DISABLE-NEXT:  .LBB0_5: # %if.end
+; DISABLE-NEXT:    popq %rbx
+; DISABLE-NEXT:    retq
+; DISABLE-NEXT:    .seh_endproc
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %for.preheader
 
 for.preheader:                                    ; preds = %entry
   tail call void asm "nop", ""()
   br label %for.body
 

 
 if.end:                                           ; preds = %if.else, %for.end
   %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
   ret i32 %sum.1
 }
 
 ; When we can sink the epilogue of the function into an existing exit block,
 ; this is Ok for shrink-wrapping to kicks in.
-; CHECK-LABEL: loopInfoSaveOutsideLoop2:
-; ENABLE: testl %ecx, %ecx
-; ENABLE-NEXT: je [[ELSE_LABEL:.LBB[0-9_]+]]
-;
-; Prologue code.
-; Make sure we save the CSR used in the inline asm: rbx.
-; CHECK: pushq %rbx
-;
-; DISABLE: testl %ecx, %ecx
-; DISABLE-NEXT: je [[ELSE_LABEL:.LBB[0-9_]+]]
-;
-; CHECK: nop
-; CHECK: xorl [[SUM:%eax]], [[SUM]]
-; CHECK-NEXT: movl $10, [[IV:%e[a-z]+]]
-;
-; CHECK: [[LOOP_LABEL:.LBB[0-9_]+]]: # %for.body
-; CHECK: movl $1, [[TMP:%e[a-z]+]]
-; CHECK: addl [[TMP]], [[SUM]]
-; CHECK-NEXT: decl [[IV]]
-; CHECK-NEXT: jne [[LOOP_LABEL]]
-; Next BB.
-; CHECK: nop
-; CHECK: shll $3, [[SUM]]
-;
-; DISABLE: jmp [[EPILOG_BB:.LBB[0-9_]+]]
-;
-; ENABLE-NEXT: popq %rbx
-; ENABLE-NEXT: retq
+define i32 @loopInfoSaveOutsideLoop2(i32 %cond, i32 %N) #0 {
+; ENABLE-LABEL: loopInfoSaveOutsideLoop2:
+; ENABLE:       # %bb.0: # %entry
+; ENABLE-NEXT:    testl %ecx, %ecx
+; ENABLE-NEXT:    je .LBB1_4
+; ENABLE-NEXT:  # %bb.1: # %for.preheader
+; ENABLE-NEXT:    pushq %rbx
+; ENABLE-NEXT:    .seh_pushreg %rbx
+; ENABLE-NEXT:    .seh_endprologue
+; ENABLE-NEXT:    #APP
+; ENABLE-NEXT:    nop
+; ENABLE-NEXT:    #NO_APP
+; ENABLE-NEXT:    xorl %eax, %eax
+; ENABLE-NEXT:    movl $10, %ecx
+; ENABLE-NEXT:    .p2align 4, 0x90
+; ENABLE-NEXT:  .LBB1_2: # %for.body
+; ENABLE-NEXT:    # =>This Inner Loop Header: Depth=1
+; ENABLE-NEXT:    #APP
+; ENABLE-NEXT:    movl $1, %edx
+; ENABLE-NEXT:    #NO_APP
+; ENABLE-NEXT:    addl %edx, %eax
+; ENABLE-NEXT:    decl %ecx
+; ENABLE-NEXT:    jne .LBB1_2
+; ENABLE-NEXT:  # %bb.3: # %for.end
+; ENABLE-NEXT:    #APP
+; ENABLE-NEXT:    nop
+; ENABLE-NEXT:    #NO_APP
+; ENABLE-NEXT:    shll $3, %eax
+; ENABLE-NEXT:    popq %rbx
+; ENABLE-NEXT:    retq
+; ENABLE-NEXT:  .LBB1_4: # %if.else
+; ENABLE-NEXT:    addl %edx, %edx
+; ENABLE-NEXT:    movl %edx, %eax
+; ENABLE-NEXT:    retq
+; ENABLE-NEXT:    .seh_endproc
 ;
-; CHECK: [[ELSE_LABEL]]: # %if.else
-; Shift second argument by one and store into returned register.
-; CHECK: addl %edx, %edx
-; CHECK: movl %edx, %eax
-;
-; DISABLE: [[EPILOG_BB]]: # %if.end
-; DISABLE-NEXT: popq %rbx
-;
-; CHECK: retq
-;
-define i32 @loopInfoSaveOutsideLoop2(i32 %cond, i32 %N) #0 {
+; DISABLE-LABEL: loopInfoSaveOutsideLoop2:
+; DISABLE:       # %bb.0: # %entry
+; DISABLE-NEXT:    pushq %rbx
+; DISABLE-NEXT:    .seh_pushreg %rbx
+; DISABLE-NEXT:    .seh_endprologue
+; DISABLE-NEXT:    testl %ecx, %ecx
+; DISABLE-NEXT:    je .LBB1_4
+; DISABLE-NEXT:  # %bb.1: # %for.preheader
+; DISABLE-NEXT:    #APP
+; DISABLE-NEXT:    nop
+; DISABLE-NEXT:    #NO_APP
+; DISABLE-NEXT:    xorl %eax, %eax
+; DISABLE-NEXT:    movl $10, %ecx
+; DISABLE-NEXT:    .p2align 4, 0x90
+; DISABLE-NEXT:  .LBB1_2: # %for.body
+; DISABLE-NEXT:    # =>This Inner Loop Header: Depth=1
+; DISABLE-NEXT:    #APP
+; DISABLE-NEXT:    movl $1, %edx
+; DISABLE-NEXT:    #NO_APP
+; DISABLE-NEXT:    addl %edx, %eax
+; DISABLE-NEXT:    decl %ecx
+; DISABLE-NEXT:    jne .LBB1_2
+; DISABLE-NEXT:  # %bb.3: # %for.end
+; DISABLE-NEXT:    #APP
+; DISABLE-NEXT:    nop
+; DISABLE-NEXT:    #NO_APP
+; DISABLE-NEXT:    shll $3, %eax
+; DISABLE-NEXT:    jmp .LBB1_5
+; DISABLE-NEXT:  .LBB1_4: # %if.else
+; DISABLE-NEXT:    addl %edx, %edx
+; DISABLE-NEXT:    movl %edx, %eax
+; DISABLE-NEXT:  .LBB1_5: # %if.end
+; DISABLE-NEXT:    popq %rbx
+; DISABLE-NEXT:    retq
+; DISABLE-NEXT:    .seh_endproc
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %for.preheader
 
 for.preheader:                                    ; preds = %entry
   tail call void asm "nop", ""()
   br label %for.body