- User Since
- Oct 21 2022, 12:19 AM (22 w, 4 d)
@qcolombet @nickdesaulniers Have addressed all the queries
Currently, depending upon whether the add/sub instruction can synthesize immediate directly, its decided whether to generate add/sub+immediate or mov+mla/mad/msb/mls ops.
Sun, Mar 26
Thu, Mar 23
Wed, Mar 22
@paulwalker-arm Any suggestions/improvements ?
Tue, Mar 21
Fri, Mar 17
This is reland attempt.
Tue, Mar 14
Thu, Mar 9
Wed, Mar 8
for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then integer element1 = UInt(Elem[operand1, e, esize]); integer element2 = UInt(Elem[operand2, e, esize]); integer product = element1 * element2; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; else Elem[result, e, esize] = Elem[**operand1**, e, esize];
Tue, Mar 7
Mon, Mar 6
@paulkirth Trying to address the issue you have mentioned in D145472. Thanks
Sun, Mar 5
@paulwalker-arm Any comments/suggestions on this ?
Thu, Mar 2
@junbuml I will take over this work next week.
Tue, Feb 28
Mon, Feb 27
Feb 23 2023
@sdesmalen I couldnt simplify the crashing test further. I hope this suffices
@paulwalker-arm adding test cases for
- Generating pseudo inst for MLA/MAD/MLS/MSUB
- Basic test cases on mul + add/sub as you had suggested in other patch
Feb 22 2023
@sdesmalen Have updated the patch. Thanks for the explanation
Feb 21 2023
Feb 20 2023
any suggestions/comments on the patch ?
@paulwalker-arm can you check now if this looks good ?
Feb 19 2023
Feb 15 2023
Could someone please have a look at the patch?
Feb 14 2023
Changed the logic to generate Psuedo instruction at ISel(which would be changed to actual instruction much later during ExpandPseudo pass) upon @paulwalker-arm suggestion
Feb 13 2023
Feb 8 2023
Adding a loop based test case to understand the effect of patch D142656 better
@junbuml Is it possible for you to rebase this patch and upstream it? With current LLVM trunk, its giving around 7% uplift on SPEC2017 povray
Feb 7 2023
One thing I missed out is a check if the invariant is taking part in vector ops. If its indeed taking part in vector ops, we will need vector registers for it. But, if it doesnt, then scalar registers should be sufficient.
Feb 6 2023
Feb 5 2023
@paulwalker-arm Thanks for the explanation. Let me check the example you have given and come up with implementation. If I cannot, will ask for your help
Feb 3 2023
- Uploading the full context
- Added a check that one of the addends is constant splat
- Made some cleanup
- Updated test for precommit test in D142998
Feb 1 2023
Jan 31 2023
@SjoerdMeijer Regarding doing the same thing at MachineCombiner stage. Even with current trunk, MLA/MLS for SVE is generated at ISel level. The line which you pointed was for scalar MADD. Also, its relatively easy to implement pattern matching at ISel rather than machine combiner for the reason that
- I am reusing pattern for 'mla'
- I dont need to get deep into intricate details needed at machine combiner level
@SjoerdMeijer Yes, I will add the patch with full context.
Jan 28 2023