[RISCV] Add i32 as a legal type for GPR register class.

[craig.topper]

Summary

I'm investigating if it is feasible to have i32 as a legal type for RV64.
The first thing we need to do is make i32 a valid type for the GPR
register class.

Unfortunately, this disables a lot of type inferencing in tablegen
and requires us to explicitly add XLenVT to many isel patterns.

This might also allow us to get rid of the GPRF16/32/64 register class
from Zhinx/Zfinx/Zdinx by adding f16/f32/f64 to GPR type. Those classes
appear to only exist for type inference purposes today. In all other ways
they are identical to the GPR class.

[craig.topper]

Rebase

[craig.topper]

Rebase

[sunshaoce]

I think if this contributes to achieving a similar effect as D153110 and further simplifies the Z*inx-related code, then it should be accepted.

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

 def XLenFVT : ValueTypeByHwMode<[RV32, RV64],
                                 [f32,  f64]>;
 def XLenRI : RegInfoByHwMode<
       [RV32,              RV64],
       [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
 
 // The order of registers represents the preferred allocation sequence.
 // Registers are listed in the order caller-save, callee-save, specials.
-def GPR : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (add
+def GPR : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (add
     (sequence "X%u", 10, 17),
     (sequence "X%u", 5, 7),
     (sequence "X%u", 28, 31),
     (sequence "X%u", 8, 9),
     (sequence "X%u", 18, 27),
     (sequence "X%u", 0, 4)
   )> {
   let RegInfos = XLenRI;
 }
 
-def GPRX0 : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (add X0)> {
+def GPRX0 : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (add X0)> {
   let RegInfos = XLenRI;
 }
 
-def GPRNoX0 : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (sub GPR, X0)> {
+def GPRNoX0 : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (sub GPR, X0)> {
   let RegInfos = XLenRI;
 }
 
-def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (sub GPR, X0, X2)> {
+def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (sub GPR, X0, X2)> {
   let RegInfos = XLenRI;
 }
 
 // Don't use X1 or X5 for JALR since that is a hint to pop the return address
 // stack on some microarchitectures. Also remove the reserved registers X0, X2,
 // X3, and X4 as it reduces the number of register classes that get synthesized
 // by tablegen.
-def GPRJALR : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (sub GPR, (sequence "X%u", 0, 5))> {
+def GPRJALR : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32,
+                            (sub GPR, (sequence "X%u", 0, 5))> {
   let RegInfos = XLenRI;
 }
 
-def GPRC : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (add
+def GPRC : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (add
     (sequence "X%u", 10, 15),
     (sequence "X%u", 8, 9)
   )> {
   let RegInfos = XLenRI;
 }
 
 // For indirect tail calls, we can't use callee-saved registers, as they are
 // restored to the saved value before the tail call, which would clobber a call
 // address. We shouldn't use x5 since that is a hint for to pop the return
 // address stack on some microarchitectures.
-def GPRTC : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (add
+def GPRTC : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (add
     (sequence "X%u", 6, 7),
     (sequence "X%u", 10, 17),
     (sequence "X%u", 28, 31)
   )> {
   let RegInfos = XLenRI;
 }
 
-def SP : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (add X2)> {
+def SP : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (add X2)> {
   let RegInfos = XLenRI;
 }
 
 // Saved Registers from s0 to s7, for C.MVA01S07 instruction in Zcmp extension
-def SR07 : RegisterClass<"RISCV", [XLenVT, XLenFVT], 32, (add
+def SR07 : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, (add
     (sequence "X%u", 8, 9),
     (sequence "X%u", 18, 23)
   )> {
   let RegInfos = XLenRI;
 }
 
 // Floating point registers
 let RegAltNameIndices = [ABIRegAltName] in {