[AMDGPU][Uniformity] SI_IF and SI_ELSE pseudos are always divergent

[sameerds]

llvm/include/llvm/ADT/GenericUniformityImpl.h

1150–1154

I guess I should lead with "On some targets, ..."

[ruiling]

llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/control-flow-intrinsics.mir

34

Although we do not have formal specification for the IF/ELSE instructions, I still prefer to see the tests are written using the well-formed pattern. that is SI_IF/SI_END_CF and SI_IF/SI_ELSE/SI_END_CF. My original concern over the SI_IF/SI_ELSE should be divergent is for the case that PHI node in merge block should be divergent(aka. sync depends on the branch). I would like this be covered in the tests.

[sameerds]

llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/control-flow-intrinsics.mir

34

I agree that MachineUA is currently not tested as extensively as the UA on LLVM IR. But this change is very specific, and the test being added is an equivalent of similar fragments in the LLVM IR tests. All we want to demonstrate here is that the control flow intrinsics are hard-coded to be divergent, even when the argument is uniform.

Separately, we need to translate all the LLVM IR test to equivalent MIR tests, and I am hoping that we can automate that once GlobalISel is ready for such use. For now, we do have some complete tests, and we deprecated some because the MIR in them was all wrong. But all this is definitely not happening in this change!

llvm/include/llvm/ADT/GenericUniformityImpl.h

GenericUniformityInfo<ContextT>::GenericUniformityInfo(
   DA->initialize();
   DA->compute();
 }
 
 template <typename ContextT>
 void GenericUniformityAnalysisImpl<ContextT>::print(raw_ostream &OS) const {
   bool haveDivergentArgs = false;
 
-  if (DivergentValues.empty()) {
-    assert(DivergentTermBlocks.empty());
-    assert(DivergentExitCycles.empty());
+  // Control flow instructions may be divergent even if their inputs are
+  // uniform. Thus, although exceedingly rare, it is possible to have a program
+  // with no divergent values but with divergent control structures.
+  if (DivergentValues.empty() && DivergentTermBlocks.empty() &&
+      DivergentExitCycles.empty()) {
     OS << "ALL VALUES UNIFORM\n";
     return;
   }
 
   for (const auto &entry : DivergentValues) {
     const BlockT *parent = Context.getDefBlock(entry);
     if (!parent) {
       if (!haveDivergentArgs) {

llvm/lib/Target/AMDGPU/SIInstructions.td

 }
 
 def SI_IF: CFPseudoInstSI <
   (outs SReg_1:$dst), (ins SReg_1:$vcc, brtarget:$target),
   [(set i1:$dst, (AMDGPUif i1:$vcc, bb:$target))], 1, 1> {
   let Constraints = "";
   let Size = 12;
   let hasSideEffects = 1;
+  let IsNeverUniform = 1;
 }
 
 def SI_ELSE : CFPseudoInstSI <
   (outs SReg_1:$dst),
   (ins SReg_1:$src, brtarget:$target), [], 1, 1> {
   let Size = 12;
   let hasSideEffects = 1;
+  let IsNeverUniform = 1;
 }
 
 def SI_WATERFALL_LOOP : CFPseudoInstSI <
   (outs),
   (ins brtarget:$target), [], 1> {
   let Size = 8;
   let isBranch = 1;
   let Defs = [];

llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/control-flow-intrinsics.mir

+# RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+
+---
+name:            f1
+body:             |
+  ; CHECK-LABEL: MachineUniformityInfo for function: f1
+  bb.0:
+    successors: %bb.1, %bb.2
+
+    ; CHECK-NOT: DIVERGENT: %1
+    %1:sreg_64(s64) = G_IMPLICIT_DEF
+    ; CHECK: DIVERGENT: {{.*}} SI_IF
+    %2:sreg_64 = SI_IF %1, %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+
+  bb.1:
+    SI_RETURN
+
+  bb.2:
+    G_BR %bb.1
+
+...
+
+---
+name:            f2
+body:             |
+  ; CHECK-LABEL: MachineUniformityInfo for function: f2
+  bb.0:
+    successors: %bb.1, %bb.2
+
+    ; CHECK-NOT: DIVERGENT: %1
+    %1:sreg_64(s64) = G_IMPLICIT_DEF
+    ; CHECK: DIVERGENT: {{.*}} SI_ELSE
+    %2:sreg_64 = SI_ELSE %1, %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+
+  bb.1:
+    SI_RETURN
+
+  bb.2:
+    G_BR %bb.1