[RISCV] Rework how implied SP operands work in the disassembler. NFC

[craig.topper]

Summary

Previously we added the SP operands when an immediate operand was added
to certain opcodes.

This patch moves it to a post processing step using the information
in MCInstrDesc. This avoids an explicit opcode list in RISCVDisassembler.cpp.

In considered using a custom DecoderMethod, but the bit swizzling we
need to do for the immediates on these instructions made that
unattractive.

[asb]

LGTM.

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

459

I know you just copied this from the previous function, but perhaps change to "Add implied SP operand for C.*SP compressed instructions. [...]"

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

 public:
   RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
                     MCInstrInfo const *MCII)
       : MCDisassembler(STI, Ctx), MCII(MCII) {}
 
   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
                               ArrayRef<uint8_t> Bytes, uint64_t Address,
                               raw_ostream &CStream) const override;
+
+private:
+  void addSPOperands(MCInst &MI) const;
 };
 } // end anonymous namespace
 
 static MCDisassembler *createRISCVDisassembler(const Target &T,
                                                const MCSubtargetInfo &STI,
                                                MCContext &Ctx) {
   return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
 }
case 0:
     break;
   case 1:
     break;
   }
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-// Add implied SP operand for instructions *SP compressed instructions. The SP
-// operand isn't explicitly encoded in the instruction.
-static void addImplySP(MCInst &Inst) {
-  if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
-      Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
-      Inst.getOpcode() == RISCV::C_FLWSP ||
-      Inst.getOpcode() == RISCV::C_FSWSP ||
-      Inst.getOpcode() == RISCV::C_FLDSP ||
-      Inst.getOpcode() == RISCV::C_FSDSP ||
-      Inst.getOpcode() == RISCV::C_ADDI4SPN) {
-    Inst.addOperand(MCOperand::createReg(RISCV::X2));
-  }
-  if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
-    Inst.addOperand(MCOperand::createReg(RISCV::X2));
-    Inst.addOperand(MCOperand::createReg(RISCV::X2));
-  }
-}
-
 template <unsigned N>
 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
                                       int64_t Address,
                                       const MCDisassembler *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
-  addImplySP(Inst);
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
 template <unsigned N>
 static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
                                              int64_t Address,
                                              const MCDisassembler *Decoder) {
   if (Imm == 0)
     return MCDisassembler::Fail;
   return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
 }
 
 template <unsigned N>
 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
                                       int64_t Address,
                                       const MCDisassembler *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
-  addImplySP(Inst);
   // Sign-extend the number in the bottom N bits of Imm
   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
   return MCDisassembler::Success;
 }
 
 template <unsigned N>
 static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
                                              int64_t Address,
static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
   if (IsWordOp)
     Inst.addOperand(MCOperand::createImm(3));
   else
     Inst.addOperand(MCOperand::createImm(4));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm,
                                     uint64_t Address, const void *Decoder) {
   if (Imm <= 3)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
 // spimm is based on rlist now.
 static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm,
                                     uint64_t Address, const void *Decoder) {
   // TODO: check if spimm matches rlist
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
+// Add implied SP operand for C.*SP compressed instructions. The SP operand
+// isn't explicitly encoded in the instruction.
+void RISCVDisassembler::addSPOperands(MCInst &MI) const {
+  const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
+  for (unsigned i = 0; i < MCID.getNumOperands(); i++)
+    if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
+      MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
+}
+
 DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
                                                ArrayRef<uint8_t> Bytes,
                                                uint64_t Address,
                                                raw_ostream &CS) const {
   // TODO: This will need modification when supporting instruction set
   // extensions with instructions > 32-bits (up to 176 bits wide).
   uint32_t Insn;
   DecodeStatus Result;
DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
   Insn = support::endian::read16le(Bytes.data());
 
   if (!STI.hasFeature(RISCV::Feature64Bit)) {
     LLVM_DEBUG(
         dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n");
     // Calling the auto-generated decoder function.
     Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address,
                                this, STI);
-    if (Result != MCDisassembler::Fail)
+    if (Result != MCDisassembler::Fail) {
+      addSPOperands(MI);
       return Result;
     }
+  }
   if (STI.hasFeature(RISCV::FeatureStdExtZcmt)) {
     LLVM_DEBUG(
         dbgs() << "Trying Zcmt table (16-bit Table Jump Instructions):\n");
     Result = decodeInstruction(DecoderTableRVZcmt16, MI, Insn, Address,
                                this, STI);
     if (Result != MCDisassembler::Fail)
       return Result;
   }
   if (STI.hasFeature(RISCV::FeatureStdExtZcmp)) {
     LLVM_DEBUG(
         dbgs()
         << "Trying Zcmp table (16-bit Push/Pop & Double Move Instructions):\n");
     Result =
         decodeInstruction(DecoderTableRVZcmp16, MI, Insn, Address, this, STI);
     if (Result != MCDisassembler::Fail)
       return Result;
   }
 
   LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
   // Calling the auto-generated decoder function.
-  return decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
+  Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
+  if (Result != MCDisassembler::Fail)
+    addSPOperands(MI);
+
+  return Result;
 }