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Differential D149655

[tests] Add missing REQUIRES: riscv-registered-target to clang test
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Authored by 4vtomat on May 2 2023, 8:26 AM.

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TWeaver
dyung

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Repository: rG LLVM Github Monorepo

Unit TestsFailed

	Time	Test
	3,750 ms	x64 debian > AddressSanitizer-x86_64-linux-dynamic.TestCases/Linux::auto_memory_profile_test.cpp

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4vtomat created this revision.May 2 2023, 8:26 AM

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4vtomat requested review of this revision.May 2 2023, 8:26 AM

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4vtomat added reviewers: TWeaver, dyung.May 2 2023, 8:27 AM

lgtm

This revision is now accepted and ready to land.May 2 2023, 9:00 AM

Harbormaster completed remote builds in B229445: Diff 518748.May 2 2023, 11:20 AM

Merged.

Revision Contents

Path

Size

clang/

test/

CodeGen/

RISCV/

rvv-intrinsics-autogenerated/

non-policy/

non-overloaded/

xsfvcp-x-rv64.c

1 line

1 line

1 line

1 line

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Diff 518748

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <sifive_vector.h>			#include <sifive_vector.h>

	#define p27_26 (0b11)			#define p27_26 (0b11)
	#define p24_20 (0b11111)			#define p24_20 (0b11111)
	#define p11_7 (0b11111)			#define p11_7 (0b11111)

	▲ Show 20 Lines • Show All 107 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s			// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
	// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <sifive_vector.h>			#include <sifive_vector.h>

	#define p27_26 (0b11)			#define p27_26 (0b11)
	#define p24_20 (0b11111)			#define p24_20 (0b11111)
	#define p11_7 (0b11111)			#define p11_7 (0b11111)
	▲ Show 20 Lines • Show All 1,681 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s			// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
	// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <sifive_vector.h>			#include <sifive_vector.h>

	#define p27_26 (0b11)			#define p27_26 (0b11)
	#define p26 (0b1)			#define p26 (0b1)
	#define p11_7 (0b11111)			#define p11_7 (0b11111)
	▲ Show 20 Lines • Show All 3,235 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s			// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
	// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <sifive_vector.h>			#include <sifive_vector.h>

	#define p27_26 (0b11)			#define p27_26 (0b11)
	#define p26 (0b1)			#define p26 (0b1)
	#define simm5 (10)			#define simm5 (10)
	▲ Show 20 Lines • Show All 3,234 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvw.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s			// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
	// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - \| opt -S -passes=mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <sifive_vector.h>			#include <sifive_vector.h>

	#define p27_26 (0b11)			#define p27_26 (0b11)
	#define p26 (0b1)			#define p26 (0b1)
	#define simm5 (10)			#define simm5 (10)
	▲ Show 20 Lines • Show All 2,268 Lines • Show Last 20 Lines