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Differential D149620

[NFC][HWASAN] Handle tags as Int8
Changes PlannedPublic

Authored by vitalybuka on May 1 2023, 3:17 PM.

Details

Reviewers
eugenis
fmayer
thurston
kstoimenov
Summary

And add custom value name.

Depends on D149619.

Diff Detail

Unit TestsFailed

TimeTest
110 msx64 debian > LLVM.Instrumentation/HWAddressSanitizer::stack-coloring.ll

Event Timeline

vitalybuka created this revision.May 1 2023, 3:17 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 1 2023, 3:17 PM
Herald added subscribers: luke, Enna1, frasercrmck and 21 others. · View Herald Transcript
vitalybuka requested review of this revision.May 1 2023, 3:17 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 1 2023, 3:17 PM
Herald added subscribers: llvm-commits, • pcwang-thead, MaskRay. · View Herald Transcript
vitalybuka added reviewers: eugenis, fmayer, thurston, kstoimenov.May 1 2023, 3:19 PM
Harbormaster completed remote builds in B229333: Diff 518576.May 1 2023, 4:03 PM
fmayer added a comment.May 12 2023, 8:19 AM

please explain in commit message why we are doing this

vitalybuka planned changes to this revision.Aug 2 2023, 1:17 PM
Herald added a subscriber: wangpc. · View Herald TranscriptAug 2 2023, 1:17 PM

Revision Contents

PathSize
llvm/
lib/
Transforms/
Instrumentation/
23 lines
test/
Instrumentation/
HWAddressSanitizer/
RISCV/
52 lines
70 lines
74 lines
59 lines
X86/
46 lines
25 lines
254 lines
76 lines
59 lines
54 lines
70 lines
70 lines
31 lines
299 lines
2 lines
61 lines
1663 lines

Diff 518576

llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp

Show First 20 Lines • Show All 983 Lines • ▼ Show 20 Lines
} }
void HWAddressSanitizer::tagAlloca(IRBuilder<> &IRB, AllocaInst *AI, void HWAddressSanitizer::tagAlloca(IRBuilder<> &IRB, AllocaInst *AI,
Value *ShadowPtr, Value *Tag, size_t Size) { Value *ShadowPtr, Value *Tag, size_t Size) {
size_t AlignedSize = alignTo(Size, Mapping.getObjectAlignment()); size_t AlignedSize = alignTo(Size, Mapping.getObjectAlignment());
if (!UseShortGranules) if (!UseShortGranules)
Size = AlignedSize; Size = AlignedSize;
Tag = IRB.CreateTrunc(Tag, IRB.getInt8Ty()); assert(Tag->getType() == Int8Ty);
if (InstrumentWithCalls) { if (InstrumentWithCalls) {
IRB.CreateCall(HwasanTagMemoryFunc, IRB.CreateCall(HwasanTagMemoryFunc,
{IRB.CreatePointerCast(AI, Int8PtrTy), Tag, {IRB.CreatePointerCast(AI, Int8PtrTy), Tag,
ConstantInt::get(IntptrTy, AlignedSize)}); ConstantInt::get(IntptrTy, AlignedSize)});
} else { } else {
size_t ShadowSize = Size >> Mapping.Scale; size_t ShadowSize = Size >> Mapping.Scale;
// If this memset is not inlined, it will be intercepted in the hwasan // If this memset is not inlined, it will be intercepted in the hwasan
// runtime library. That's OK, because the interceptor skips the checks if // runtime library. That's OK, because the interceptor skips the checks if
Show All 30 Linesunsigned HWAddressSanitizer::retagMask(unsigned AllocaNo) {
// https://github.com/google/sanitizers/blob/master/hwaddress-sanitizer/sort_masks.py // https://github.com/google/sanitizers/blob/master/hwaddress-sanitizer/sort_masks.py
static const unsigned FastMasks[] = { static const unsigned FastMasks[] = {
0, 128, 64, 192, 32, 96, 224, 112, 240, 48, 16, 120, 0, 128, 64, 192, 32, 96, 224, 112, 240, 48, 16, 120,
248, 56, 24, 8, 124, 252, 60, 28, 12, 4, 126, 254, 248, 56, 24, 8, 124, 252, 60, 28, 12, 4, 126, 254,
62, 30, 14, 6, 2, 127, 63, 31, 15, 7, 3, 1}; 62, 30, 14, 6, 2, 127, 63, 31, 15, 7, 3, 1};
return FastMasks[AllocaNo % std::size(FastMasks)]; return FastMasks[AllocaNo % std::size(FastMasks)];
} }
Value *HWAddressSanitizer::applyTagMask(IRBuilder<> &IRB, Value *OldTag) { Value *HWAddressSanitizer::applyTagMask(IRBuilder<> &IRB, Value *Tag) {
if (TagMaskByte == 0xFF) Tag = IRB.CreateTrunc(Tag, Int8Ty);
return OldTag; // No need to clear the tag byte. if (TagMaskByte != 0xFF) // No need to clear the tag byte.
return IRB.CreateAnd(OldTag, Tag = IRB.CreateAnd(Tag, ConstantInt::get(Tag->getType(), TagMaskByte));
ConstantInt::get(OldTag->getType(), TagMaskByte)); return Tag;
} }
Value *HWAddressSanitizer::getNextTagWithCall(IRBuilder<> &IRB) { Value *HWAddressSanitizer::getNextTagWithCall(IRBuilder<> &IRB) {
return IRB.CreateZExt(IRB.CreateCall(HwasanGenerateTagFunc), IntptrTy); return IRB.CreateCall(HwasanGenerateTagFunc);
} }
Value *HWAddressSanitizer::getStackBaseTag(IRBuilder<> &IRB) { Value *HWAddressSanitizer::getStackBaseTag(IRBuilder<> &IRB) {
if (ClGenerateTagsWithCalls) if (ClGenerateTagsWithCalls)
return nullptr; return nullptr;
if (StackBaseTag) if (StackBaseTag)
return StackBaseTag; return StackBaseTag;
// Extract some entropy from the stack pointer for the tags. // Extract some entropy from the stack pointer for the tags.
Show All 14 LinesValue *HWAddressSanitizer::getAllocaTag(IRBuilder<> &IRB, Value *StackTag,
return IRB.CreateXor( return IRB.CreateXor(
StackTag, ConstantInt::get(StackTag->getType(), retagMask(AllocaNo))); StackTag, ConstantInt::get(StackTag->getType(), retagMask(AllocaNo)));
} }
Value *HWAddressSanitizer::getUARTag(IRBuilder<> &IRB) { Value *HWAddressSanitizer::getUARTag(IRBuilder<> &IRB) {
Value *StackPointerLong = getSP(IRB); Value *StackPointerLong = getSP(IRB);
Value *UARTag = Value *UARTag =
applyTagMask(IRB, IRB.CreateLShr(StackPointerLong, PointerTagShift)); applyTagMask(IRB, IRB.CreateLShr(StackPointerLong, PointerTagShift));
UARTag->setName("hwasan.uar.tag"); UARTag->setName("hwasan.uar.tag");
return UARTag; return UARTag;
} }
// Add a tag to an address. // Add a tag to an address.
Value *HWAddressSanitizer::tagPointer(IRBuilder<> &IRB, Type *Ty, Value *HWAddressSanitizer::tagPointer(IRBuilder<> &IRB, Type *Ty,
Value *PtrLong, Value *Tag) { Value *PtrLong, Value *Tag) {
assert(!UsePageAliases); assert(!UsePageAliases);
Value *TaggedPtrLong; Value *TaggedPtrLong;
assert(Tag->getType() == Int8Ty);
Tag = IRB.CreateZExt(Tag, IntptrTy);
if (CompileKernel) { if (CompileKernel) {
// Kernel addresses have 0xFF in the most significant byte. // Kernel addresses have 0xFF in the most significant byte.
Value *ShiftedTag = Value *ShiftedTag =
IRB.CreateOr(IRB.CreateShl(Tag, PointerTagShift), IRB.CreateOr(IRB.CreateShl(Tag, PointerTagShift),
ConstantInt::get(IntptrTy, (1ULL << PointerTagShift) - 1)); ConstantInt::get(IntptrTy, (1ULL << PointerTagShift) - 1));
TaggedPtrLong = IRB.CreateAnd(PtrLong, ShiftedTag); TaggedPtrLong = IRB.CreateAnd(PtrLong, ShiftedTag);
} else { } else {
// Userspace can simply do OR (tag << PointerTagShift); // Userspace can simply do OR (tag << PointerTagShift);
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines case libcall: {
// recording stack history. // recording stack history.
Value *FrameRecordInfo = getFrameRecordInfo(IRB); Value *FrameRecordInfo = getFrameRecordInfo(IRB);
IRB.CreateCall(HwasanRecordFrameRecordFunc, {FrameRecordInfo}); IRB.CreateCall(HwasanRecordFrameRecordFunc, {FrameRecordInfo});
break; break;
} }
case instr: { case instr: {
ThreadLongMaybeUntagged = getThreadLongMaybeUntagged(); ThreadLongMaybeUntagged = getThreadLongMaybeUntagged();
StackBaseTag = IRB.CreateAShr(ThreadLong, 3); StackBaseTag = applyTagMask(IRB, IRB.CreateAShr(ThreadLong, 3));
// Store data to ring buffer. // Store data to ring buffer.
Value *FrameRecordInfo = getFrameRecordInfo(IRB); Value *FrameRecordInfo = getFrameRecordInfo(IRB);
Value *RecordPtr = IRB.CreateIntToPtr(ThreadLongMaybeUntagged, Value *RecordPtr = IRB.CreateIntToPtr(ThreadLongMaybeUntagged,
IntptrTy->getPointerTo(0)); IntptrTy->getPointerTo(0));
IRB.CreateStore(FrameRecordInfo, RecordPtr); IRB.CreateStore(FrameRecordInfo, RecordPtr);
// Update the ring buffer. Top byte of ThreadLong defines the size of the // Update the ring buffer. Top byte of ThreadLong defines the size of the
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines for (auto &KV : SInfo.AllocasToInstrument) {
memtag::AllocaInfo &Info = KV.second; memtag::AllocaInfo &Info = KV.second;
IRBuilder<> IRB(AI->getNextNode()); IRBuilder<> IRB(AI->getNextNode());
// Replace uses of the alloca with tagged address. // Replace uses of the alloca with tagged address.
Value *Tag = getAllocaTag(IRB, StackTag, N); Value *Tag = getAllocaTag(IRB, StackTag, N);
Value *AILong = IRB.CreatePointerCast(AI, IntptrTy); Value *AILong = IRB.CreatePointerCast(AI, IntptrTy);
Value *AINoTagLong = untagPointer(IRB, AILong); Value *AINoTagLong = untagPointer(IRB, AILong);
Value *ShadowPtr = memToShadow(AINoTagLong, IRB); Value *ShadowPtr = memToShadow(AINoTagLong, IRB);
Value *Replacement = tagPointer(IRB, AI->getType(), AILong, Tag); Value *Replacement = tagPointer(IRB, AI->getType(), AINoTagLong, Tag);
std::string Name = std::string Name =
AI->hasName() ? AI->getName().str() : "alloca." + itostr(N); AI->hasName() ? AI->getName().str() : "alloca." + itostr(N);
Tag->setName(Name + ".tag");
AINoTagLong->setName(Name + ".notag"); AINoTagLong->setName(Name + ".notag");
Replacement->setName(Name + ".hwasan"); Replacement->setName(Name + ".hwasan");
ShadowPtr->setName(Name + ".shadow"); ShadowPtr->setName(Name + ".shadow");
size_t Size = memtag::getAllocaSizeInBytes(*AI); size_t Size = memtag::getAllocaSizeInBytes(*AI);
size_t AlignedSize = alignTo(Size, Mapping.getObjectAlignment()); size_t AlignedSize = alignTo(Size, Mapping.getObjectAlignment());
Value *AICast = IRB.CreatePointerCast(AI, Int8PtrTy); Value *AICast = IRB.CreatePointerCast(AI, Int8PtrTy);
▲ Show 20 Lines • Show All 386 Lines • Show Last 20 Lines

llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca-with-calls.ll

Show All 9 Lines
define void @test_alloca() sanitize_hwaddress { define void @test_alloca() sanitize_hwaddress {
; CHECK-LABEL: define void @test_alloca ; CHECK-LABEL: define void @test_alloca
; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk { ; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8 ; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 72057594037927935 ; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 72057594037927935
; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP0]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP3:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i8
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP3]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 44 ; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[TMP4]] to i64
; CHECK-NEXT: [[TMP6:%.*]] = or i64 ptrtoint (ptr @test_alloca to i64), [[TMP5]] ; CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 44
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP1]] to ptr ; CHECK-NEXT: [[TMP7:%.*]] = or i64 ptrtoint (ptr @test_alloca to i64), [[TMP6]]
; CHECK-NEXT: store i64 [[TMP6]], ptr [[TMP7]], align 8 ; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP1]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = ashr i64 [[TMP0]], 56 ; CHECK-NEXT: store i64 [[TMP7]], ptr [[TMP8]], align 8
; CHECK-NEXT: [[TMP9:%.*]] = shl nuw nsw i64 [[TMP8]], 12 ; CHECK-NEXT: [[TMP9:%.*]] = ashr i64 [[TMP0]], 56
; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], -1 ; CHECK-NEXT: [[TMP10:%.*]] = shl nuw nsw i64 [[TMP9]], 12
; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[TMP0]], 8 ; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], -1
; CHECK-NEXT: [[TMP12:%.*]] = and i64 [[TMP11]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP0]], 8
; CHECK-NEXT: store i64 [[TMP12]], ptr @__hwasan_tls, align 8 ; CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], [[TMP11]]
; CHECK-NEXT: [[TMP13:%.*]] = or i64 [[TMP1]], 4294967295 ; CHECK-NEXT: store i64 [[TMP13]], ptr @__hwasan_tls, align 8
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP13]], 1 ; CHECK-NEXT: [[TMP14:%.*]] = or i64 [[TMP1]], 4294967295
; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP14]], 1
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP4]], 56 ; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[TMP16:%.*]] = lshr i64 [[TMP5]], 56
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP16]] to i8
; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; CHECK-NEXT: [[TMP15:%.*]] = call i8 @__hwasan_generate_tag() ; CHECK-NEXT: [[X_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; CHECK-NEXT: [[TMP16:%.*]] = zext i8 [[TMP15]] to i64
; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[X]] to i64 ; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP17]], 72057594037927935 ; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP17]], 72057594037927935
; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[X_NOTAG]], 4 ; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[X_NOTAG]], 4
; CHECK-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP18]] ; CHECK-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP15]], i64 [[TMP18]]
; CHECK-NEXT: [[TMP19:%.*]] = shl i64 [[TMP16]], 56 ; CHECK-NEXT: [[TMP19:%.*]] = zext i8 [[X_TAG]] to i64
; CHECK-NEXT: [[TMP20:%.*]] = or i64 [[TMP17]], [[TMP19]] ; CHECK-NEXT: [[TMP20:%.*]] = shl i64 [[TMP19]], 56
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP20]] to ptr ; CHECK-NEXT: [[TMP21:%.*]] = or i64 [[X_NOTAG]], [[TMP20]]
; CHECK-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP16]] to i8 ; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP21]] to ptr
; CHECK-NEXT: [[TMP22:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0 ; CHECK-NEXT: [[TMP22:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0
; CHECK-NEXT: store i8 4, ptr [[TMP22]], align 1 ; CHECK-NEXT: store i8 4, ptr [[TMP22]], align 1
; CHECK-NEXT: [[TMP23:%.*]] = getelementptr i8, ptr [[X]], i32 15 ; CHECK-NEXT: [[TMP23:%.*]] = getelementptr i8, ptr [[X]], i32 15
; CHECK-NEXT: store i8 [[TMP21]], ptr [[TMP23]], align 1 ; CHECK-NEXT: store i8 [[X_TAG]], ptr [[TMP23]], align 1
; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]) ; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]])
; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP24]], i64 1, i1 false)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%x = alloca i32, align 4 %x = alloca i32, align 4
call void @use32(ptr nonnull %x) call void @use32(ptr nonnull %x)
ret void ret void
} }

llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll

Show All 11 Lines
define void @test_alloca() sanitize_hwaddress !dbg !15 { define void @test_alloca() sanitize_hwaddress !dbg !15 {
; DYNAMIC-SHADOW-LABEL: define void @test_alloca ; DYNAMIC-SHADOW-LABEL: define void @test_alloca
; DYNAMIC-SHADOW-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk !dbg [[DBG7:![0-9]+]] { ; DYNAMIC-SHADOW-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk !dbg [[DBG7:![0-9]+]] {
; DYNAMIC-SHADOW-NEXT: entry: ; DYNAMIC-SHADOW-NEXT: entry:
; DYNAMIC-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow) ; DYNAMIC-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow)
; DYNAMIC-SHADOW-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; DYNAMIC-SHADOW-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; DYNAMIC-SHADOW-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64 ; DYNAMIC-SHADOW-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; DYNAMIC-SHADOW-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20 ; DYNAMIC-SHADOW-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; DYNAMIC-SHADOW-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP1]], [[TMP2]] ; DYNAMIC-SHADOW-NEXT: [[TMP3:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; DYNAMIC-SHADOW-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP1]], 56 ; DYNAMIC-SHADOW-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = trunc i64 [[TMP3]] to i8
; DYNAMIC-SHADOW-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP1]], 56
; DYNAMIC-SHADOW-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP4]] to i8
; DYNAMIC-SHADOW-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; DYNAMIC-SHADOW-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; DYNAMIC-SHADOW-NEXT: [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG10:![0-9]+]] ; DYNAMIC-SHADOW-NEXT: [[X_TAG:%.*]] = xor i8 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG10:![0-9]+]]
; DYNAMIC-SHADOW-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP4]], 72057594037927935, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP5]], 72057594037927935, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP5:%.*]] = lshr i64 [[X_NOTAG]], 4, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[TMP6:%.*]] = lshr i64 [[X_NOTAG]], 4, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP5]], !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP6]], !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP6:%.*]] = shl i64 [[TMP3]], 56, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[TMP7:%.*]] = zext i8 [[X_TAG]] to i64, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]], !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 56, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to ptr, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[TMP9:%.*]] = or i64 [[X_NOTAG]], [[TMP8]], !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP3]] to i8, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP9]] to ptr, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: store i8 4, ptr [[TMP9]], align 1, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: store i8 4, ptr [[TMP10]], align 1, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: store i8 [[TMP8]], ptr [[TMP10]], align 1, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: store i8 [[X_TAG]], ptr [[TMP11]], align 1, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: call void @llvm.dbg.value(metadata !DIArgList(ptr [[X]], ptr [[X]]), metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref)), !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: call void @llvm.dbg.value(metadata !DIArgList(ptr [[X]], ptr [[X]]), metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref)), !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13:![0-9]+]] ; DYNAMIC-SHADOW-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13:![0-9]+]]
; DYNAMIC-SHADOW-NEXT: [[TMP11:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8, !dbg [[DBG14:![0-9]+]] ; DYNAMIC-SHADOW-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false), !dbg [[DBG14:![0-9]+]]
; DYNAMIC-SHADOW-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP11]], i64 1, i1 false), !dbg [[DBG14]]
; DYNAMIC-SHADOW-NEXT: ret void, !dbg [[DBG14]] ; DYNAMIC-SHADOW-NEXT: ret void, !dbg [[DBG14]]
; ;
; ZERO-BASED-SHADOW-LABEL: define void @test_alloca ; ZERO-BASED-SHADOW-LABEL: define void @test_alloca
; ZERO-BASED-SHADOW-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk !dbg [[DBG7:![0-9]+]] { ; ZERO-BASED-SHADOW-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk !dbg [[DBG7:![0-9]+]] {
; ZERO-BASED-SHADOW-NEXT: entry: ; ZERO-BASED-SHADOW-NEXT: entry:
; ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; ZERO-BASED-SHADOW-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; ZERO-BASED-SHADOW-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; ZERO-BASED-SHADOW-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64 ; ZERO-BASED-SHADOW-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; ZERO-BASED-SHADOW-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20 ; ZERO-BASED-SHADOW-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; ZERO-BASED-SHADOW-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP1]], [[TMP2]] ; ZERO-BASED-SHADOW-NEXT: [[TMP3:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; ZERO-BASED-SHADOW-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP1]], 56 ; ZERO-BASED-SHADOW-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = trunc i64 [[TMP3]] to i8
; ZERO-BASED-SHADOW-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP1]], 56
; ZERO-BASED-SHADOW-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP4]] to i8
; ZERO-BASED-SHADOW-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; ZERO-BASED-SHADOW-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; ZERO-BASED-SHADOW-NEXT: [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG10:![0-9]+]] ; ZERO-BASED-SHADOW-NEXT: [[X_TAG:%.*]] = xor i8 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG10:![0-9]+]]
; ZERO-BASED-SHADOW-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP4]], 72057594037927935, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP5]], 72057594037927935, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP5:%.*]] = lshr i64 [[X_NOTAG]], 4, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[TMP6:%.*]] = lshr i64 [[X_NOTAG]], 4, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP5]] to ptr, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP6:%.*]] = shl i64 [[TMP3]], 56, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[TMP7:%.*]] = zext i8 [[X_TAG]] to i64, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]], !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 56, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to ptr, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[TMP9:%.*]] = or i64 [[X_NOTAG]], [[TMP8]], !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP3]] to i8, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP9]] to ptr, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: store i8 4, ptr [[TMP9]], align 1, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: store i8 4, ptr [[TMP10]], align 1, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: store i8 [[TMP8]], ptr [[TMP10]], align 1, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: store i8 [[X_TAG]], ptr [[TMP11]], align 1, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: call void @llvm.dbg.value(metadata !DIArgList(ptr [[X]], ptr [[X]]), metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref)), !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: call void @llvm.dbg.value(metadata !DIArgList(ptr [[X]], ptr [[X]]), metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref)), !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13:![0-9]+]] ; ZERO-BASED-SHADOW-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13:![0-9]+]]
; ZERO-BASED-SHADOW-NEXT: [[TMP11:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8, !dbg [[DBG14:![0-9]+]] ; ZERO-BASED-SHADOW-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false), !dbg [[DBG14:![0-9]+]]
; ZERO-BASED-SHADOW-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP11]], i64 1, i1 false), !dbg [[DBG14]]
; ZERO-BASED-SHADOW-NEXT: ret void, !dbg [[DBG14]] ; ZERO-BASED-SHADOW-NEXT: ret void, !dbg [[DBG14]]
; ;
entry: entry:
%x = alloca i32, align 4 %x = alloca i32, align 4
call void @llvm.dbg.value(metadata !DIArgList(ptr %x, ptr %x), metadata !22, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_deref)), !dbg !21 call void @llvm.dbg.value(metadata !DIArgList(ptr %x, ptr %x), metadata !22, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_deref)), !dbg !21
call void @use32(ptr nonnull %x), !dbg !23 call void @use32(ptr nonnull %x), !dbg !23
ret void, !dbg !24 ret void, !dbg !24
} }
Show All 22 Lines

llvm/test/Instrumentation/HWAddressSanitizer/RISCV/exception-lifetime.ll

Show All 15 Lines
define void @test() sanitize_hwaddress personality ptr @__gxx_personality_v0 { define void @test() sanitize_hwaddress personality ptr @__gxx_personality_v0 {
; CHECK-LABEL: define void @test ; CHECK-LABEL: define void @test
; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk.__gxx_personality_v0 { ; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk.__gxx_personality_v0 {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8 ; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 72057594037927935 ; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 72057594037927935
; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP0]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP3:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i8
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP3]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 44 ; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[TMP4]] to i64
; CHECK-NEXT: [[TMP6:%.*]] = or i64 ptrtoint (ptr @test to i64), [[TMP5]] ; CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 44
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP1]] to ptr ; CHECK-NEXT: [[TMP7:%.*]] = or i64 ptrtoint (ptr @test to i64), [[TMP6]]
; CHECK-NEXT: store i64 [[TMP6]], ptr [[TMP7]], align 8 ; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP1]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = ashr i64 [[TMP0]], 56 ; CHECK-NEXT: store i64 [[TMP7]], ptr [[TMP8]], align 8
; CHECK-NEXT: [[TMP9:%.*]] = shl nuw nsw i64 [[TMP8]], 12 ; CHECK-NEXT: [[TMP9:%.*]] = ashr i64 [[TMP0]], 56
; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], -1 ; CHECK-NEXT: [[TMP10:%.*]] = shl nuw nsw i64 [[TMP9]], 12
; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[TMP0]], 8 ; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], -1
; CHECK-NEXT: [[TMP12:%.*]] = and i64 [[TMP11]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP0]], 8
; CHECK-NEXT: store i64 [[TMP12]], ptr @__hwasan_tls, align 8 ; CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], [[TMP11]]
; CHECK-NEXT: [[TMP13:%.*]] = or i64 [[TMP1]], 4294967295 ; CHECK-NEXT: store i64 [[TMP13]], ptr @__hwasan_tls, align 8
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP13]], 1 ; CHECK-NEXT: [[TMP14:%.*]] = or i64 [[TMP1]], 4294967295
; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP14]], 1
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP4]], 56 ; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[TMP16:%.*]] = lshr i64 [[TMP5]], 56
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP16]] to i8
; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; CHECK-NEXT: [[TMP15:%.*]] = xor i64 [[TMP2]], 0 ; CHECK-NEXT: [[X_TAG:%.*]] = xor i8 [[TMP3]], 0
; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[X]] to i64 ; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP16]], 72057594037927935 ; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP17]], 72057594037927935
; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[X_NOTAG]], 4 ; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[X_NOTAG]], 4
; CHECK-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP17]] ; CHECK-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP15]], i64 [[TMP18]]
; CHECK-NEXT: [[TMP18:%.*]] = shl i64 [[TMP15]], 56 ; CHECK-NEXT: [[TMP19:%.*]] = zext i8 [[X_TAG]] to i64
; CHECK-NEXT: [[TMP19:%.*]] = or i64 [[TMP16]], [[TMP18]] ; CHECK-NEXT: [[TMP20:%.*]] = shl i64 [[TMP19]], 56
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP19]] to ptr ; CHECK-NEXT: [[TMP21:%.*]] = or i64 [[X_NOTAG]], [[TMP20]]
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP21]] to ptr
; CHECK-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 ; CHECK-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8
; CHECK-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr [[X]]) ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr [[X]])
; CHECK-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP15]] to i8 ; CHECK-NEXT: [[TMP22:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0
; CHECK-NEXT: [[TMP21:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0 ; CHECK-NEXT: store i8 4, ptr [[TMP22]], align 1
; CHECK-NEXT: store i8 4, ptr [[TMP21]], align 1 ; CHECK-NEXT: [[TMP23:%.*]] = getelementptr i8, ptr [[X]], i32 15
; CHECK-NEXT: [[TMP22:%.*]] = getelementptr i8, ptr [[X]], i32 15 ; CHECK-NEXT: store i8 [[X_TAG]], ptr [[TMP23]], align 1
; CHECK-NEXT: store i8 [[TMP20]], ptr [[TMP22]], align 1
; CHECK-NEXT: invoke void @mayFail(ptr [[X_HWASAN]]) ; CHECK-NEXT: invoke void @mayFail(ptr [[X_HWASAN]])
; CHECK-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] ; CHECK-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
; CHECK: invoke.cont: ; CHECK: invoke.cont:
; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP23]], i64 1, i1 false)
; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[X]]) ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[X]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: lpad: ; CHECK: lpad:
; CHECK-NEXT: [[TMP24:%.*]] = landingpad { ptr, i32 } ; CHECK-NEXT: [[TMP24:%.*]] = landingpad { ptr, i32 }
; CHECK-NEXT: cleanup ; CHECK-NEXT: cleanup
; CHECK-NEXT: [[TMP25:%.*]] = extractvalue { ptr, i32 } [[TMP24]], 0 ; CHECK-NEXT: [[TMP25:%.*]] = extractvalue { ptr, i32 } [[TMP24]], 0
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP14]], ptr [[EXN_SLOT]], i32 19) ; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP15]], ptr [[EXN_SLOT]], i32 19)
; CHECK-NEXT: store ptr [[TMP25]], ptr [[EXN_SLOT]], align 8 ; CHECK-NEXT: store ptr [[TMP25]], ptr [[EXN_SLOT]], align 8
; CHECK-NEXT: [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP24]], 1 ; CHECK-NEXT: [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP24]], 1
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP14]], ptr [[EHSELECTOR_SLOT]], i32 18) ; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP15]], ptr [[EHSELECTOR_SLOT]], i32 18)
; CHECK-NEXT: store i32 [[TMP26]], ptr [[EHSELECTOR_SLOT]], align 4 ; CHECK-NEXT: store i32 [[TMP26]], ptr [[EHSELECTOR_SLOT]], align 4
; CHECK-NEXT: call void @onExcept(ptr [[X_HWASAN]]) ; CHECK-NEXT: call void @onExcept(ptr [[X_HWASAN]])
; CHECK-NEXT: [[TMP27:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP27]], i64 1, i1 false)
; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[X]]) ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[X]])
; CHECK-NEXT: br label [[EH_RESUME:%.*]] ; CHECK-NEXT: br label [[EH_RESUME:%.*]]
; CHECK: eh.resume: ; CHECK: eh.resume:
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP14]], ptr [[EXN_SLOT]], i32 3) ; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP15]], ptr [[EXN_SLOT]], i32 3)
; CHECK-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 ; CHECK-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP14]], ptr [[EHSELECTOR_SLOT]], i32 2) ; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP15]], ptr [[EHSELECTOR_SLOT]], i32 2)
; CHECK-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 ; CHECK-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
; CHECK-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } undef, ptr [[EXN]], 0 ; CHECK-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } undef, ptr [[EXN]], 0
; CHECK-NEXT: [[LPAD_VAL1:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 ; CHECK-NEXT: [[LPAD_VAL1:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
; CHECK-NEXT: resume { ptr, i32 } [[LPAD_VAL1]] ; CHECK-NEXT: resume { ptr, i32 } [[LPAD_VAL1]]
; ;
entry: entry:
%x = alloca i32, align 8 %x = alloca i32, align 8
%exn.slot = alloca ptr, align 8 %exn.slot = alloca ptr, align 8
Show All 28 Lines

llvm/test/Instrumentation/HWAddressSanitizer/RISCV/use-after-scope-setjmp.ll

Show All 9 Lines
define dso_local noundef i1 @_Z6targetv() sanitize_hwaddress { define dso_local noundef i1 @_Z6targetv() sanitize_hwaddress {
; CHECK-LABEL: define dso_local noundef i1 @_Z6targetv ; CHECK-LABEL: define dso_local noundef i1 @_Z6targetv
; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk { ; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8 ; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 72057594037927935 ; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 72057594037927935
; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP0]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP3:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i8
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP3]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 44 ; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[TMP4]] to i64
; CHECK-NEXT: [[TMP6:%.*]] = or i64 ptrtoint (ptr @_Z6targetv to i64), [[TMP5]] ; CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 44
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP1]] to ptr ; CHECK-NEXT: [[TMP7:%.*]] = or i64 ptrtoint (ptr @_Z6targetv to i64), [[TMP6]]
; CHECK-NEXT: store i64 [[TMP6]], ptr [[TMP7]], align 8 ; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP1]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = ashr i64 [[TMP0]], 56 ; CHECK-NEXT: store i64 [[TMP7]], ptr [[TMP8]], align 8
; CHECK-NEXT: [[TMP9:%.*]] = shl nuw nsw i64 [[TMP8]], 12 ; CHECK-NEXT: [[TMP9:%.*]] = ashr i64 [[TMP0]], 56
; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], -1 ; CHECK-NEXT: [[TMP10:%.*]] = shl nuw nsw i64 [[TMP9]], 12
; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[TMP0]], 8 ; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], -1
; CHECK-NEXT: [[TMP12:%.*]] = and i64 [[TMP11]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP0]], 8
; CHECK-NEXT: store i64 [[TMP12]], ptr @__hwasan_tls, align 8 ; CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], [[TMP11]]
; CHECK-NEXT: [[TMP13:%.*]] = or i64 [[TMP1]], 4294967295 ; CHECK-NEXT: store i64 [[TMP13]], ptr @__hwasan_tls, align 8
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP13]], 1 ; CHECK-NEXT: [[TMP14:%.*]] = or i64 [[TMP1]], 4294967295
; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP14]], 1
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP4]], 56 ; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[TMP16:%.*]] = lshr i64 [[TMP5]], 56
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP16]] to i8
; CHECK-NEXT: [[BUF:%.*]] = alloca [4096 x i8], align 16 ; CHECK-NEXT: [[BUF:%.*]] = alloca [4096 x i8], align 16
; CHECK-NEXT: [[TMP15:%.*]] = xor i64 [[TMP2]], 0 ; CHECK-NEXT: [[BUF_TAG:%.*]] = xor i8 [[TMP3]], 0
; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[BUF]] to i64 ; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[BUF]] to i64
; CHECK-NEXT: [[BUF_NOTAG:%.*]] = and i64 [[TMP16]], 72057594037927935 ; CHECK-NEXT: [[BUF_NOTAG:%.*]] = and i64 [[TMP17]], 72057594037927935
; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[BUF_NOTAG]], 4 ; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[BUF_NOTAG]], 4
; CHECK-NEXT: [[BUF_SHADOW:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP17]] ; CHECK-NEXT: [[BUF_SHADOW:%.*]] = getelementptr i8, ptr [[TMP15]], i64 [[TMP18]]
; CHECK-NEXT: [[TMP18:%.*]] = shl i64 [[TMP15]], 56 ; CHECK-NEXT: [[TMP19:%.*]] = zext i8 [[BUF_TAG]] to i64
; CHECK-NEXT: [[TMP19:%.*]] = or i64 [[TMP16]], [[TMP18]] ; CHECK-NEXT: [[TMP20:%.*]] = shl i64 [[TMP19]], 56
; CHECK-NEXT: [[BUF_HWASAN:%.*]] = inttoptr i64 [[TMP19]] to ptr ; CHECK-NEXT: [[TMP21:%.*]] = or i64 [[BUF_NOTAG]], [[TMP20]]
; CHECK-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP15]] to i8 ; CHECK-NEXT: [[BUF_HWASAN:%.*]] = inttoptr i64 [[TMP21]] to ptr
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[BUF_SHADOW]], i8 [[TMP20]], i64 256, i1 false) ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[BUF_SHADOW]], i8 [[BUF_TAG]], i64 256, i1 false)
; CHECK-NEXT: [[CALL:%.*]] = call i32 @setjmp(ptr noundef @jbuf) ; CHECK-NEXT: [[CALL:%.*]] = call i32 @setjmp(ptr noundef @jbuf)
; CHECK-NEXT: switch i32 [[CALL]], label [[WHILE_BODY:%.*]] [ ; CHECK-NEXT: switch i32 [[CALL]], label [[WHILE_BODY:%.*]] [
; CHECK-NEXT: i32 1, label [[RETURN:%.*]] ; CHECK-NEXT: i32 1, label [[RETURN:%.*]]
; CHECK-NEXT: i32 2, label [[SW_BB1:%.*]] ; CHECK-NEXT: i32 2, label [[SW_BB1:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: sw.bb1: ; CHECK: sw.bb1:
; CHECK-NEXT: br label [[RETURN]] ; CHECK-NEXT: br label [[RETURN]]
; CHECK: while.body: ; CHECK: while.body:
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP14]], ptr @stackbuf, i32 19) ; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP15]], ptr @stackbuf, i32 19)
; CHECK-NEXT: store ptr [[BUF_HWASAN]], ptr @stackbuf, align 8 ; CHECK-NEXT: store ptr [[BUF_HWASAN]], ptr @stackbuf, align 8
; CHECK-NEXT: call void @may_jump() ; CHECK-NEXT: call void @may_jump()
; CHECK-NEXT: br label [[RETURN]] ; CHECK-NEXT: br label [[RETURN]]
; CHECK: return: ; CHECK: return:
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i1 [ true, [[WHILE_BODY]] ], [ true, [[SW_BB1]] ], [ false, [[ENTRY:%.*]] ] ; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i1 [ true, [[WHILE_BODY]] ], [ true, [[SW_BB1]] ], [ false, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP21:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[BUF_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 256, i1 false)
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[BUF_SHADOW]], i8 [[TMP21]], i64 256, i1 false)
; CHECK-NEXT: ret i1 [[RETVAL_0]] ; CHECK-NEXT: ret i1 [[RETVAL_0]]
; ;
entry: entry:
%buf = alloca [4096 x i8], align 1 %buf = alloca [4096 x i8], align 1
%call = call i32 @setjmp(ptr noundef @jbuf) %call = call i32 @setjmp(ptr noundef @jbuf)
switch i32 %call, label %while.body [ switch i32 %call, label %while.body [
i32 1, label %return i32 1, label %return
i32 2, label %sw.bb1 i32 2, label %sw.bb1
Show All 24 Lines

llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca-array.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt < %s -passes=hwasan -S | FileCheck %s ; RUN: opt < %s -passes=hwasan -S | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
declare void @use(ptr, ptr) declare void @use(ptr, ptr)
define void @test_alloca() sanitize_hwaddress { define void @test_alloca() sanitize_hwaddress {
; CHECK-LABEL: define void @test_alloca ; CHECK-LABEL: define void @test_alloca
; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk { ; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk {
; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 20 ; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 20
; CHECK-NEXT: [[TMP4:%.*]] = xor i64 [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[TMP4:%.*]] = xor i64 [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = and i64 [[TMP4]], 63 ; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP2]], 57 ; CHECK-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = and i8 [[TMP5]], 63
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP5]], 63 ; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP2]], 57
; CHECK-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i8
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP7]], 63
; CHECK-NEXT: [[X:%.*]] = alloca { [4 x i8], [12 x i8] }, align 16 ; CHECK-NEXT: [[X:%.*]] = alloca { [4 x i8], [12 x i8] }, align 16
; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0 ; CHECK-NEXT: [[X_TAG:%.*]] = xor i8 [[HWASAN_STACK_BASE_TAG]], 0
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[X]] to i64 ; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP7]], -9079256848778919937 ; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP8]], -9079256848778919937
; CHECK-NEXT: [[TMP8:%.*]] = lshr i64 [[X_NOTAG]], 4 ; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[X_NOTAG]], 4
; CHECK-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP8]] to ptr ; CHECK-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP9]] to ptr
; CHECK-NEXT: [[TMP9:%.*]] = shl i64 [[TMP6]], 57 ; CHECK-NEXT: [[TMP10:%.*]] = zext i8 [[X_TAG]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP7]], [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = shl i64 [[TMP10]], 57
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr ; CHECK-NEXT: [[TMP12:%.*]] = or i64 [[X_NOTAG]], [[TMP11]]
; CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP6]] to i8 ; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP12]] to ptr
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[TMP11]], i64 16) ; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[X_TAG]], i64 16)
; CHECK-NEXT: [[Y:%.*]] = alloca i8, i64 16, align 16 ; CHECK-NEXT: [[Y:%.*]] = alloca i8, i64 16, align 16
; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 1 ; CHECK-NEXT: [[Y_TAG:%.*]] = xor i8 [[HWASAN_STACK_BASE_TAG]], 1
; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[Y]] to i64 ; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[Y]] to i64
; CHECK-NEXT: [[Y_NOTAG:%.*]] = and i64 [[TMP13]], -9079256848778919937 ; CHECK-NEXT: [[Y_NOTAG:%.*]] = and i64 [[TMP13]], -9079256848778919937
; CHECK-NEXT: [[TMP14:%.*]] = lshr i64 [[Y_NOTAG]], 4 ; CHECK-NEXT: [[TMP14:%.*]] = lshr i64 [[Y_NOTAG]], 4
; CHECK-NEXT: [[Y_SHADOW:%.*]] = inttoptr i64 [[TMP14]] to ptr ; CHECK-NEXT: [[Y_SHADOW:%.*]] = inttoptr i64 [[TMP14]] to ptr
; CHECK-NEXT: [[TMP15:%.*]] = shl i64 [[TMP12]], 57 ; CHECK-NEXT: [[TMP15:%.*]] = zext i8 [[Y_TAG]] to i64
; CHECK-NEXT: [[TMP16:%.*]] = or i64 [[TMP13]], [[TMP15]] ; CHECK-NEXT: [[TMP16:%.*]] = shl i64 [[TMP15]], 57
; CHECK-NEXT: [[Y_HWASAN:%.*]] = inttoptr i64 [[TMP16]] to ptr ; CHECK-NEXT: [[TMP17:%.*]] = or i64 [[Y_NOTAG]], [[TMP16]]
; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP12]] to i8 ; CHECK-NEXT: [[Y_HWASAN:%.*]] = inttoptr i64 [[TMP17]] to ptr
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[Y]], i8 [[TMP17]], i64 16) ; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[Y]], i8 [[Y_TAG]], i64 16)
; CHECK-NEXT: call void @use(ptr [[X_HWASAN]], ptr [[Y_HWASAN]]) ; CHECK-NEXT: call void @use(ptr [[X_HWASAN]], ptr [[Y_HWASAN]])
; CHECK-NEXT: [[TMP18:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[HWASAN_UAR_TAG]], i64 16)
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[TMP18]], i64 16) ; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[Y]], i8 [[HWASAN_UAR_TAG]], i64 16)
; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[Y]], i8 [[TMP19]], i64 16)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%x = alloca i8, i64 4 %x = alloca i8, i64 4
%y = alloca i8, i64 16 %y = alloca i8, i64 16
call void @use(ptr %x, ptr %y) call void @use(ptr %x, ptr %y)
ret void ret void
} }

llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca-with-calls.ll

Show All 10 Lines
define void @test_alloca() sanitize_hwaddress { define void @test_alloca() sanitize_hwaddress {
; CHECK-LABEL: define void @test_alloca ; CHECK-LABEL: define void @test_alloca
; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk { ; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 57 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 57
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP2]], 63 ; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i8
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP3]], 63
; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; CHECK-NEXT: [[TMP3:%.*]] = call i8 @__hwasan_generate_tag() ; CHECK-NEXT: [[X_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[X]] to i64 ; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP4]], -9079256848778919937
; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP5]], -9079256848778919937 ; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[X_NOTAG]], 4
; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[X_NOTAG]], 4 ; CHECK-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP5]] to ptr
; CHECK-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP6]] to ptr ; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[X_TAG]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = shl i64 [[TMP4]], 57 ; CHECK-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 57
; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[X_NOTAG]], [[TMP7]]
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP8]] to ptr ; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP8]] to ptr
; CHECK-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP4]] to i8 ; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[X_TAG]], i64 16)
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[TMP9]], i64 16)
; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]) ; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]])
; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[HWASAN_UAR_TAG]], i64 16)
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[TMP10]], i64 16)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%x = alloca i32, align 4 %x = alloca i32, align 4
call void @use32(ptr nonnull %x) call void @use32(ptr nonnull %x)
ret void ret void
} }

llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca.ll

Show All 12 Lines
; CHECK-LABEL: define void @test_alloca ; CHECK-LABEL: define void @test_alloca
; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk { ; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; CHECK-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = and i64 [[TMP3]], 63 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; CHECK-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP1]], 57 ; CHECK-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = and i8 [[TMP4]], 63
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP4]], 63 ; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP1]], 57
; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i8
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP6]], 63
; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0 ; CHECK-NEXT: [[X_TAG:%.*]] = xor i8 [[HWASAN_STACK_BASE_TAG]], 0
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[X]] to i64 ; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP6]], -9079256848778919937 ; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP7]], -9079256848778919937
; CHECK-NEXT: [[TMP7:%.*]] = lshr i64 [[X_NOTAG]], 4 ; CHECK-NEXT: [[TMP8:%.*]] = lshr i64 [[X_NOTAG]], 4
; CHECK-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP7]] to ptr ; CHECK-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP8]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP5]], 57 ; CHECK-NEXT: [[TMP9:%.*]] = zext i8 [[X_TAG]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = shl i64 [[TMP9]], 57
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP9]] to ptr ; CHECK-NEXT: [[TMP11:%.*]] = or i64 [[X_NOTAG]], [[TMP10]]
; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP5]] to i8 ; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP11]] to ptr
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[TMP10]], i64 16) ; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[X_TAG]], i64 16)
; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]) ; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]])
; CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[HWASAN_UAR_TAG]], i64 16)
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[TMP11]], i64 16)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; INLINE-LABEL: define void @test_alloca ; INLINE-LABEL: define void @test_alloca
; INLINE-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk { ; INLINE-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk {
; INLINE-NEXT: entry: ; INLINE-NEXT: entry:
; INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8 ; INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
; INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], -9079256848778919937 ; INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], -9079256848778919937
; INLINE-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP0]], 3 ; INLINE-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP0]], 3
; INLINE-NEXT: [[TMP3:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; INLINE-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i8
; INLINE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP3]] to i64 ; INLINE-NEXT: [[TMP4:%.*]] = and i8 [[TMP3]], 63
; INLINE-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 44 ; INLINE-NEXT: [[TMP5:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; INLINE-NEXT: [[TMP6:%.*]] = or i64 ptrtoint (ptr @test_alloca to i64), [[TMP5]] ; INLINE-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; INLINE-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP1]] to ptr ; INLINE-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 44
; INLINE-NEXT: store i64 [[TMP6]], ptr [[TMP7]], align 8 ; INLINE-NEXT: [[TMP8:%.*]] = or i64 ptrtoint (ptr @test_alloca to i64), [[TMP7]]
; INLINE-NEXT: [[TMP8:%.*]] = ashr i64 [[TMP0]], 56 ; INLINE-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP1]] to ptr
; INLINE-NEXT: [[TMP9:%.*]] = shl nuw nsw i64 [[TMP8]], 12 ; INLINE-NEXT: store i64 [[TMP8]], ptr [[TMP9]], align 8
; INLINE-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], -1 ; INLINE-NEXT: [[TMP10:%.*]] = ashr i64 [[TMP0]], 56
; INLINE-NEXT: [[TMP11:%.*]] = add i64 [[TMP0]], 8 ; INLINE-NEXT: [[TMP11:%.*]] = shl nuw nsw i64 [[TMP10]], 12
; INLINE-NEXT: [[TMP12:%.*]] = and i64 [[TMP11]], [[TMP10]] ; INLINE-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], -1
; INLINE-NEXT: store i64 [[TMP12]], ptr @__hwasan_tls, align 8 ; INLINE-NEXT: [[TMP13:%.*]] = add i64 [[TMP0]], 8
; INLINE-NEXT: [[TMP13:%.*]] = or i64 [[TMP1]], 4294967295 ; INLINE-NEXT: [[TMP14:%.*]] = and i64 [[TMP13]], [[TMP12]]
; INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP13]], 1 ; INLINE-NEXT: store i64 [[TMP14]], ptr @__hwasan_tls, align 8
; INLINE-NEXT: [[TMP14:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; INLINE-NEXT: [[TMP15:%.*]] = or i64 [[TMP1]], 4294967295
; INLINE-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP4]], 57 ; INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP15]], 1
; INLINE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP15]], 63 ; INLINE-NEXT: [[TMP16:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; INLINE-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP6]], 57
; INLINE-NEXT: [[TMP18:%.*]] = trunc i64 [[TMP17]] to i8
; INLINE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP18]], 63
; INLINE-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; INLINE-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; INLINE-NEXT: [[TMP16:%.*]] = xor i64 [[TMP2]], 0 ; INLINE-NEXT: [[X_TAG:%.*]] = xor i8 [[TMP4]], 0
; INLINE-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[X]] to i64 ; INLINE-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[X]] to i64
; INLINE-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP17]], -9079256848778919937 ; INLINE-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP19]], -9079256848778919937
; INLINE-NEXT: [[TMP18:%.*]] = lshr i64 [[X_NOTAG]], 4 ; INLINE-NEXT: [[TMP20:%.*]] = lshr i64 [[X_NOTAG]], 4
; INLINE-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP18]] ; INLINE-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP20]]
; INLINE-NEXT: [[TMP19:%.*]] = shl i64 [[TMP16]], 57 ; INLINE-NEXT: [[TMP21:%.*]] = zext i8 [[X_TAG]] to i64
; INLINE-NEXT: [[TMP20:%.*]] = or i64 [[TMP17]], [[TMP19]] ; INLINE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP21]], 57
; INLINE-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP20]] to ptr ; INLINE-NEXT: [[TMP23:%.*]] = or i64 [[X_NOTAG]], [[TMP22]]
; INLINE-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP16]] to i8 ; INLINE-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr
; INLINE-NEXT: [[TMP22:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0 ; INLINE-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0
; INLINE-NEXT: store i8 4, ptr [[TMP22]], align 1 ; INLINE-NEXT: store i8 4, ptr [[TMP24]], align 1
; INLINE-NEXT: [[TMP23:%.*]] = getelementptr i8, ptr [[X]], i32 15 ; INLINE-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[X]], i32 15
; INLINE-NEXT: store i8 [[TMP21]], ptr [[TMP23]], align 1 ; INLINE-NEXT: store i8 [[X_TAG]], ptr [[TMP25]], align 1
; INLINE-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]) ; INLINE-NEXT: call void @use32(ptr nonnull [[X_HWASAN]])
; INLINE-NEXT: [[TMP24:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; INLINE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; INLINE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP24]], i64 1, i1 false)
; INLINE-NEXT: ret void ; INLINE-NEXT: ret void
; ;
entry: entry:
%x = alloca i32, align 4 %x = alloca i32, align 4
call void @use32(ptr nonnull %x) call void @use32(ptr nonnull %x)
ret void ret void
} }
define i32 @test_simple(ptr %a) sanitize_hwaddress { define i32 @test_simple(ptr %a) sanitize_hwaddress {
; CHECK-LABEL: define i32 @test_simple ; CHECK-LABEL: define i32 @test_simple
; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0]] personality ptr @__hwasan_personality_thunk { ; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0]] personality ptr @__hwasan_personality_thunk {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; CHECK-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = and i64 [[TMP3]], 63 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; CHECK-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP1]], 57 ; CHECK-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = and i8 [[TMP4]], 63
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP4]], 63 ; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP1]], 57
; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i8
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP6]], 63
; CHECK-NEXT: [[BUF_SROA_0:%.*]] = alloca { i8, [15 x i8] }, align 16 ; CHECK-NEXT: [[BUF_SROA_0:%.*]] = alloca { i8, [15 x i8] }, align 16
; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0 ; CHECK-NEXT: [[BUF_SROA_0_TAG:%.*]] = xor i8 [[HWASAN_STACK_BASE_TAG]], 0
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[BUF_SROA_0]] to i64 ; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[BUF_SROA_0]] to i64
; CHECK-NEXT: [[BUF_SROA_0_NOTAG:%.*]] = and i64 [[TMP6]], -9079256848778919937 ; CHECK-NEXT: [[BUF_SROA_0_NOTAG:%.*]] = and i64 [[TMP7]], -9079256848778919937
; CHECK-NEXT: [[TMP7:%.*]] = lshr i64 [[BUF_SROA_0_NOTAG]], 4 ; CHECK-NEXT: [[TMP8:%.*]] = lshr i64 [[BUF_SROA_0_NOTAG]], 4
; CHECK-NEXT: [[BUF_SROA_0_SHADOW:%.*]] = inttoptr i64 [[TMP7]] to ptr ; CHECK-NEXT: [[BUF_SROA_0_SHADOW:%.*]] = inttoptr i64 [[TMP8]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP5]], 57 ; CHECK-NEXT: [[TMP9:%.*]] = zext i8 [[BUF_SROA_0_TAG]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = shl i64 [[TMP9]], 57
; CHECK-NEXT: [[BUF_SROA_0_HWASAN:%.*]] = inttoptr i64 [[TMP9]] to ptr ; CHECK-NEXT: [[TMP11:%.*]] = or i64 [[BUF_SROA_0_NOTAG]], [[TMP10]]
; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP5]] to i8 ; CHECK-NEXT: [[BUF_SROA_0_HWASAN:%.*]] = inttoptr i64 [[TMP11]] to ptr
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[BUF_SROA_0]], i8 [[TMP10]], i64 16) ; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[BUF_SROA_0]], i8 [[BUF_SROA_0_TAG]], i64 16)
; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[BUF_SROA_0_HWASAN]] to i64 ; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[BUF_SROA_0_HWASAN]] to i64
; CHECK-NEXT: call void @__hwasan_store1(i64 [[TMP11]]) ; CHECK-NEXT: call void @__hwasan_store1(i64 [[TMP12]])
; CHECK-NEXT: store volatile i8 0, ptr [[BUF_SROA_0_HWASAN]], align 4 ; CHECK-NEXT: store volatile i8 0, ptr [[BUF_SROA_0_HWASAN]], align 4
; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[BUF_SROA_0]], i8 [[HWASAN_UAR_TAG]], i64 16)
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[BUF_SROA_0]], i8 [[TMP12]], i64 16)
; CHECK-NEXT: ret i32 0 ; CHECK-NEXT: ret i32 0
; ;
; INLINE-LABEL: define i32 @test_simple ; INLINE-LABEL: define i32 @test_simple
; INLINE-SAME: (ptr [[A:%.*]]) #[[ATTR0]] personality ptr @__hwasan_personality_thunk { ; INLINE-SAME: (ptr [[A:%.*]]) #[[ATTR0]] personality ptr @__hwasan_personality_thunk {
; INLINE-NEXT: entry: ; INLINE-NEXT: entry:
; INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8 ; INLINE-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
; INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], -9079256848778919937 ; INLINE-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], -9079256848778919937
; INLINE-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP0]], 3 ; INLINE-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP0]], 3
; INLINE-NEXT: [[TMP3:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; INLINE-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i8
; INLINE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP3]] to i64 ; INLINE-NEXT: [[TMP4:%.*]] = and i8 [[TMP3]], 63
; INLINE-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 44 ; INLINE-NEXT: [[TMP5:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; INLINE-NEXT: [[TMP6:%.*]] = or i64 ptrtoint (ptr @test_simple to i64), [[TMP5]] ; INLINE-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; INLINE-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP1]] to ptr ; INLINE-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 44
; INLINE-NEXT: store i64 [[TMP6]], ptr [[TMP7]], align 8 ; INLINE-NEXT: [[TMP8:%.*]] = or i64 ptrtoint (ptr @test_simple to i64), [[TMP7]]
; INLINE-NEXT: [[TMP8:%.*]] = ashr i64 [[TMP0]], 56 ; INLINE-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP1]] to ptr
; INLINE-NEXT: [[TMP9:%.*]] = shl nuw nsw i64 [[TMP8]], 12 ; INLINE-NEXT: store i64 [[TMP8]], ptr [[TMP9]], align 8
; INLINE-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], -1 ; INLINE-NEXT: [[TMP10:%.*]] = ashr i64 [[TMP0]], 56
; INLINE-NEXT: [[TMP11:%.*]] = add i64 [[TMP0]], 8 ; INLINE-NEXT: [[TMP11:%.*]] = shl nuw nsw i64 [[TMP10]], 12
; INLINE-NEXT: [[TMP12:%.*]] = and i64 [[TMP11]], [[TMP10]] ; INLINE-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], -1
; INLINE-NEXT: store i64 [[TMP12]], ptr @__hwasan_tls, align 8 ; INLINE-NEXT: [[TMP13:%.*]] = add i64 [[TMP0]], 8
; INLINE-NEXT: [[TMP13:%.*]] = or i64 [[TMP1]], 4294967295 ; INLINE-NEXT: [[TMP14:%.*]] = and i64 [[TMP13]], [[TMP12]]
; INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP13]], 1 ; INLINE-NEXT: store i64 [[TMP14]], ptr @__hwasan_tls, align 8
; INLINE-NEXT: [[TMP14:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; INLINE-NEXT: [[TMP15:%.*]] = or i64 [[TMP1]], 4294967295
; INLINE-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP4]], 57 ; INLINE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP15]], 1
; INLINE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP15]], 63 ; INLINE-NEXT: [[TMP16:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; INLINE-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP6]], 57
; INLINE-NEXT: [[TMP18:%.*]] = trunc i64 [[TMP17]] to i8
; INLINE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP18]], 63
; INLINE-NEXT: [[BUF_SROA_0:%.*]] = alloca { i8, [15 x i8] }, align 16 ; INLINE-NEXT: [[BUF_SROA_0:%.*]] = alloca { i8, [15 x i8] }, align 16
; INLINE-NEXT: [[TMP16:%.*]] = xor i64 [[TMP2]], 0 ; INLINE-NEXT: [[BUF_SROA_0_TAG:%.*]] = xor i8 [[TMP4]], 0
; INLINE-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[BUF_SROA_0]] to i64 ; INLINE-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[BUF_SROA_0]] to i64
; INLINE-NEXT: [[BUF_SROA_0_NOTAG:%.*]] = and i64 [[TMP17]], -9079256848778919937 ; INLINE-NEXT: [[BUF_SROA_0_NOTAG:%.*]] = and i64 [[TMP19]], -9079256848778919937
; INLINE-NEXT: [[TMP18:%.*]] = lshr i64 [[BUF_SROA_0_NOTAG]], 4 ; INLINE-NEXT: [[TMP20:%.*]] = lshr i64 [[BUF_SROA_0_NOTAG]], 4
; INLINE-NEXT: [[BUF_SROA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP18]] ; INLINE-NEXT: [[BUF_SROA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP20]]
; INLINE-NEXT: [[TMP19:%.*]] = shl i64 [[TMP16]], 57 ; INLINE-NEXT: [[TMP21:%.*]] = zext i8 [[BUF_SROA_0_TAG]] to i64
; INLINE-NEXT: [[TMP20:%.*]] = or i64 [[TMP17]], [[TMP19]] ; INLINE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP21]], 57
; INLINE-NEXT: [[BUF_SROA_0_HWASAN:%.*]] = inttoptr i64 [[TMP20]] to ptr ; INLINE-NEXT: [[TMP23:%.*]] = or i64 [[BUF_SROA_0_NOTAG]], [[TMP22]]
; INLINE-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP16]] to i8 ; INLINE-NEXT: [[BUF_SROA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr
; INLINE-NEXT: [[TMP22:%.*]] = getelementptr i8, ptr [[BUF_SROA_0_SHADOW]], i32 0 ; INLINE-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[BUF_SROA_0_SHADOW]], i32 0
; INLINE-NEXT: store i8 1, ptr [[TMP22]], align 1 ; INLINE-NEXT: store i8 1, ptr [[TMP24]], align 1
; INLINE-NEXT: [[TMP23:%.*]] = getelementptr i8, ptr [[BUF_SROA_0]], i32 15 ; INLINE-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[BUF_SROA_0]], i32 15
; INLINE-NEXT: store i8 [[TMP21]], ptr [[TMP23]], align 1 ; INLINE-NEXT: store i8 [[BUF_SROA_0_TAG]], ptr [[TMP25]], align 1
; INLINE-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[BUF_SROA_0_HWASAN]] to i64 ; INLINE-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[BUF_SROA_0_HWASAN]] to i64
; INLINE-NEXT: [[TMP25:%.*]] = lshr i64 [[TMP24]], 57 ; INLINE-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP26]], 57
; INLINE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP25]] to i8 ; INLINE-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8
; INLINE-NEXT: [[TMP27:%.*]] = and i64 [[TMP24]], -9079256848778919937 ; INLINE-NEXT: [[TMP29:%.*]] = and i64 [[TMP26]], -9079256848778919937
; INLINE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 ; INLINE-NEXT: [[TMP30:%.*]] = lshr i64 [[TMP29]], 4
; INLINE-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP28]] ; INLINE-NEXT: [[TMP31:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP30]]
; INLINE-NEXT: [[TMP30:%.*]] = load i8, ptr [[TMP29]], align 1 ; INLINE-NEXT: [[TMP32:%.*]] = load i8, ptr [[TMP31]], align 1
; INLINE-NEXT: [[TMP31:%.*]] = icmp ne i8 [[TMP26]], [[TMP30]] ; INLINE-NEXT: [[TMP33:%.*]] = icmp ne i8 [[TMP28]], [[TMP32]]
; INLINE-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP46:%.*]], !prof [[PROF1:![0-9]+]] ; INLINE-NEXT: br i1 [[TMP33]], label [[TMP34:%.*]], label [[TMP48:%.*]], !prof [[PROF1:![0-9]+]]
; INLINE: 32:
; INLINE-NEXT: [[TMP33:%.*]] = icmp ugt i8 [[TMP30]], 15
; INLINE-NEXT: br i1 [[TMP33]], label [[TMP34:%.*]], label [[TMP35:%.*]], !prof [[PROF1]]
; INLINE: 34: ; INLINE: 34:
; INLINE-NEXT: call void asm sideeffect "int3\0Anopl 80([[RAX:%.*]])", "{rdi}"(i64 [[TMP24]]) ; INLINE-NEXT: [[TMP35:%.*]] = icmp ugt i8 [[TMP32]], 15
; INLINE-NEXT: br i1 [[TMP35]], label [[TMP36:%.*]], label [[TMP37:%.*]], !prof [[PROF1]]
; INLINE: 36:
; INLINE-NEXT: call void asm sideeffect "int3\0Anopl 80([[RAX:%.*]])", "{rdi}"(i64 [[TMP26]])
; INLINE-NEXT: unreachable ; INLINE-NEXT: unreachable
; INLINE: 35: ; INLINE: 37:
; INLINE-NEXT: [[TMP36:%.*]] = and i64 [[TMP24]], 15 ; INLINE-NEXT: [[TMP38:%.*]] = and i64 [[TMP26]], 15
; INLINE-NEXT: [[TMP37:%.*]] = trunc i64 [[TMP36]] to i8 ; INLINE-NEXT: [[TMP39:%.*]] = trunc i64 [[TMP38]] to i8
; INLINE-NEXT: [[TMP38:%.*]] = add i8 [[TMP37]], 0 ; INLINE-NEXT: [[TMP40:%.*]] = add i8 [[TMP39]], 0
; INLINE-NEXT: [[TMP39:%.*]] = icmp uge i8 [[TMP38]], [[TMP30]] ; INLINE-NEXT: [[TMP41:%.*]] = icmp uge i8 [[TMP40]], [[TMP32]]
; INLINE-NEXT: br i1 [[TMP39]], label [[TMP34]], label [[TMP40:%.*]], !prof [[PROF1]] ; INLINE-NEXT: br i1 [[TMP41]], label [[TMP36]], label [[TMP42:%.*]], !prof [[PROF1]]
; INLINE: 40: ; INLINE: 42:
; INLINE-NEXT: [[TMP41:%.*]] = or i64 [[TMP27]], 15 ; INLINE-NEXT: [[TMP43:%.*]] = or i64 [[TMP29]], 15
; INLINE-NEXT: [[TMP42:%.*]] = inttoptr i64 [[TMP41]] to ptr ; INLINE-NEXT: [[TMP44:%.*]] = inttoptr i64 [[TMP43]] to ptr
; INLINE-NEXT: [[TMP43:%.*]] = load i8, ptr [[TMP42]], align 1 ; INLINE-NEXT: [[TMP45:%.*]] = load i8, ptr [[TMP44]], align 1
; INLINE-NEXT: [[TMP44:%.*]] = icmp ne i8 [[TMP26]], [[TMP43]] ; INLINE-NEXT: [[TMP46:%.*]] = icmp ne i8 [[TMP28]], [[TMP45]]
; INLINE-NEXT: br i1 [[TMP44]], label [[TMP34]], label [[TMP45:%.*]], !prof [[PROF1]] ; INLINE-NEXT: br i1 [[TMP46]], label [[TMP36]], label [[TMP47:%.*]], !prof [[PROF1]]
; INLINE: 45: ; INLINE: 47:
; INLINE-NEXT: br label [[TMP46]] ; INLINE-NEXT: br label [[TMP48]]
; INLINE: 46: ; INLINE: 48:
; INLINE-NEXT: store volatile i8 0, ptr [[BUF_SROA_0_HWASAN]], align 4 ; INLINE-NEXT: store volatile i8 0, ptr [[BUF_SROA_0_HWASAN]], align 4
; INLINE-NEXT: [[TMP47:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; INLINE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[BUF_SROA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; INLINE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[BUF_SROA_0_SHADOW]], i8 [[TMP47]], i64 1, i1 false)
; INLINE-NEXT: ret i32 0 ; INLINE-NEXT: ret i32 0
; ;
entry: entry:
%buf.sroa.0 = alloca i8, align 4 %buf.sroa.0 = alloca i8, align 4
call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %buf.sroa.0) call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %buf.sroa.0)
store volatile i8 0, ptr %buf.sroa.0, align 4 store volatile i8 0, ptr %buf.sroa.0, align 4
call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %buf.sroa.0) call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %buf.sroa.0)
ret i32 0 ret i32 0
} }
; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn ; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn ; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)

llvm/test/Instrumentation/HWAddressSanitizer/alloca-array.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt < %s -passes=hwasan -S | FileCheck %s ; RUN: opt < %s -passes=hwasan -S | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--linux-android" target triple = "aarch64--linux-android"
declare void @use(ptr, ptr) declare void @use(ptr, ptr)
define void @test_alloca() sanitize_hwaddress { define void @test_alloca() sanitize_hwaddress {
; CHECK-LABEL: define void @test_alloca ; CHECK-LABEL: define void @test_alloca
; CHECK-SAME: () #[[ATTR0:[0-9]+]] { ; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) ; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; CHECK-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; CHECK-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; CHECK-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; CHECK-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 8 ; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; CHECK-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 8
; CHECK-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; CHECK-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; CHECK-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; CHECK-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 8 ; CHECK-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; CHECK-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; CHECK-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 8
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; CHECK-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; CHECK-NEXT: [[X:%.*]] = alloca { [4 x i8], [12 x i8] }, align 16 ; CHECK-NEXT: [[X:%.*]] = alloca { [4 x i8], [12 x i8] }, align 16
; CHECK-NEXT: [[TMP18:%.*]] = xor i64 [[TMP4]], 0 ; CHECK-NEXT: [[X_TAG:%.*]] = xor i8 [[TMP5]], 0
; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[X]] to i64 ; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP19]], 72057594037927935 ; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP20]], 72057594037927935
; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[X_NOTAG]], 4 ; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[X_NOTAG]], 4
; CHECK-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP20]] ; CHECK-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP21]]
; CHECK-NEXT: [[TMP21:%.*]] = shl i64 [[TMP18]], 56 ; CHECK-NEXT: [[TMP22:%.*]] = zext i8 [[X_TAG]] to i64
; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP19]], [[TMP21]] ; CHECK-NEXT: [[TMP23:%.*]] = shl i64 [[TMP22]], 56
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP22]] to ptr ; CHECK-NEXT: [[TMP24:%.*]] = or i64 [[X_NOTAG]], [[TMP23]]
; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[TMP18]] to i8 ; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP23]], i64 1, i1 false) ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[X_TAG]], i64 1, i1 false)
; CHECK-NEXT: [[Y:%.*]] = alloca i8, i64 16, align 16 ; CHECK-NEXT: [[Y:%.*]] = alloca i8, i64 16, align 16
; CHECK-NEXT: [[TMP24:%.*]] = xor i64 [[TMP4]], 128 ; CHECK-NEXT: [[Y_TAG:%.*]] = xor i8 [[TMP5]], -128
; CHECK-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[Y]] to i64 ; CHECK-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[Y]] to i64
; CHECK-NEXT: [[Y_NOTAG:%.*]] = and i64 [[TMP25]], 72057594037927935 ; CHECK-NEXT: [[Y_NOTAG:%.*]] = and i64 [[TMP25]], 72057594037927935
; CHECK-NEXT: [[TMP26:%.*]] = lshr i64 [[Y_NOTAG]], 4 ; CHECK-NEXT: [[TMP26:%.*]] = lshr i64 [[Y_NOTAG]], 4
; CHECK-NEXT: [[Y_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] ; CHECK-NEXT: [[Y_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP26]]
; CHECK-NEXT: [[TMP27:%.*]] = shl i64 [[TMP24]], 56 ; CHECK-NEXT: [[TMP27:%.*]] = zext i8 [[Y_TAG]] to i64
; CHECK-NEXT: [[TMP28:%.*]] = or i64 [[TMP25]], [[TMP27]] ; CHECK-NEXT: [[TMP28:%.*]] = shl i64 [[TMP27]], 56
; CHECK-NEXT: [[Y_HWASAN:%.*]] = inttoptr i64 [[TMP28]] to ptr ; CHECK-NEXT: [[TMP29:%.*]] = or i64 [[Y_NOTAG]], [[TMP28]]
; CHECK-NEXT: [[TMP29:%.*]] = trunc i64 [[TMP24]] to i8 ; CHECK-NEXT: [[Y_HWASAN:%.*]] = inttoptr i64 [[TMP29]] to ptr
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[Y_SHADOW]], i8 [[TMP29]], i64 1, i1 false) ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[Y_SHADOW]], i8 [[Y_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @use(ptr [[X_HWASAN]], ptr [[Y_HWASAN]]) ; CHECK-NEXT: call void @use(ptr [[X_HWASAN]], ptr [[Y_HWASAN]])
; CHECK-NEXT: [[TMP30:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP30]], i64 1, i1 false) ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[Y_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; CHECK-NEXT: [[TMP31:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[Y_SHADOW]], i8 [[TMP31]], i64 1, i1 false)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%x = alloca i8, i64 4 %x = alloca i8, i64 4
%y = alloca i8, i64 16 %y = alloca i8, i64 16
call void @use(ptr %x, ptr %y) call void @use(ptr %x, ptr %y)
ret void ret void
} }

llvm/test/Instrumentation/HWAddressSanitizer/alloca-compat.ll

Show All 9 Lines
define void @test_alloca() sanitize_hwaddress { define void @test_alloca() sanitize_hwaddress {
; CHECK-LABEL: define void @test_alloca ; CHECK-LABEL: define void @test_alloca
; CHECK-SAME: () #[[ATTR0:[0-9]+]] { ; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) ; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; CHECK-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; CHECK-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; CHECK-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; CHECK-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 8 ; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; CHECK-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 8
; CHECK-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; CHECK-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; CHECK-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; CHECK-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 8 ; CHECK-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; CHECK-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; CHECK-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 8
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; CHECK-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; CHECK-NEXT: [[TMP18:%.*]] = xor i64 [[TMP4]], 0 ; CHECK-NEXT: [[X_TAG:%.*]] = xor i8 [[TMP5]], 0
; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[X]] to i64 ; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP19]], 72057594037927935 ; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP20]], 72057594037927935
; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[X_NOTAG]], 4 ; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[X_NOTAG]], 4
; CHECK-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP20]] ; CHECK-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP21]]
; CHECK-NEXT: [[TMP21:%.*]] = shl i64 [[TMP18]], 56 ; CHECK-NEXT: [[TMP22:%.*]] = zext i8 [[X_TAG]] to i64
; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP19]], [[TMP21]] ; CHECK-NEXT: [[TMP23:%.*]] = shl i64 [[TMP22]], 56
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP22]] to ptr ; CHECK-NEXT: [[TMP24:%.*]] = or i64 [[X_NOTAG]], [[TMP23]]
; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[TMP18]] to i8 ; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP23]], i64 1, i1 false) ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[X_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]) ; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]])
; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP24]], i64 1, i1 false)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%x = alloca i32, align 4 %x = alloca i32, align 4
call void @use32(ptr nonnull %x) call void @use32(ptr nonnull %x)
ret void ret void
} }

llvm/test/Instrumentation/HWAddressSanitizer/alloca-with-calls.ll

Show All 10 Lines
define void @test_alloca() sanitize_hwaddress { define void @test_alloca() sanitize_hwaddress {
; CHECK-LABEL: define void @test_alloca ; CHECK-LABEL: define void @test_alloca
; CHECK-SAME: () #[[ATTR0:[0-9]+]] { ; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.thread.pointer() ; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.thread.pointer()
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 48 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 48
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8
; CHECK-NEXT: [[TMP3:%.*]] = ashr i64 [[TMP2]], 3 ; CHECK-NEXT: [[TMP3:%.*]] = ashr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) ; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; CHECK-NEXT: [[TMP5:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 44 ; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP4]], [[TMP7]] ; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44
; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP2]] to ptr ; CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]]
; CHECK-NEXT: store i64 [[TMP8]], ptr [[TMP9]], align 8 ; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP2]] to ptr
; CHECK-NEXT: [[TMP10:%.*]] = ashr i64 [[TMP2]], 56 ; CHECK-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 8
; CHECK-NEXT: [[TMP11:%.*]] = shl nuw nsw i64 [[TMP10]], 12 ; CHECK-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP2]], 56
; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], -1 ; CHECK-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12
; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP2]], 8 ; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1
; CHECK-NEXT: [[TMP14:%.*]] = and i64 [[TMP13]], [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP2]], 8
; CHECK-NEXT: store i64 [[TMP14]], ptr [[TMP1]], align 8 ; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]]
; CHECK-NEXT: [[TMP15:%.*]] = or i64 [[TMP2]], 4294967295 ; CHECK-NEXT: store i64 [[TMP15]], ptr [[TMP1]], align 8
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP15]], 1 ; CHECK-NEXT: [[TMP16:%.*]] = or i64 [[TMP2]], 4294967295
; CHECK-NEXT: [[TMP16:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP6]], 56 ; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP7]], 56
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP18]] to i8
; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; CHECK-NEXT: [[TMP17:%.*]] = call i8 @__hwasan_generate_tag() ; CHECK-NEXT: [[X_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; CHECK-NEXT: [[TMP18:%.*]] = zext i8 [[TMP17]] to i64
; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[X]] to i64 ; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP19]], 72057594037927935 ; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP19]], 72057594037927935
; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[X_NOTAG]], 4 ; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[X_NOTAG]], 4
; CHECK-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP20]] ; CHECK-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP20]]
; CHECK-NEXT: [[TMP21:%.*]] = shl i64 [[TMP18]], 56 ; CHECK-NEXT: [[TMP21:%.*]] = zext i8 [[X_TAG]] to i64
; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP19]], [[TMP21]] ; CHECK-NEXT: [[TMP22:%.*]] = shl i64 [[TMP21]], 56
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP22]] to ptr ; CHECK-NEXT: [[TMP23:%.*]] = or i64 [[X_NOTAG]], [[TMP22]]
; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[TMP18]] to i8 ; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP23]], i64 1, i1 false) ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[X_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]) ; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]])
; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP24]], i64 1, i1 false)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%x = alloca i32, align 4 %x = alloca i32, align 4
call void @use32(ptr nonnull %x) call void @use32(ptr nonnull %x)
ret void ret void
} }

llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll

Show All 11 Lines
define void @test_alloca() sanitize_hwaddress !dbg !15 { define void @test_alloca() sanitize_hwaddress !dbg !15 {
; DYNAMIC-SHADOW-LABEL: define void @test_alloca ; DYNAMIC-SHADOW-LABEL: define void @test_alloca
; DYNAMIC-SHADOW-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk !dbg [[DBG7:![0-9]+]] { ; DYNAMIC-SHADOW-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk !dbg [[DBG7:![0-9]+]] {
; DYNAMIC-SHADOW-NEXT: entry: ; DYNAMIC-SHADOW-NEXT: entry:
; DYNAMIC-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow) ; DYNAMIC-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow)
; DYNAMIC-SHADOW-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; DYNAMIC-SHADOW-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; DYNAMIC-SHADOW-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64 ; DYNAMIC-SHADOW-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; DYNAMIC-SHADOW-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20 ; DYNAMIC-SHADOW-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; DYNAMIC-SHADOW-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP1]], [[TMP2]] ; DYNAMIC-SHADOW-NEXT: [[TMP3:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; DYNAMIC-SHADOW-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP1]], 56 ; DYNAMIC-SHADOW-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = trunc i64 [[TMP3]] to i8
; DYNAMIC-SHADOW-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP1]], 56
; DYNAMIC-SHADOW-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP4]] to i8
; DYNAMIC-SHADOW-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; DYNAMIC-SHADOW-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; DYNAMIC-SHADOW-NEXT: [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG10:![0-9]+]] ; DYNAMIC-SHADOW-NEXT: [[X_TAG:%.*]] = xor i8 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG10:![0-9]+]]
; DYNAMIC-SHADOW-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP4]], 72057594037927935, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP5]], 72057594037927935, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP5:%.*]] = lshr i64 [[X_NOTAG]], 4, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[TMP6:%.*]] = lshr i64 [[X_NOTAG]], 4, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP5]], !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP6]], !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP6:%.*]] = shl i64 [[TMP3]], 56, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[TMP7:%.*]] = zext i8 [[X_TAG]] to i64, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]], !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 56, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to ptr, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[TMP9:%.*]] = or i64 [[X_NOTAG]], [[TMP8]], !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP3]] to i8, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP9]] to ptr, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: store i8 4, ptr [[TMP9]], align 1, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: store i8 4, ptr [[TMP10]], align 1, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: store i8 [[TMP8]], ptr [[TMP10]], align 1, !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: store i8 [[X_TAG]], ptr [[TMP11]], align 1, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: call void @llvm.dbg.value(metadata !DIArgList(ptr [[X]], ptr [[X]]), metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref)), !dbg [[DBG10]] ; DYNAMIC-SHADOW-NEXT: call void @llvm.dbg.value(metadata !DIArgList(ptr [[X]], ptr [[X]]), metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref)), !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13:![0-9]+]] ; DYNAMIC-SHADOW-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13:![0-9]+]]
; DYNAMIC-SHADOW-NEXT: [[TMP11:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8, !dbg [[DBG14:![0-9]+]] ; DYNAMIC-SHADOW-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false), !dbg [[DBG14:![0-9]+]]
; DYNAMIC-SHADOW-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP11]], i64 1, i1 false), !dbg [[DBG14]]
; DYNAMIC-SHADOW-NEXT: ret void, !dbg [[DBG14]] ; DYNAMIC-SHADOW-NEXT: ret void, !dbg [[DBG14]]
; ;
; ZERO-BASED-SHADOW-LABEL: define void @test_alloca ; ZERO-BASED-SHADOW-LABEL: define void @test_alloca
; ZERO-BASED-SHADOW-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk !dbg [[DBG7:![0-9]+]] { ; ZERO-BASED-SHADOW-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk !dbg [[DBG7:![0-9]+]] {
; ZERO-BASED-SHADOW-NEXT: entry: ; ZERO-BASED-SHADOW-NEXT: entry:
; ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; ZERO-BASED-SHADOW-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; ZERO-BASED-SHADOW-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; ZERO-BASED-SHADOW-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64 ; ZERO-BASED-SHADOW-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; ZERO-BASED-SHADOW-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20 ; ZERO-BASED-SHADOW-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; ZERO-BASED-SHADOW-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP1]], [[TMP2]] ; ZERO-BASED-SHADOW-NEXT: [[TMP3:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; ZERO-BASED-SHADOW-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP1]], 56 ; ZERO-BASED-SHADOW-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = trunc i64 [[TMP3]] to i8
; ZERO-BASED-SHADOW-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP1]], 56
; ZERO-BASED-SHADOW-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP4]] to i8
; ZERO-BASED-SHADOW-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; ZERO-BASED-SHADOW-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; ZERO-BASED-SHADOW-NEXT: [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG10:![0-9]+]] ; ZERO-BASED-SHADOW-NEXT: [[X_TAG:%.*]] = xor i8 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG10:![0-9]+]]
; ZERO-BASED-SHADOW-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP4]], 72057594037927935, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP5]], 72057594037927935, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP5:%.*]] = lshr i64 [[X_NOTAG]], 4, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[TMP6:%.*]] = lshr i64 [[X_NOTAG]], 4, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP5]] to ptr, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP6:%.*]] = shl i64 [[TMP3]], 56, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[TMP7:%.*]] = zext i8 [[X_TAG]] to i64, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]], !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 56, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to ptr, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[TMP9:%.*]] = or i64 [[X_NOTAG]], [[TMP8]], !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP3]] to i8, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP9]] to ptr, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: store i8 4, ptr [[TMP9]], align 1, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: store i8 4, ptr [[TMP10]], align 1, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: store i8 [[TMP8]], ptr [[TMP10]], align 1, !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: store i8 [[X_TAG]], ptr [[TMP11]], align 1, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: call void @llvm.dbg.value(metadata !DIArgList(ptr [[X]], ptr [[X]]), metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref)), !dbg [[DBG10]] ; ZERO-BASED-SHADOW-NEXT: call void @llvm.dbg.value(metadata !DIArgList(ptr [[X]], ptr [[X]]), metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref)), !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13:![0-9]+]] ; ZERO-BASED-SHADOW-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13:![0-9]+]]
; ZERO-BASED-SHADOW-NEXT: [[TMP11:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8, !dbg [[DBG14:![0-9]+]] ; ZERO-BASED-SHADOW-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false), !dbg [[DBG14:![0-9]+]]
; ZERO-BASED-SHADOW-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP11]], i64 1, i1 false), !dbg [[DBG14]]
; ZERO-BASED-SHADOW-NEXT: ret void, !dbg [[DBG14]] ; ZERO-BASED-SHADOW-NEXT: ret void, !dbg [[DBG14]]
; ;
entry: entry:
%x = alloca i32, align 4 %x = alloca i32, align 4
call void @llvm.dbg.value(metadata !DIArgList(ptr %x, ptr %x), metadata !22, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_deref)), !dbg !21 call void @llvm.dbg.value(metadata !DIArgList(ptr %x, ptr %x), metadata !22, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_deref)), !dbg !21
call void @use32(ptr nonnull %x), !dbg !23 call void @use32(ptr nonnull %x), !dbg !23
ret void, !dbg !24 ret void, !dbg !24
} }
Show All 22 Lines

llvm/test/Instrumentation/HWAddressSanitizer/exception-lifetime.ll

Show All 16 Lines
define void @test() sanitize_hwaddress personality ptr @__gxx_personality_v0 { define void @test() sanitize_hwaddress personality ptr @__gxx_personality_v0 {
; CHECK-LABEL: define void @test ; CHECK-LABEL: define void @test
; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 { ; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.thread.pointer() ; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.thread.pointer()
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 48 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 48
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8
; CHECK-NEXT: [[TMP3:%.*]] = ashr i64 [[TMP2]], 3 ; CHECK-NEXT: [[TMP3:%.*]] = ashr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) ; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; CHECK-NEXT: [[TMP5:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 44 ; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP4]], [[TMP7]] ; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44
; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP2]] to ptr ; CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]]
; CHECK-NEXT: store i64 [[TMP8]], ptr [[TMP9]], align 8 ; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP2]] to ptr
; CHECK-NEXT: [[TMP10:%.*]] = ashr i64 [[TMP2]], 56 ; CHECK-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 8
; CHECK-NEXT: [[TMP11:%.*]] = shl nuw nsw i64 [[TMP10]], 12 ; CHECK-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP2]], 56
; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], -1 ; CHECK-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12
; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP2]], 8 ; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1
; CHECK-NEXT: [[TMP14:%.*]] = and i64 [[TMP13]], [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP2]], 8
; CHECK-NEXT: store i64 [[TMP14]], ptr [[TMP1]], align 8 ; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]]
; CHECK-NEXT: [[TMP15:%.*]] = or i64 [[TMP2]], 4294967295 ; CHECK-NEXT: store i64 [[TMP15]], ptr [[TMP1]], align 8
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP15]], 1 ; CHECK-NEXT: [[TMP16:%.*]] = or i64 [[TMP2]], 4294967295
; CHECK-NEXT: [[TMP16:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP6]], 56 ; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP7]], 56
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP18]] to i8
; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP3]], 0 ; CHECK-NEXT: [[X_TAG:%.*]] = xor i8 [[TMP4]], 0
; CHECK-NEXT: [[TMP18:%.*]] = ptrtoint ptr [[X]] to i64 ; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP18]], 72057594037927935 ; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP19]], 72057594037927935
; CHECK-NEXT: [[TMP19:%.*]] = lshr i64 [[X_NOTAG]], 4 ; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[X_NOTAG]], 4
; CHECK-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP19]] ; CHECK-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP20]]
; CHECK-NEXT: [[TMP20:%.*]] = shl i64 [[TMP17]], 56 ; CHECK-NEXT: [[TMP21:%.*]] = zext i8 [[X_TAG]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = or i64 [[TMP18]], [[TMP20]] ; CHECK-NEXT: [[TMP22:%.*]] = shl i64 [[TMP21]], 56
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP21]] to ptr ; CHECK-NEXT: [[TMP23:%.*]] = or i64 [[X_NOTAG]], [[TMP22]]
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr
; CHECK-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 ; CHECK-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8
; CHECK-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr [[X]]) ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr [[X]])
; CHECK-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP17]] to i8 ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[X_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP22]], i64 1, i1 false)
; CHECK-NEXT: invoke void @mayFail(ptr [[X_HWASAN]]) ; CHECK-NEXT: invoke void @mayFail(ptr [[X_HWASAN]])
; CHECK-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] ; CHECK-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
; CHECK: invoke.cont: ; CHECK: invoke.cont:
; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP23]], i64 1, i1 false)
; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[X]]) ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[X]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: lpad: ; CHECK: lpad:
; CHECK-NEXT: [[TMP24:%.*]] = landingpad { ptr, i32 } ; CHECK-NEXT: [[TMP24:%.*]] = landingpad { ptr, i32 }
; CHECK-NEXT: cleanup ; CHECK-NEXT: cleanup
; CHECK-NEXT: [[TMP25:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2:![0-9]+]]) ; CHECK-NEXT: [[TMP25:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2:![0-9]+]])
; CHECK-NEXT: call void @__hwasan_handle_vfork(i64 [[TMP25]]) ; CHECK-NEXT: call void @__hwasan_handle_vfork(i64 [[TMP25]])
; CHECK-NEXT: [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP24]], 0 ; CHECK-NEXT: [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP24]], 0
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[TMP16]], ptr [[EXN_SLOT]], i32 19) ; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[TMP17]], ptr [[EXN_SLOT]], i32 19)
; CHECK-NEXT: store ptr [[TMP26]], ptr [[EXN_SLOT]], align 8 ; CHECK-NEXT: store ptr [[TMP26]], ptr [[EXN_SLOT]], align 8
; CHECK-NEXT: [[TMP27:%.*]] = extractvalue { ptr, i32 } [[TMP24]], 1 ; CHECK-NEXT: [[TMP27:%.*]] = extractvalue { ptr, i32 } [[TMP24]], 1
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[TMP16]], ptr [[EHSELECTOR_SLOT]], i32 18) ; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[TMP17]], ptr [[EHSELECTOR_SLOT]], i32 18)
; CHECK-NEXT: store i32 [[TMP27]], ptr [[EHSELECTOR_SLOT]], align 4 ; CHECK-NEXT: store i32 [[TMP27]], ptr [[EHSELECTOR_SLOT]], align 4
; CHECK-NEXT: call void @onExcept(ptr [[X_HWASAN]]) ; CHECK-NEXT: call void @onExcept(ptr [[X_HWASAN]])
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP28]], i64 1, i1 false)
; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[X]]) ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[X]])
; CHECK-NEXT: br label [[EH_RESUME:%.*]] ; CHECK-NEXT: br label [[EH_RESUME:%.*]]
; CHECK: eh.resume: ; CHECK: eh.resume:
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[TMP16]], ptr [[EXN_SLOT]], i32 3) ; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[TMP17]], ptr [[EXN_SLOT]], i32 3)
; CHECK-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 ; CHECK-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[TMP16]], ptr [[EHSELECTOR_SLOT]], i32 2) ; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[TMP17]], ptr [[EHSELECTOR_SLOT]], i32 2)
; CHECK-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 ; CHECK-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
; CHECK-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } undef, ptr [[EXN]], 0 ; CHECK-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } undef, ptr [[EXN]], 0
; CHECK-NEXT: [[LPAD_VAL1:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 ; CHECK-NEXT: [[LPAD_VAL1:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
; CHECK-NEXT: resume { ptr, i32 } [[LPAD_VAL1]] ; CHECK-NEXT: resume { ptr, i32 } [[LPAD_VAL1]]
; ;
entry: entry:
%x = alloca i32, align 8 %x = alloca i32, align 8
%exn.slot = alloca ptr, align 8 %exn.slot = alloca ptr, align 8
Show All 28 Lines

llvm/test/Instrumentation/HWAddressSanitizer/kernel-alloca.ll

Show All 10 Lines
define void @test_alloca() sanitize_hwaddress { define void @test_alloca() sanitize_hwaddress {
; CHECK-LABEL: define void @test_alloca ; CHECK-LABEL: define void @test_alloca
; CHECK-SAME: () #[[ATTR0:[0-9]+]] { ; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; CHECK-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP1]], 56 ; CHECK-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = trunc i64 [[TMP3]] to i8
; CHECK-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP1]], 56
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP4]] to i8
; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0 ; CHECK-NEXT: [[X_TAG:%.*]] = xor i8 [[HWASAN_STACK_BASE_TAG]], 0
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64 ; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[X_NOTAG:%.*]] = or i64 [[TMP4]], -72057594037927936 ; CHECK-NEXT: [[X_NOTAG:%.*]] = or i64 [[TMP5]], -72057594037927936
; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[X_NOTAG]], 4 ; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[X_NOTAG]], 4
; CHECK-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP5]] to ptr ; CHECK-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP6]] to ptr
; CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP3]], 56 ; CHECK-NEXT: [[TMP7:%.*]] = zext i8 [[X_TAG]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = or i64 [[TMP6]], 72057594037927935 ; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 56
; CHECK-NEXT: [[TMP8:%.*]] = and i64 [[TMP4]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP8]], 72057594037927935
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP8]] to ptr ; CHECK-NEXT: [[TMP10:%.*]] = and i64 [[X_NOTAG]], [[TMP9]]
; CHECK-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP3]] to i8 ; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP9]], i64 1, i1 false) ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[X_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]) ; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]])
; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP10]], i64 1, i1 false)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%x = alloca i32, align 4 %x = alloca i32, align 4
call void @use32(ptr nonnull %x) call void @use32(ptr nonnull %x)
ret void ret void
} }

llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; When watching stack history, all code paths attempt to get PC and SP and mix them together. ; When watching stack history, all code paths attempt to get PC and SP and mix them together.
; CHECK-LABEL: define void @test_alloca ; CHECK-LABEL: define void @test_alloca
; CHECK-SAME: () #[[ATTR0]] { ; CHECK-SAME: () #[[ATTR0]] {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.thread.pointer() ; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.thread.pointer()
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 48 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 48
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8
; CHECK-NEXT: [[TMP3:%.*]] = ashr i64 [[TMP2]], 3 ; CHECK-NEXT: [[TMP3:%.*]] = ashr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) ; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; CHECK-NEXT: [[TMP5:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 44 ; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP4]], [[TMP7]] ; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44
; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP2]] to ptr ; CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]]
; CHECK-NEXT: store i64 [[TMP8]], ptr [[TMP9]], align 8 ; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP2]] to ptr
; CHECK-NEXT: [[TMP10:%.*]] = ashr i64 [[TMP2]], 56 ; CHECK-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 8
; CHECK-NEXT: [[TMP11:%.*]] = shl nuw nsw i64 [[TMP10]], 12 ; CHECK-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP2]], 56
; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], -1 ; CHECK-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12
; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP2]], 8 ; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1
; CHECK-NEXT: [[TMP14:%.*]] = and i64 [[TMP13]], [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP2]], 8
; CHECK-NEXT: store i64 [[TMP14]], ptr [[TMP1]], align 8 ; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]]
; CHECK-NEXT: [[TMP15:%.*]] = or i64 [[TMP2]], 4294967295 ; CHECK-NEXT: store i64 [[TMP15]], ptr [[TMP1]], align 8
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP15]], 1 ; CHECK-NEXT: [[TMP16:%.*]] = or i64 [[TMP2]], 4294967295
; CHECK-NEXT: [[TMP16:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP6]], 56 ; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP7]], 56
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP18]] to i8
; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP3]], 0 ; CHECK-NEXT: [[X_TAG:%.*]] = xor i8 [[TMP4]], 0
; CHECK-NEXT: [[TMP18:%.*]] = ptrtoint ptr [[X]] to i64 ; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP18]], 72057594037927935 ; CHECK-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP19]], 72057594037927935
; CHECK-NEXT: [[TMP19:%.*]] = lshr i64 [[X_NOTAG]], 4 ; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[X_NOTAG]], 4
; CHECK-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP19]] ; CHECK-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP20]]
; CHECK-NEXT: [[TMP20:%.*]] = shl i64 [[TMP17]], 56 ; CHECK-NEXT: [[TMP21:%.*]] = zext i8 [[X_TAG]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = or i64 [[TMP18]], [[TMP20]] ; CHECK-NEXT: [[TMP22:%.*]] = shl i64 [[TMP21]], 56
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP21]] to ptr ; CHECK-NEXT: [[TMP23:%.*]] = or i64 [[X_NOTAG]], [[TMP22]]
; CHECK-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP17]] to i8 ; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP22]], i64 1, i1 false) ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[X_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @use(ptr [[X_HWASAN]]) ; CHECK-NEXT: call void @use(ptr [[X_HWASAN]])
; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP23]], i64 1, i1 false)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; NOIFUNC-TLS-HISTORY-LABEL: define void @test_alloca ; NOIFUNC-TLS-HISTORY-LABEL: define void @test_alloca
; NOIFUNC-TLS-HISTORY-SAME: () #[[ATTR0]] { ; NOIFUNC-TLS-HISTORY-SAME: () #[[ATTR0]] {
; NOIFUNC-TLS-HISTORY-NEXT: entry: ; NOIFUNC-TLS-HISTORY-NEXT: entry:
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP0:%.*]] = call ptr @llvm.thread.pointer() ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP0:%.*]] = call ptr @llvm.thread.pointer()
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 48 ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 48
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8 ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP3:%.*]] = ashr i64 [[TMP2]], 3 ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP3:%.*]] = ashr i64 [[TMP2]], 3
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP4:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP5:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64 ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 44 ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP8:%.*]] = or i64 [[TMP4]], [[TMP7]] ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP2]] to ptr ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]]
; NOIFUNC-TLS-HISTORY-NEXT: store i64 [[TMP8]], ptr [[TMP9]], align 8 ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP2]] to ptr
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP10:%.*]] = ashr i64 [[TMP2]], 56 ; NOIFUNC-TLS-HISTORY-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 8
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP11:%.*]] = shl nuw nsw i64 [[TMP10]], 12 ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP2]], 56
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], -1 ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP13:%.*]] = add i64 [[TMP2]], 8 ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP14:%.*]] = and i64 [[TMP13]], [[TMP12]] ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP14:%.*]] = add i64 [[TMP2]], 8
; NOIFUNC-TLS-HISTORY-NEXT: store i64 [[TMP14]], ptr [[TMP1]], align 8 ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]]
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP15:%.*]] = or i64 [[TMP2]], 4294967295 ; NOIFUNC-TLS-HISTORY-NEXT: store i64 [[TMP15]], ptr [[TMP1]], align 8
; NOIFUNC-TLS-HISTORY-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP15]], 1 ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP16:%.*]] = or i64 [[TMP2]], 4294967295
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP16:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; NOIFUNC-TLS-HISTORY-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1
; NOIFUNC-TLS-HISTORY-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP6]], 56 ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP7]], 56
; NOIFUNC-TLS-HISTORY-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP18]] to i8
; NOIFUNC-TLS-HISTORY-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; NOIFUNC-TLS-HISTORY-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP17:%.*]] = xor i64 [[TMP3]], 0 ; NOIFUNC-TLS-HISTORY-NEXT: [[X_TAG:%.*]] = xor i8 [[TMP4]], 0
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP18:%.*]] = ptrtoint ptr [[X]] to i64 ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[X]] to i64
; NOIFUNC-TLS-HISTORY-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP18]], 72057594037927935 ; NOIFUNC-TLS-HISTORY-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP19]], 72057594037927935
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP19:%.*]] = lshr i64 [[X_NOTAG]], 4 ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP20:%.*]] = lshr i64 [[X_NOTAG]], 4
; NOIFUNC-TLS-HISTORY-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP19]] ; NOIFUNC-TLS-HISTORY-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP20]]
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP20:%.*]] = shl i64 [[TMP17]], 56 ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP21:%.*]] = zext i8 [[X_TAG]] to i64
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP21:%.*]] = or i64 [[TMP18]], [[TMP20]] ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP22:%.*]] = shl i64 [[TMP21]], 56
; NOIFUNC-TLS-HISTORY-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP21]] to ptr ; NOIFUNC-TLS-HISTORY-NEXT: [[TMP23:%.*]] = or i64 [[X_NOTAG]], [[TMP22]]
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP17]] to i8 ; NOIFUNC-TLS-HISTORY-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr
; NOIFUNC-TLS-HISTORY-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP22]], i64 1, i1 false) ; NOIFUNC-TLS-HISTORY-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[X_TAG]], i64 1, i1 false)
; NOIFUNC-TLS-HISTORY-NEXT: call void @use(ptr [[X_HWASAN]]) ; NOIFUNC-TLS-HISTORY-NEXT: call void @use(ptr [[X_HWASAN]])
; NOIFUNC-TLS-HISTORY-NEXT: [[TMP23:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; NOIFUNC-TLS-HISTORY-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; NOIFUNC-TLS-HISTORY-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP23]], i64 1, i1 false)
; NOIFUNC-TLS-HISTORY-NEXT: ret void ; NOIFUNC-TLS-HISTORY-NEXT: ret void
; ;
; NOIFUNC-TLS-NOHISTORY-LABEL: define void @test_alloca ; NOIFUNC-TLS-NOHISTORY-LABEL: define void @test_alloca
; NOIFUNC-TLS-NOHISTORY-SAME: () #[[ATTR0]] { ; NOIFUNC-TLS-NOHISTORY-SAME: () #[[ATTR0]] {
; NOIFUNC-TLS-NOHISTORY-NEXT: entry: ; NOIFUNC-TLS-NOHISTORY-NEXT: entry:
; NOIFUNC-TLS-NOHISTORY-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow) ; NOIFUNC-TLS-NOHISTORY-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow)
; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64 ; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20 ; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; NOIFUNC-TLS-NOHISTORY-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP1]], [[TMP2]] ; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP3:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; NOIFUNC-TLS-NOHISTORY-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP1]], 56 ; NOIFUNC-TLS-NOHISTORY-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = trunc i64 [[TMP3]] to i8
; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP1]], 56
; NOIFUNC-TLS-NOHISTORY-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP4]] to i8
; NOIFUNC-TLS-NOHISTORY-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; NOIFUNC-TLS-NOHISTORY-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0 ; NOIFUNC-TLS-NOHISTORY-NEXT: [[X_TAG:%.*]] = xor i8 [[HWASAN_STACK_BASE_TAG]], 0
; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64 ; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[X]] to i64
; NOIFUNC-TLS-NOHISTORY-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP4]], 72057594037927935 ; NOIFUNC-TLS-NOHISTORY-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP5]], 72057594037927935
; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP5:%.*]] = lshr i64 [[X_NOTAG]], 4 ; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP6:%.*]] = lshr i64 [[X_NOTAG]], 4
; NOIFUNC-TLS-NOHISTORY-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP5]] ; NOIFUNC-TLS-NOHISTORY-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP6]]
; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP6:%.*]] = shl i64 [[TMP3]], 56 ; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP7:%.*]] = zext i8 [[X_TAG]] to i64
; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]] ; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 56
; NOIFUNC-TLS-NOHISTORY-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to ptr ; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP9:%.*]] = or i64 [[X_NOTAG]], [[TMP8]]
; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP3]] to i8 ; NOIFUNC-TLS-NOHISTORY-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP9]] to ptr
; NOIFUNC-TLS-NOHISTORY-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP8]], i64 1, i1 false) ; NOIFUNC-TLS-NOHISTORY-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[X_TAG]], i64 1, i1 false)
; NOIFUNC-TLS-NOHISTORY-NEXT: call void @use(ptr [[X_HWASAN]]) ; NOIFUNC-TLS-NOHISTORY-NEXT: call void @use(ptr [[X_HWASAN]])
; NOIFUNC-TLS-NOHISTORY-NEXT: [[TMP9:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; NOIFUNC-TLS-NOHISTORY-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; NOIFUNC-TLS-NOHISTORY-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP9]], i64 1, i1 false)
; NOIFUNC-TLS-NOHISTORY-NEXT: ret void ; NOIFUNC-TLS-NOHISTORY-NEXT: ret void
; ;
; NOIFUNC-NOTLS-LABEL: define void @test_alloca ; NOIFUNC-NOTLS-LABEL: define void @test_alloca
; NOIFUNC-NOTLS-SAME: () #[[ATTR0]] { ; NOIFUNC-NOTLS-SAME: () #[[ATTR0]] {
; NOIFUNC-NOTLS-NEXT: entry: ; NOIFUNC-NOTLS-NEXT: entry:
; NOIFUNC-NOTLS-NEXT: [[TMP0:%.*]] = load ptr, ptr @__hwasan_shadow_memory_dynamic_address, align 8 ; NOIFUNC-NOTLS-NEXT: [[TMP0:%.*]] = load ptr, ptr @__hwasan_shadow_memory_dynamic_address, align 8
; NOIFUNC-NOTLS-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; NOIFUNC-NOTLS-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; NOIFUNC-NOTLS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 ; NOIFUNC-NOTLS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
; NOIFUNC-NOTLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 20 ; NOIFUNC-NOTLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 20
; NOIFUNC-NOTLS-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP2]], [[TMP3]] ; NOIFUNC-NOTLS-NEXT: [[TMP4:%.*]] = xor i64 [[TMP2]], [[TMP3]]
; NOIFUNC-NOTLS-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP2]], 56 ; NOIFUNC-NOTLS-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = trunc i64 [[TMP4]] to i8
; NOIFUNC-NOTLS-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP2]], 56
; NOIFUNC-NOTLS-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP5]] to i8
; NOIFUNC-NOTLS-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; NOIFUNC-NOTLS-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; NOIFUNC-NOTLS-NEXT: [[TMP4:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0 ; NOIFUNC-NOTLS-NEXT: [[X_TAG:%.*]] = xor i8 [[HWASAN_STACK_BASE_TAG]], 0
; NOIFUNC-NOTLS-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[X]] to i64 ; NOIFUNC-NOTLS-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[X]] to i64
; NOIFUNC-NOTLS-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP5]], 72057594037927935 ; NOIFUNC-NOTLS-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP6]], 72057594037927935
; NOIFUNC-NOTLS-NEXT: [[TMP6:%.*]] = lshr i64 [[X_NOTAG]], 4 ; NOIFUNC-NOTLS-NEXT: [[TMP7:%.*]] = lshr i64 [[X_NOTAG]], 4
; NOIFUNC-NOTLS-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP0]], i64 [[TMP6]] ; NOIFUNC-NOTLS-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[TMP0]], i64 [[TMP7]]
; NOIFUNC-NOTLS-NEXT: [[TMP7:%.*]] = shl i64 [[TMP4]], 56 ; NOIFUNC-NOTLS-NEXT: [[TMP8:%.*]] = zext i8 [[X_TAG]] to i64
; NOIFUNC-NOTLS-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]] ; NOIFUNC-NOTLS-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 56
; NOIFUNC-NOTLS-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP8]] to ptr ; NOIFUNC-NOTLS-NEXT: [[TMP10:%.*]] = or i64 [[X_NOTAG]], [[TMP9]]
; NOIFUNC-NOTLS-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP4]] to i8 ; NOIFUNC-NOTLS-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr
; NOIFUNC-NOTLS-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP9]], i64 1, i1 false) ; NOIFUNC-NOTLS-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[X_TAG]], i64 1, i1 false)
; NOIFUNC-NOTLS-NEXT: call void @use(ptr [[X_HWASAN]]) ; NOIFUNC-NOTLS-NEXT: call void @use(ptr [[X_HWASAN]])
; NOIFUNC-NOTLS-NEXT: [[TMP10:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; NOIFUNC-NOTLS-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; NOIFUNC-NOTLS-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP10]], i64 1, i1 false)
; NOIFUNC-NOTLS-NEXT: ret void ; NOIFUNC-NOTLS-NEXT: ret void
; ;
; IFUNC-NOTLS-LABEL: define void @test_alloca ; IFUNC-NOTLS-LABEL: define void @test_alloca
; IFUNC-NOTLS-SAME: () #[[ATTR0]] { ; IFUNC-NOTLS-SAME: () #[[ATTR0]] {
; IFUNC-NOTLS-NEXT: entry: ; IFUNC-NOTLS-NEXT: entry:
; IFUNC-NOTLS-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow) ; IFUNC-NOTLS-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow)
; IFUNC-NOTLS-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; IFUNC-NOTLS-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; IFUNC-NOTLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64 ; IFUNC-NOTLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; IFUNC-NOTLS-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20 ; IFUNC-NOTLS-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; IFUNC-NOTLS-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP1]], [[TMP2]] ; IFUNC-NOTLS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; IFUNC-NOTLS-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP1]], 56 ; IFUNC-NOTLS-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = trunc i64 [[TMP3]] to i8
; IFUNC-NOTLS-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP1]], 56
; IFUNC-NOTLS-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP4]] to i8
; IFUNC-NOTLS-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; IFUNC-NOTLS-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; IFUNC-NOTLS-NEXT: [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0 ; IFUNC-NOTLS-NEXT: [[X_TAG:%.*]] = xor i8 [[HWASAN_STACK_BASE_TAG]], 0
; IFUNC-NOTLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64 ; IFUNC-NOTLS-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[X]] to i64
; IFUNC-NOTLS-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP4]], 72057594037927935 ; IFUNC-NOTLS-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP5]], 72057594037927935
; IFUNC-NOTLS-NEXT: [[TMP5:%.*]] = lshr i64 [[X_NOTAG]], 4 ; IFUNC-NOTLS-NEXT: [[TMP6:%.*]] = lshr i64 [[X_NOTAG]], 4
; IFUNC-NOTLS-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP5]] ; IFUNC-NOTLS-NEXT: [[X_SHADOW:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP6]]
; IFUNC-NOTLS-NEXT: [[TMP6:%.*]] = shl i64 [[TMP3]], 56 ; IFUNC-NOTLS-NEXT: [[TMP7:%.*]] = zext i8 [[X_TAG]] to i64
; IFUNC-NOTLS-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]] ; IFUNC-NOTLS-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 56
; IFUNC-NOTLS-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to ptr ; IFUNC-NOTLS-NEXT: [[TMP9:%.*]] = or i64 [[X_NOTAG]], [[TMP8]]
; IFUNC-NOTLS-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP3]] to i8 ; IFUNC-NOTLS-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP9]] to ptr
; IFUNC-NOTLS-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP8]], i64 1, i1 false) ; IFUNC-NOTLS-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[X_TAG]], i64 1, i1 false)
; IFUNC-NOTLS-NEXT: call void @use(ptr [[X_HWASAN]]) ; IFUNC-NOTLS-NEXT: call void @use(ptr [[X_HWASAN]])
; IFUNC-NOTLS-NEXT: [[TMP9:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; IFUNC-NOTLS-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; IFUNC-NOTLS-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP9]], i64 1, i1 false)
; IFUNC-NOTLS-NEXT: ret void ; IFUNC-NOTLS-NEXT: ret void
; ;
; FUCHSIA-LABEL: define void @test_alloca ; FUCHSIA-LABEL: define void @test_alloca
; FUCHSIA-SAME: () #[[ATTR0]] personality ptr @__hwasan_personality_thunk { ; FUCHSIA-SAME: () #[[ATTR0]] personality ptr @__hwasan_personality_thunk {
; FUCHSIA-NEXT: entry: ; FUCHSIA-NEXT: entry:
; FUCHSIA-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; FUCHSIA-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; FUCHSIA-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8 ; FUCHSIA-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
; FUCHSIA-NEXT: [[TMP1:%.*]] = ashr i64 [[TMP0]], 3 ; FUCHSIA-NEXT: [[TMP1:%.*]] = ashr i64 [[TMP0]], 3
; FUCHSIA-NEXT: [[TMP2:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) ; FUCHSIA-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i8
; FUCHSIA-NEXT: [[TMP3:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; FUCHSIA-NEXT: [[TMP3:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; FUCHSIA-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP3]] to i64 ; FUCHSIA-NEXT: [[TMP4:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; FUCHSIA-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 44 ; FUCHSIA-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[TMP4]] to i64
; FUCHSIA-NEXT: [[TMP6:%.*]] = or i64 [[TMP2]], [[TMP5]] ; FUCHSIA-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 44
; FUCHSIA-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP0]] to ptr ; FUCHSIA-NEXT: [[TMP7:%.*]] = or i64 [[TMP3]], [[TMP6]]
; FUCHSIA-NEXT: store i64 [[TMP6]], ptr [[TMP7]], align 8 ; FUCHSIA-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP0]] to ptr
; FUCHSIA-NEXT: [[TMP8:%.*]] = ashr i64 [[TMP0]], 56 ; FUCHSIA-NEXT: store i64 [[TMP7]], ptr [[TMP8]], align 8
; FUCHSIA-NEXT: [[TMP9:%.*]] = shl nuw nsw i64 [[TMP8]], 12 ; FUCHSIA-NEXT: [[TMP9:%.*]] = ashr i64 [[TMP0]], 56
; FUCHSIA-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], -1 ; FUCHSIA-NEXT: [[TMP10:%.*]] = shl nuw nsw i64 [[TMP9]], 12
; FUCHSIA-NEXT: [[TMP11:%.*]] = add i64 [[TMP0]], 8 ; FUCHSIA-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], -1
; FUCHSIA-NEXT: [[TMP12:%.*]] = and i64 [[TMP11]], [[TMP10]] ; FUCHSIA-NEXT: [[TMP12:%.*]] = add i64 [[TMP0]], 8
; FUCHSIA-NEXT: store i64 [[TMP12]], ptr @__hwasan_tls, align 8 ; FUCHSIA-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], [[TMP11]]
; FUCHSIA-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP4]], 56 ; FUCHSIA-NEXT: store i64 [[TMP13]], ptr @__hwasan_tls, align 8
; FUCHSIA-NEXT: [[TMP14:%.*]] = lshr i64 [[TMP5]], 56
; FUCHSIA-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP14]] to i8
; FUCHSIA-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; FUCHSIA-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; FUCHSIA-NEXT: [[TMP13:%.*]] = xor i64 [[TMP1]], 0 ; FUCHSIA-NEXT: [[X_TAG:%.*]] = xor i8 [[TMP2]], 0
; FUCHSIA-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[X]] to i64 ; FUCHSIA-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[X]] to i64
; FUCHSIA-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP14]], 72057594037927935 ; FUCHSIA-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP15]], 72057594037927935
; FUCHSIA-NEXT: [[TMP15:%.*]] = lshr i64 [[X_NOTAG]], 4 ; FUCHSIA-NEXT: [[TMP16:%.*]] = lshr i64 [[X_NOTAG]], 4
; FUCHSIA-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP15]] to ptr ; FUCHSIA-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP16]] to ptr
; FUCHSIA-NEXT: [[TMP16:%.*]] = shl i64 [[TMP13]], 56 ; FUCHSIA-NEXT: [[TMP17:%.*]] = zext i8 [[X_TAG]] to i64
; FUCHSIA-NEXT: [[TMP17:%.*]] = or i64 [[TMP14]], [[TMP16]] ; FUCHSIA-NEXT: [[TMP18:%.*]] = shl i64 [[TMP17]], 56
; FUCHSIA-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP17]] to ptr ; FUCHSIA-NEXT: [[TMP19:%.*]] = or i64 [[X_NOTAG]], [[TMP18]]
; FUCHSIA-NEXT: [[TMP18:%.*]] = trunc i64 [[TMP13]] to i8 ; FUCHSIA-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP19]] to ptr
; FUCHSIA-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0 ; FUCHSIA-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0
; FUCHSIA-NEXT: store i8 4, ptr [[TMP19]], align 1 ; FUCHSIA-NEXT: store i8 4, ptr [[TMP20]], align 1
; FUCHSIA-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[X]], i32 15 ; FUCHSIA-NEXT: [[TMP21:%.*]] = getelementptr i8, ptr [[X]], i32 15
; FUCHSIA-NEXT: store i8 [[TMP18]], ptr [[TMP20]], align 1 ; FUCHSIA-NEXT: store i8 [[X_TAG]], ptr [[TMP21]], align 1
; FUCHSIA-NEXT: call void @use(ptr [[X_HWASAN]]) ; FUCHSIA-NEXT: call void @use(ptr [[X_HWASAN]])
; FUCHSIA-NEXT: [[TMP21:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; FUCHSIA-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; FUCHSIA-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP21]], i64 1, i1 false)
; FUCHSIA-NEXT: ret void ; FUCHSIA-NEXT: ret void
; ;
; FUCHSIA-LIBCALL-LABEL: define void @test_alloca ; FUCHSIA-LIBCALL-LABEL: define void @test_alloca
; FUCHSIA-LIBCALL-SAME: () #[[ATTR0]] personality ptr @__hwasan_personality_thunk { ; FUCHSIA-LIBCALL-SAME: () #[[ATTR0]] personality ptr @__hwasan_personality_thunk {
; FUCHSIA-LIBCALL-NEXT: entry: ; FUCHSIA-LIBCALL-NEXT: entry:
; FUCHSIA-LIBCALL-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; FUCHSIA-LIBCALL-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; FUCHSIA-LIBCALL-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) ; FUCHSIA-LIBCALL-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; FUCHSIA-LIBCALL-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; FUCHSIA-LIBCALL-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; FUCHSIA-LIBCALL-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 ; FUCHSIA-LIBCALL-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
; FUCHSIA-LIBCALL-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 44 ; FUCHSIA-LIBCALL-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 44
; FUCHSIA-LIBCALL-NEXT: [[TMP4:%.*]] = or i64 [[TMP0]], [[TMP3]] ; FUCHSIA-LIBCALL-NEXT: [[TMP4:%.*]] = or i64 [[TMP0]], [[TMP3]]
; FUCHSIA-LIBCALL-NEXT: call void @__hwasan_add_frame_record(i64 [[TMP4]]) ; FUCHSIA-LIBCALL-NEXT: call void @__hwasan_add_frame_record(i64 [[TMP4]])
; FUCHSIA-LIBCALL-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP2]], 20 ; FUCHSIA-LIBCALL-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP2]], 20
; FUCHSIA-LIBCALL-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP2]], [[TMP5]] ; FUCHSIA-LIBCALL-NEXT: [[TMP6:%.*]] = xor i64 [[TMP2]], [[TMP5]]
; FUCHSIA-LIBCALL-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP2]], 56 ; FUCHSIA-LIBCALL-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = trunc i64 [[TMP6]] to i8
; FUCHSIA-LIBCALL-NEXT: [[TMP7:%.*]] = lshr i64 [[TMP2]], 56
; FUCHSIA-LIBCALL-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP7]] to i8
; FUCHSIA-LIBCALL-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16 ; FUCHSIA-LIBCALL-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; FUCHSIA-LIBCALL-NEXT: [[TMP6:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0 ; FUCHSIA-LIBCALL-NEXT: [[X_TAG:%.*]] = xor i8 [[HWASAN_STACK_BASE_TAG]], 0
; FUCHSIA-LIBCALL-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[X]] to i64 ; FUCHSIA-LIBCALL-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[X]] to i64
; FUCHSIA-LIBCALL-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP7]], 72057594037927935 ; FUCHSIA-LIBCALL-NEXT: [[X_NOTAG:%.*]] = and i64 [[TMP8]], 72057594037927935
; FUCHSIA-LIBCALL-NEXT: [[TMP8:%.*]] = lshr i64 [[X_NOTAG]], 4 ; FUCHSIA-LIBCALL-NEXT: [[TMP9:%.*]] = lshr i64 [[X_NOTAG]], 4
; FUCHSIA-LIBCALL-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP8]] to ptr ; FUCHSIA-LIBCALL-NEXT: [[X_SHADOW:%.*]] = inttoptr i64 [[TMP9]] to ptr
; FUCHSIA-LIBCALL-NEXT: [[TMP9:%.*]] = shl i64 [[TMP6]], 56 ; FUCHSIA-LIBCALL-NEXT: [[TMP10:%.*]] = zext i8 [[X_TAG]] to i64
; FUCHSIA-LIBCALL-NEXT: [[TMP10:%.*]] = or i64 [[TMP7]], [[TMP9]] ; FUCHSIA-LIBCALL-NEXT: [[TMP11:%.*]] = shl i64 [[TMP10]], 56
; FUCHSIA-LIBCALL-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr ; FUCHSIA-LIBCALL-NEXT: [[TMP12:%.*]] = or i64 [[X_NOTAG]], [[TMP11]]
; FUCHSIA-LIBCALL-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP6]] to i8 ; FUCHSIA-LIBCALL-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP12]] to ptr
; FUCHSIA-LIBCALL-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0 ; FUCHSIA-LIBCALL-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[X_SHADOW]], i32 0
; FUCHSIA-LIBCALL-NEXT: store i8 4, ptr [[TMP12]], align 1 ; FUCHSIA-LIBCALL-NEXT: store i8 4, ptr [[TMP13]], align 1
; FUCHSIA-LIBCALL-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[X]], i32 15 ; FUCHSIA-LIBCALL-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[X]], i32 15
; FUCHSIA-LIBCALL-NEXT: store i8 [[TMP11]], ptr [[TMP13]], align 1 ; FUCHSIA-LIBCALL-NEXT: store i8 [[X_TAG]], ptr [[TMP14]], align 1
; FUCHSIA-LIBCALL-NEXT: call void @use(ptr [[X_HWASAN]]) ; FUCHSIA-LIBCALL-NEXT: call void @use(ptr [[X_HWASAN]])
; FUCHSIA-LIBCALL-NEXT: [[TMP14:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; FUCHSIA-LIBCALL-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; FUCHSIA-LIBCALL-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[X_SHADOW]], i8 [[TMP14]], i64 1, i1 false)
; FUCHSIA-LIBCALL-NEXT: ret void ; FUCHSIA-LIBCALL-NEXT: ret void
; ;
entry: entry:
%x = alloca i32, align 4 %x = alloca i32, align 4
call void @use(ptr %x) call void @use(ptr %x)
ret void ret void
} }

llvm/test/Instrumentation/HWAddressSanitizer/stack-coloring.ll

; Test that storage for allocas with disjoint lifetimes is reused with ; Test that storage for allocas with disjoint lifetimes is reused with
; use-after-scope. ; use-after-scope.
; RUN: opt -S -passes=hwasan %s -hwasan-use-after-scope -o - | \ ; RUN: opt -S -passes=hwasan %s -hwasan-use-after-scope -o - | \
; RUN: llc -no-stack-coloring=false -o - | \ ; RUN: llc -no-stack-coloring=false -o - | \
; RUN: FileCheck %s --check-prefix=COLOR ; RUN: FileCheck %s --check-prefix=COLOR
; RUN: opt -S -passes=hwasan -hwasan-use-after-scope %s -o - | \ ; RUN: opt -S -passes=hwasan -hwasan-use-after-scope %s -o - | \
; RUN: llc -no-stack-coloring=true -o - | \ ; RUN: llc -no-stack-coloring=true -o - | \
; RUN: FileCheck %s --check-prefix=NOCOLOR ; RUN: FileCheck %s --check-prefix=NOCOLOR
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-android29" target triple = "aarch64-unknown-linux-android29"
; REQUIRES: aarch64-registered-target ; REQUIRES: aarch64-registered-target
; COLOR: sub sp, sp, #240 ; COLOR: sub sp, sp, #240
; NOCOLOR: sub sp, sp, #400 ; NOCOLOR: sub sp, sp, #384
define i32 @myCall_w2(i32 %in) sanitize_hwaddress { define i32 @myCall_w2(i32 %in) sanitize_hwaddress {
entry: entry:
%a = alloca [17 x ptr], align 8 %a = alloca [17 x ptr], align 8
%a2 = alloca [16 x ptr], align 8 %a2 = alloca [16 x ptr], align 8
call void @llvm.lifetime.start.p0(i64 136, ptr %a) call void @llvm.lifetime.start.p0(i64 136, ptr %a)
%t1 = call i32 @foo(i32 %in, ptr %a) %t1 = call i32 @foo(i32 %in, ptr %a)
%t2 = call i32 @foo(i32 %in, ptr %a) %t2 = call i32 @foo(i32 %in, ptr %a)
Show All 16 Lines

llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope-setjmp.ll

Show All 10 Lines
define dso_local noundef i1 @_Z6targetv() sanitize_hwaddress { define dso_local noundef i1 @_Z6targetv() sanitize_hwaddress {
; CHECK-LABEL: define dso_local noundef i1 @_Z6targetv ; CHECK-LABEL: define dso_local noundef i1 @_Z6targetv
; CHECK-SAME: () #[[ATTR0:[0-9]+]] { ; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.thread.pointer() ; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.thread.pointer()
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 48 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 48
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8
; CHECK-NEXT: [[TMP3:%.*]] = ashr i64 [[TMP2]], 3 ; CHECK-NEXT: [[TMP3:%.*]] = ashr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) ; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; CHECK-NEXT: [[TMP5:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 44 ; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP4]], [[TMP7]] ; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44
; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP2]] to ptr ; CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]]
; CHECK-NEXT: store i64 [[TMP8]], ptr [[TMP9]], align 8 ; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP2]] to ptr
; CHECK-NEXT: [[TMP10:%.*]] = ashr i64 [[TMP2]], 56 ; CHECK-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 8
; CHECK-NEXT: [[TMP11:%.*]] = shl nuw nsw i64 [[TMP10]], 12 ; CHECK-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP2]], 56
; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], -1 ; CHECK-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12
; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP2]], 8 ; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1
; CHECK-NEXT: [[TMP14:%.*]] = and i64 [[TMP13]], [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP2]], 8
; CHECK-NEXT: store i64 [[TMP14]], ptr [[TMP1]], align 8 ; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]]
; CHECK-NEXT: [[TMP15:%.*]] = or i64 [[TMP2]], 4294967295 ; CHECK-NEXT: store i64 [[TMP15]], ptr [[TMP1]], align 8
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP15]], 1 ; CHECK-NEXT: [[TMP16:%.*]] = or i64 [[TMP2]], 4294967295
; CHECK-NEXT: [[TMP16:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP6]], 56 ; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP7]], 56
; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP18]] to i8
; CHECK-NEXT: [[BUF:%.*]] = alloca [4096 x i8], align 16 ; CHECK-NEXT: [[BUF:%.*]] = alloca [4096 x i8], align 16
; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP3]], 0 ; CHECK-NEXT: [[BUF_TAG:%.*]] = xor i8 [[TMP4]], 0
; CHECK-NEXT: [[TMP18:%.*]] = ptrtoint ptr [[BUF]] to i64 ; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[BUF]] to i64
; CHECK-NEXT: [[BUF_NOTAG:%.*]] = and i64 [[TMP18]], 72057594037927935 ; CHECK-NEXT: [[BUF_NOTAG:%.*]] = and i64 [[TMP19]], 72057594037927935
; CHECK-NEXT: [[TMP19:%.*]] = lshr i64 [[BUF_NOTAG]], 4 ; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[BUF_NOTAG]], 4
; CHECK-NEXT: [[BUF_SHADOW:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP19]] ; CHECK-NEXT: [[BUF_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP20]]
; CHECK-NEXT: [[TMP20:%.*]] = shl i64 [[TMP17]], 56 ; CHECK-NEXT: [[TMP21:%.*]] = zext i8 [[BUF_TAG]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = or i64 [[TMP18]], [[TMP20]] ; CHECK-NEXT: [[TMP22:%.*]] = shl i64 [[TMP21]], 56
; CHECK-NEXT: [[BUF_HWASAN:%.*]] = inttoptr i64 [[TMP21]] to ptr ; CHECK-NEXT: [[TMP23:%.*]] = or i64 [[BUF_NOTAG]], [[TMP22]]
; CHECK-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP17]] to i8 ; CHECK-NEXT: [[BUF_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[BUF_SHADOW]], i8 [[TMP22]], i64 256, i1 false) ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[BUF_SHADOW]], i8 [[BUF_TAG]], i64 256, i1 false)
; CHECK-NEXT: [[CALL:%.*]] = call i32 @setjmp(ptr noundef @jbuf) ; CHECK-NEXT: [[CALL:%.*]] = call i32 @setjmp(ptr noundef @jbuf)
; CHECK-NEXT: switch i32 [[CALL]], label [[WHILE_BODY:%.*]] [ ; CHECK-NEXT: switch i32 [[CALL]], label [[WHILE_BODY:%.*]] [
; CHECK-NEXT: i32 1, label [[RETURN:%.*]] ; CHECK-NEXT: i32 1, label [[RETURN:%.*]]
; CHECK-NEXT: i32 2, label [[SW_BB1:%.*]] ; CHECK-NEXT: i32 2, label [[SW_BB1:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: sw.bb1: ; CHECK: sw.bb1:
; CHECK-NEXT: br label [[RETURN]] ; CHECK-NEXT: br label [[RETURN]]
; CHECK: while.body: ; CHECK: while.body:
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[TMP16]], ptr @stackbuf, i32 19) ; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[TMP17]], ptr @stackbuf, i32 19)
; CHECK-NEXT: store ptr [[BUF_HWASAN]], ptr @stackbuf, align 8 ; CHECK-NEXT: store ptr [[BUF_HWASAN]], ptr @stackbuf, align 8
; CHECK-NEXT: call void @may_jump() ; CHECK-NEXT: call void @may_jump()
; CHECK-NEXT: br label [[RETURN]] ; CHECK-NEXT: br label [[RETURN]]
; CHECK: return: ; CHECK: return:
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i1 [ true, [[WHILE_BODY]] ], [ true, [[SW_BB1]] ], [ false, [[ENTRY:%.*]] ] ; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i1 [ true, [[WHILE_BODY]] ], [ true, [[SW_BB1]] ], [ false, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[BUF_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 256, i1 false)
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[BUF_SHADOW]], i8 [[TMP23]], i64 256, i1 false)
; CHECK-NEXT: ret i1 [[RETVAL_0]] ; CHECK-NEXT: ret i1 [[RETVAL_0]]
; ;
entry: entry:
%buf = alloca [4096 x i8], align 1 %buf = alloca [4096 x i8], align 1
%call = call i32 @setjmp(ptr noundef @jbuf) %call = call i32 @setjmp(ptr noundef @jbuf)
switch i32 %call, label %while.body [ switch i32 %call, label %while.body [
i32 1, label %return i32 1, label %return
i32 2, label %sw.bb1 i32 2, label %sw.bb1
Show All 24 Lines

llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll

Show All 22 Lines
define dso_local i32 @standard_lifetime() local_unnamed_addr sanitize_hwaddress { define dso_local i32 @standard_lifetime() local_unnamed_addr sanitize_hwaddress {
; X86-SCOPE-LABEL: @standard_lifetime( ; X86-SCOPE-LABEL: @standard_lifetime(
; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; X86-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; X86-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; X86-SCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 ; X86-SCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
; X86-SCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57 ; X86-SCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57
; X86-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP3]], 63 ; X86-SCOPE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; X86-SCOPE-NEXT: [[TMP4:%.*]] = alloca { i8, [15 x i8] }, align 16 ; X86-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP4]], 63
; X86-SCOPE-NEXT: [[TMP5:%.*]] = call i8 @__hwasan_generate_tag() ; X86-SCOPE-NEXT: [[TMP5:%.*]] = alloca { i8, [15 x i8] }, align 16
; X86-SCOPE-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i64 ; X86-SCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; X86-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 ; X86-SCOPE-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; X86-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP7]], -9079256848778919937 ; X86-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP6]], -9079256848778919937
; X86-SCOPE-NEXT: [[TMP8:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; X86-SCOPE-NEXT: [[TMP7:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; X86-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP8]] to ptr ; X86-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP7]] to ptr
; X86-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP6]], 57 ; X86-SCOPE-NEXT: [[TMP8:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; X86-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP7]], [[TMP9]] ; X86-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 57
; X86-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP9]]
; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr ; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr
; X86-SCOPE-NEXT: br label [[TMP11:%.*]] ; X86-SCOPE-NEXT: br label [[TMP11:%.*]]
; X86-SCOPE: 11: ; X86-SCOPE: 11:
; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP4]]) ; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP5]])
; X86-SCOPE-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP6]] to i8 ; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[ALLOCA_0_TAG]], i64 16)
; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP12]], i64 16) ; X86-SCOPE-NEXT: [[TMP12:%.*]] = tail call i1 (...) @cond()
; X86-SCOPE-NEXT: [[TMP13:%.*]] = tail call i1 (...) @cond() ; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[HWASAN_UAR_TAG]], i64 16)
; X86-SCOPE-NEXT: [[TMP14:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP5]])
; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP14]], i64 16) ; X86-SCOPE-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP11]]
; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP4]]) ; X86-SCOPE: 13:
; X86-SCOPE-NEXT: br i1 [[TMP13]], label [[TMP15:%.*]], label [[TMP11]]
; X86-SCOPE: 15:
; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; X86-SCOPE-NEXT: ret i32 0 ; X86-SCOPE-NEXT: ret i32 0
; ;
; X86-NOSCOPE-LABEL: @standard_lifetime( ; X86-NOSCOPE-LABEL: @standard_lifetime(
; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; X86-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; X86-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 ; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57 ; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57
; X86-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP3]], 63 ; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = alloca { i8, [15 x i8] }, align 16 ; X86-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP4]], 63
; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = call i8 @__hwasan_generate_tag() ; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = alloca { i8, [15 x i8] }, align 16
; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i64 ; X86-NOSCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 ; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; X86-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP7]], -9079256848778919937 ; X86-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP6]], -9079256848778919937
; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; X86-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP8]] to ptr ; X86-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP7]] to ptr
; X86-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP6]], 57 ; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; X86-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP7]], [[TMP9]] ; X86-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 57
; X86-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP9]]
; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr ; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr
; X86-NOSCOPE-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP6]] to i8 ; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[ALLOCA_0_TAG]], i64 16)
; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP11]], i64 16) ; X86-NOSCOPE-NEXT: br label [[TMP11:%.*]]
; X86-NOSCOPE-NEXT: br label [[TMP12:%.*]] ; X86-NOSCOPE: 11:
; X86-NOSCOPE: 12: ; X86-NOSCOPE-NEXT: [[TMP12:%.*]] = tail call i1 (...) @cond()
; X86-NOSCOPE-NEXT: [[TMP13:%.*]] = tail call i1 (...) @cond() ; X86-NOSCOPE-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP11]]
; X86-NOSCOPE-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP12]] ; X86-NOSCOPE: 13:
; X86-NOSCOPE: 14:
; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; X86-NOSCOPE-NEXT: [[TMP15:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[HWASAN_UAR_TAG]], i64 16)
; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP15]], i64 16)
; X86-NOSCOPE-NEXT: ret i32 0 ; X86-NOSCOPE-NEXT: ret i32 0
; ;
; AARCH64-SCOPE-LABEL: @standard_lifetime( ; AARCH64-SCOPE-LABEL: @standard_lifetime(
; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) ; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-SCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-SCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-SCOPE-NEXT: br label [[TMP25:%.*]] ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-SCOPE: 25: ; AARCH64-SCOPE-NEXT: br label [[TMP26:%.*]]
; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) ; AARCH64-SCOPE: 26:
; AARCH64-SCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP26]], i64 1, i1 false) ; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[ALLOCA_0_TAG]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: [[TMP27:%.*]] = tail call i1 (...) @cond() ; AARCH64-SCOPE-NEXT: [[TMP27:%.*]] = tail call i1 (...) @cond()
; AARCH64-SCOPE-NEXT: [[TMP28:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP28]], i64 1, i1 false) ; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]]) ; AARCH64-SCOPE-NEXT: br i1 [[TMP27]], label [[TMP28:%.*]], label [[TMP26]]
; AARCH64-SCOPE-NEXT: br i1 [[TMP27]], label [[TMP29:%.*]], label [[TMP25]] ; AARCH64-SCOPE: 28:
; AARCH64-SCOPE: 29:
; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SCOPE-NEXT: ret i32 0 ; AARCH64-SCOPE-NEXT: ret i32 0
; ;
; AARCH64-NOSCOPE-LABEL: @standard_lifetime( ; AARCH64-NOSCOPE-LABEL: @standard_lifetime(
; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) ; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-NOSCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-NOSCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP25]], i64 1, i1 false) ; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[ALLOCA_0_TAG]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: br label [[TMP26:%.*]] ; AARCH64-NOSCOPE-NEXT: br label [[TMP26:%.*]]
; AARCH64-NOSCOPE: 26: ; AARCH64-NOSCOPE: 26:
; AARCH64-NOSCOPE-NEXT: [[TMP27:%.*]] = tail call i1 (...) @cond() ; AARCH64-NOSCOPE-NEXT: [[TMP27:%.*]] = tail call i1 (...) @cond()
; AARCH64-NOSCOPE-NEXT: br i1 [[TMP27]], label [[TMP28:%.*]], label [[TMP26]] ; AARCH64-NOSCOPE-NEXT: br i1 [[TMP27]], label [[TMP28:%.*]], label [[TMP26]]
; AARCH64-NOSCOPE: 28: ; AARCH64-NOSCOPE: 28:
; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-NOSCOPE-NEXT: [[TMP29:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP29]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: ret i32 0 ; AARCH64-NOSCOPE-NEXT: ret i32 0
; ;
; AARCH64-SHORT-SCOPE-LABEL: @standard_lifetime( ; AARCH64-SHORT-SCOPE-LABEL: @standard_lifetime(
; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP25:%.*]] ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-SHORT-SCOPE: 25: ; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP26:%.*]]
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) ; AARCH64-SHORT-SCOPE: 26:
; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0
; AARCH64-SHORT-SCOPE-NEXT: store i8 1, ptr [[TMP27]], align 1 ; AARCH64-SHORT-SCOPE-NEXT: store i8 1, ptr [[TMP27]], align 1
; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP20]], i32 15
; AARCH64-SHORT-SCOPE-NEXT: store i8 [[TMP26]], ptr [[TMP28]], align 1 ; AARCH64-SHORT-SCOPE-NEXT: store i8 [[ALLOCA_0_TAG]], ptr [[TMP28]], align 1
; AARCH64-SHORT-SCOPE-NEXT: [[TMP29:%.*]] = tail call i1 (...) @cond() ; AARCH64-SHORT-SCOPE-NEXT: [[TMP29:%.*]] = tail call i1 (...) @cond()
; AARCH64-SHORT-SCOPE-NEXT: [[TMP30:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP30]], i64 1, i1 false) ; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]]) ; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP26]]
; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP29]], label [[TMP31:%.*]], label [[TMP25]] ; AARCH64-SHORT-SCOPE: 30:
; AARCH64-SHORT-SCOPE: 31:
; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SHORT-SCOPE-NEXT: ret i32 0 ; AARCH64-SHORT-SCOPE-NEXT: ret i32 0
; ;
; AARCH64-SHORT-NOSCOPE-LABEL: @standard_lifetime( ; AARCH64-SHORT-NOSCOPE-LABEL: @standard_lifetime(
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0
; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1 ; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP20]], i32 15
; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[TMP25]], ptr [[TMP27]], align 1 ; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[ALLOCA_0_TAG]], ptr [[TMP27]], align 1
; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP28:%.*]] ; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP28:%.*]]
; AARCH64-SHORT-NOSCOPE: 28: ; AARCH64-SHORT-NOSCOPE: 28:
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP29:%.*]] = tail call i1 (...) @cond() ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP29:%.*]] = tail call i1 (...) @cond()
; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP28]] ; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP28]]
; AARCH64-SHORT-NOSCOPE: 30: ; AARCH64-SHORT-NOSCOPE: 30:
; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP31:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP31]], i64 1, i1 false)
; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0 ; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0
; ;
%1 = alloca i8, align 1 %1 = alloca i8, align 1
br label %2 br label %2
2: ; preds = %2, %0 2: ; preds = %2, %0
; We should tag the memory after the br (in the loop). ; We should tag the memory after the br (in the loop).
call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1) call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1)
%3 = tail call i1 (...) @cond() #2 %3 = tail call i1 (...) @cond() #2
; We should tag the memory before the next br (before the jump back). ; We should tag the memory before the next br (before the jump back).
call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1) call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1)
br i1 %3, label %4, label %2 br i1 %3, label %4, label %2
4: ; preds = %2 4: ; preds = %2
call void @use(ptr nonnull %1) #2 call void @use(ptr nonnull %1) #2
ret i32 0 ret i32 0
} }
define dso_local i32 @standard_lifetime_optnone() local_unnamed_addr optnone noinline sanitize_hwaddress { define dso_local i32 @standard_lifetime_optnone() local_unnamed_addr optnone noinline sanitize_hwaddress {
; X86-SCOPE-LABEL: @standard_lifetime_optnone( ; X86-SCOPE-LABEL: @standard_lifetime_optnone(
; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; X86-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; X86-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; X86-SCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 ; X86-SCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
; X86-SCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57 ; X86-SCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57
; X86-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP3]], 63 ; X86-SCOPE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; X86-SCOPE-NEXT: [[TMP4:%.*]] = alloca { i8, [15 x i8] }, align 16 ; X86-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP4]], 63
; X86-SCOPE-NEXT: [[TMP5:%.*]] = call i8 @__hwasan_generate_tag() ; X86-SCOPE-NEXT: [[TMP5:%.*]] = alloca { i8, [15 x i8] }, align 16
; X86-SCOPE-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i64 ; X86-SCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; X86-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 ; X86-SCOPE-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; X86-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP7]], -9079256848778919937 ; X86-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP6]], -9079256848778919937
; X86-SCOPE-NEXT: [[TMP8:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; X86-SCOPE-NEXT: [[TMP7:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; X86-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP8]] to ptr ; X86-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP7]] to ptr
; X86-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP6]], 57 ; X86-SCOPE-NEXT: [[TMP8:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; X86-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP7]], [[TMP9]] ; X86-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 57
; X86-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP9]]
; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr ; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr
; X86-SCOPE-NEXT: br label [[TMP11:%.*]] ; X86-SCOPE-NEXT: br label [[TMP11:%.*]]
; X86-SCOPE: 11: ; X86-SCOPE: 11:
; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP4]]) ; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP5]])
; X86-SCOPE-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP6]] to i8 ; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[ALLOCA_0_TAG]], i64 16)
; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP12]], i64 16) ; X86-SCOPE-NEXT: [[TMP12:%.*]] = tail call i1 (...) @cond()
; X86-SCOPE-NEXT: [[TMP13:%.*]] = tail call i1 (...) @cond() ; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[HWASAN_UAR_TAG]], i64 16)
; X86-SCOPE-NEXT: [[TMP14:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP5]])
; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP14]], i64 16) ; X86-SCOPE-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP11]]
; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP4]]) ; X86-SCOPE: 13:
; X86-SCOPE-NEXT: br i1 [[TMP13]], label [[TMP15:%.*]], label [[TMP11]]
; X86-SCOPE: 15:
; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; X86-SCOPE-NEXT: ret i32 0 ; X86-SCOPE-NEXT: ret i32 0
; ;
; X86-NOSCOPE-LABEL: @standard_lifetime_optnone( ; X86-NOSCOPE-LABEL: @standard_lifetime_optnone(
; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; X86-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; X86-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 ; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57 ; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57
; X86-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP3]], 63 ; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = alloca { i8, [15 x i8] }, align 16 ; X86-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP4]], 63
; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = call i8 @__hwasan_generate_tag() ; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = alloca { i8, [15 x i8] }, align 16
; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i64 ; X86-NOSCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 ; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; X86-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP7]], -9079256848778919937 ; X86-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP6]], -9079256848778919937
; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; X86-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP8]] to ptr ; X86-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP7]] to ptr
; X86-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP6]], 57 ; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; X86-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP7]], [[TMP9]] ; X86-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 57
; X86-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP9]]
; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr ; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr
; X86-NOSCOPE-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP6]] to i8 ; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[ALLOCA_0_TAG]], i64 16)
; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP11]], i64 16) ; X86-NOSCOPE-NEXT: br label [[TMP11:%.*]]
; X86-NOSCOPE-NEXT: br label [[TMP12:%.*]] ; X86-NOSCOPE: 11:
; X86-NOSCOPE: 12: ; X86-NOSCOPE-NEXT: [[TMP12:%.*]] = tail call i1 (...) @cond()
; X86-NOSCOPE-NEXT: [[TMP13:%.*]] = tail call i1 (...) @cond() ; X86-NOSCOPE-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP11]]
; X86-NOSCOPE-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP12]] ; X86-NOSCOPE: 13:
; X86-NOSCOPE: 14:
; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; X86-NOSCOPE-NEXT: [[TMP15:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[HWASAN_UAR_TAG]], i64 16)
; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP15]], i64 16)
; X86-NOSCOPE-NEXT: ret i32 0 ; X86-NOSCOPE-NEXT: ret i32 0
; ;
; AARCH64-SCOPE-LABEL: @standard_lifetime_optnone( ; AARCH64-SCOPE-LABEL: @standard_lifetime_optnone(
; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-SCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-SCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-SCOPE-NEXT: br label [[TMP25:%.*]] ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-SCOPE: 25: ; AARCH64-SCOPE-NEXT: br label [[TMP26:%.*]]
; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) ; AARCH64-SCOPE: 26:
; AARCH64-SCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP26]], i64 1, i1 false) ; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[ALLOCA_0_TAG]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: [[TMP27:%.*]] = tail call i1 (...) @cond() ; AARCH64-SCOPE-NEXT: [[TMP27:%.*]] = tail call i1 (...) @cond()
; AARCH64-SCOPE-NEXT: [[TMP28:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP28]], i64 1, i1 false) ; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]]) ; AARCH64-SCOPE-NEXT: br i1 [[TMP27]], label [[TMP28:%.*]], label [[TMP26]]
; AARCH64-SCOPE-NEXT: br i1 [[TMP27]], label [[TMP29:%.*]], label [[TMP25]] ; AARCH64-SCOPE: 28:
; AARCH64-SCOPE: 29:
; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SCOPE-NEXT: ret i32 0 ; AARCH64-SCOPE-NEXT: ret i32 0
; ;
; AARCH64-NOSCOPE-LABEL: @standard_lifetime_optnone( ; AARCH64-NOSCOPE-LABEL: @standard_lifetime_optnone(
; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-NOSCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-NOSCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP25]], i64 1, i1 false) ; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[ALLOCA_0_TAG]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: br label [[TMP26:%.*]] ; AARCH64-NOSCOPE-NEXT: br label [[TMP26:%.*]]
; AARCH64-NOSCOPE: 26: ; AARCH64-NOSCOPE: 26:
; AARCH64-NOSCOPE-NEXT: [[TMP27:%.*]] = tail call i1 (...) @cond() ; AARCH64-NOSCOPE-NEXT: [[TMP27:%.*]] = tail call i1 (...) @cond()
; AARCH64-NOSCOPE-NEXT: br i1 [[TMP27]], label [[TMP28:%.*]], label [[TMP26]] ; AARCH64-NOSCOPE-NEXT: br i1 [[TMP27]], label [[TMP28:%.*]], label [[TMP26]]
; AARCH64-NOSCOPE: 28: ; AARCH64-NOSCOPE: 28:
; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-NOSCOPE-NEXT: [[TMP29:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP29]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: ret i32 0 ; AARCH64-NOSCOPE-NEXT: ret i32 0
; ;
; AARCH64-SHORT-SCOPE-LABEL: @standard_lifetime_optnone( ; AARCH64-SHORT-SCOPE-LABEL: @standard_lifetime_optnone(
; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP25:%.*]] ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-SHORT-SCOPE: 25: ; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP26:%.*]]
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) ; AARCH64-SHORT-SCOPE: 26:
; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0
; AARCH64-SHORT-SCOPE-NEXT: store i8 1, ptr [[TMP27]], align 1 ; AARCH64-SHORT-SCOPE-NEXT: store i8 1, ptr [[TMP27]], align 1
; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP20]], i32 15
; AARCH64-SHORT-SCOPE-NEXT: store i8 [[TMP26]], ptr [[TMP28]], align 1 ; AARCH64-SHORT-SCOPE-NEXT: store i8 [[ALLOCA_0_TAG]], ptr [[TMP28]], align 1
; AARCH64-SHORT-SCOPE-NEXT: [[TMP29:%.*]] = tail call i1 (...) @cond() ; AARCH64-SHORT-SCOPE-NEXT: [[TMP29:%.*]] = tail call i1 (...) @cond()
; AARCH64-SHORT-SCOPE-NEXT: [[TMP30:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP30]], i64 1, i1 false) ; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]]) ; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP26]]
; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP29]], label [[TMP31:%.*]], label [[TMP25]] ; AARCH64-SHORT-SCOPE: 30:
; AARCH64-SHORT-SCOPE: 31:
; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SHORT-SCOPE-NEXT: ret i32 0 ; AARCH64-SHORT-SCOPE-NEXT: ret i32 0
; ;
; AARCH64-SHORT-NOSCOPE-LABEL: @standard_lifetime_optnone( ; AARCH64-SHORT-NOSCOPE-LABEL: @standard_lifetime_optnone(
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0
; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1 ; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP20]], i32 15
; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[TMP25]], ptr [[TMP27]], align 1 ; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[ALLOCA_0_TAG]], ptr [[TMP27]], align 1
; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP28:%.*]] ; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP28:%.*]]
; AARCH64-SHORT-NOSCOPE: 28: ; AARCH64-SHORT-NOSCOPE: 28:
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP29:%.*]] = tail call i1 (...) @cond() ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP29:%.*]] = tail call i1 (...) @cond()
; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP28]] ; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP28]]
; AARCH64-SHORT-NOSCOPE: 30: ; AARCH64-SHORT-NOSCOPE: 30:
; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP31:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP31]], i64 1, i1 false)
; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0 ; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0
; ;
%1 = alloca i8, align 1 %1 = alloca i8, align 1
br label %2 br label %2
2: ; preds = %2, %0 2: ; preds = %2, %0
; We should tag the memory after the br (in the loop). ; We should tag the memory after the br (in the loop).
call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1) call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1)
%3 = tail call i1 (...) @cond() #2 %3 = tail call i1 (...) @cond() #2
; We should tag the memory before the next br (before the jump back). ; We should tag the memory before the next br (before the jump back).
call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1) call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1)
br i1 %3, label %4, label %2 br i1 %3, label %4, label %2
4: ; preds = %2 4: ; preds = %2
call void @use(ptr nonnull %1) #2 call void @use(ptr nonnull %1) #2
ret i32 0 ret i32 0
} }
define dso_local i32 @multiple_lifetimes() local_unnamed_addr sanitize_hwaddress { define dso_local i32 @multiple_lifetimes() local_unnamed_addr sanitize_hwaddress {
; X86-SCOPE-LABEL: @multiple_lifetimes( ; X86-SCOPE-LABEL: @multiple_lifetimes(
; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; X86-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; X86-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; X86-SCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 ; X86-SCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
; X86-SCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57 ; X86-SCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57
; X86-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP3]], 63 ; X86-SCOPE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; X86-SCOPE-NEXT: [[TMP4:%.*]] = alloca { i8, [15 x i8] }, align 16 ; X86-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP4]], 63
; X86-SCOPE-NEXT: [[TMP5:%.*]] = call i8 @__hwasan_generate_tag() ; X86-SCOPE-NEXT: [[TMP5:%.*]] = alloca { i8, [15 x i8] }, align 16
; X86-SCOPE-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i64 ; X86-SCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; X86-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 ; X86-SCOPE-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; X86-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP7]], -9079256848778919937 ; X86-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP6]], -9079256848778919937
; X86-SCOPE-NEXT: [[TMP8:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; X86-SCOPE-NEXT: [[TMP7:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; X86-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP8]] to ptr ; X86-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP7]] to ptr
; X86-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP6]], 57 ; X86-SCOPE-NEXT: [[TMP8:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; X86-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP7]], [[TMP9]] ; X86-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 57
; X86-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP9]]
; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr ; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr
; X86-SCOPE-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP6]] to i8 ; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[ALLOCA_0_TAG]], i64 16)
; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP11]], i64 16)
; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; X86-SCOPE-NEXT: [[TMP12:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[HWASAN_UAR_TAG]], i64 16)
; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP12]], i64 16)
; X86-SCOPE-NEXT: ret i32 0 ; X86-SCOPE-NEXT: ret i32 0
; ;
; X86-NOSCOPE-LABEL: @multiple_lifetimes( ; X86-NOSCOPE-LABEL: @multiple_lifetimes(
; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; X86-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; X86-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 ; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57 ; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57
; X86-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP3]], 63 ; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = alloca { i8, [15 x i8] }, align 16 ; X86-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP4]], 63
; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = call i8 @__hwasan_generate_tag() ; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = alloca { i8, [15 x i8] }, align 16
; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i64 ; X86-NOSCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 ; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; X86-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP7]], -9079256848778919937 ; X86-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP6]], -9079256848778919937
; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; X86-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP8]] to ptr ; X86-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP7]] to ptr
; X86-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP6]], 57 ; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; X86-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP7]], [[TMP9]] ; X86-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 57
; X86-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP9]]
; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr ; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr
; X86-NOSCOPE-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP6]] to i8 ; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[ALLOCA_0_TAG]], i64 16)
; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP11]], i64 16)
; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; X86-NOSCOPE-NEXT: [[TMP12:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[HWASAN_UAR_TAG]], i64 16)
; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP12]], i64 16)
; X86-NOSCOPE-NEXT: ret i32 0 ; X86-NOSCOPE-NEXT: ret i32 0
; ;
; AARCH64-SCOPE-LABEL: @multiple_lifetimes( ; AARCH64-SCOPE-LABEL: @multiple_lifetimes(
; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-SCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-SCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP25]], i64 1, i1 false) ; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[ALLOCA_0_TAG]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP26]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: ret i32 0 ; AARCH64-SCOPE-NEXT: ret i32 0
; ;
; AARCH64-NOSCOPE-LABEL: @multiple_lifetimes( ; AARCH64-NOSCOPE-LABEL: @multiple_lifetimes(
; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-NOSCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-NOSCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP25]], i64 1, i1 false) ; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[ALLOCA_0_TAG]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-NOSCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP26]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: ret i32 0 ; AARCH64-NOSCOPE-NEXT: ret i32 0
; ;
; AARCH64-SHORT-SCOPE-LABEL: @multiple_lifetimes( ; AARCH64-SHORT-SCOPE-LABEL: @multiple_lifetimes(
; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0
; AARCH64-SHORT-SCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1 ; AARCH64-SHORT-SCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1
; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP20]], i32 15
; AARCH64-SHORT-SCOPE-NEXT: store i8 [[TMP25]], ptr [[TMP27]], align 1 ; AARCH64-SHORT-SCOPE-NEXT: store i8 [[ALLOCA_0_TAG]], ptr [[TMP27]], align 1
; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP28]], i64 1, i1 false)
; AARCH64-SHORT-SCOPE-NEXT: ret i32 0 ; AARCH64-SHORT-SCOPE-NEXT: ret i32 0
; ;
; AARCH64-SHORT-NOSCOPE-LABEL: @multiple_lifetimes( ; AARCH64-SHORT-NOSCOPE-LABEL: @multiple_lifetimes(
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0
; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1 ; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP20]], i32 15
; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[TMP25]], ptr [[TMP27]], align 1 ; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[ALLOCA_0_TAG]], ptr [[TMP27]], align 1
; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP28:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP28]], i64 1, i1 false)
; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0 ; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0
; ;
%1 = alloca i8, align 1 %1 = alloca i8, align 1
; We erase lifetime markers if we insert instrumentation outside of the ; We erase lifetime markers if we insert instrumentation outside of the
; lifetime. ; lifetime.
call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1) call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1)
call void @use(ptr nonnull %1) #2 call void @use(ptr nonnull %1) #2
call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1) call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1)
call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1) call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1)
call void @use(ptr nonnull %1) #2 call void @use(ptr nonnull %1) #2
call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1) call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1)
ret i32 0 ret i32 0
} }
define dso_local i32 @unreachable_exit() local_unnamed_addr sanitize_hwaddress { define dso_local i32 @unreachable_exit() local_unnamed_addr sanitize_hwaddress {
; X86-SCOPE-LABEL: @unreachable_exit( ; X86-SCOPE-LABEL: @unreachable_exit(
; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; X86-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; X86-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; X86-SCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 ; X86-SCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
; X86-SCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57 ; X86-SCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57
; X86-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP3]], 63 ; X86-SCOPE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; X86-SCOPE-NEXT: [[TMP4:%.*]] = alloca { i8, [15 x i8] }, align 16 ; X86-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP4]], 63
; X86-SCOPE-NEXT: [[TMP5:%.*]] = call i8 @__hwasan_generate_tag() ; X86-SCOPE-NEXT: [[TMP5:%.*]] = alloca { i8, [15 x i8] }, align 16
; X86-SCOPE-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i64 ; X86-SCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; X86-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 ; X86-SCOPE-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; X86-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP7]], -9079256848778919937 ; X86-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP6]], -9079256848778919937
; X86-SCOPE-NEXT: [[TMP8:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; X86-SCOPE-NEXT: [[TMP7:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; X86-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP8]] to ptr ; X86-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP7]] to ptr
; X86-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP6]], 57 ; X86-SCOPE-NEXT: [[TMP8:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; X86-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP7]], [[TMP9]] ; X86-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 57
; X86-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP9]]
; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr ; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr
; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP4]]) ; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP5]])
; X86-SCOPE-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP6]] to i8 ; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[ALLOCA_0_TAG]], i64 16)
; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP11]], i64 16) ; X86-SCOPE-NEXT: [[TMP11:%.*]] = tail call i1 (...) @cond()
; X86-SCOPE-NEXT: [[TMP12:%.*]] = tail call i1 (...) @cond() ; X86-SCOPE-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP13:%.*]]
; X86-SCOPE-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP15:%.*]] ; X86-SCOPE: 12:
; X86-SCOPE: 13:
; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; X86-SCOPE-NEXT: [[TMP14:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[HWASAN_UAR_TAG]], i64 16)
; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP14]], i64 16)
; X86-SCOPE-NEXT: ret i32 0 ; X86-SCOPE-NEXT: ret i32 0
; X86-SCOPE: 15: ; X86-SCOPE: 13:
; X86-SCOPE-NEXT: [[TMP16:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[HWASAN_UAR_TAG]], i64 16)
; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP16]], i64 16)
; X86-SCOPE-NEXT: ret i32 0 ; X86-SCOPE-NEXT: ret i32 0
; ;
; X86-NOSCOPE-LABEL: @unreachable_exit( ; X86-NOSCOPE-LABEL: @unreachable_exit(
; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; X86-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; X86-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 ; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57 ; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57
; X86-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP3]], 63 ; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = alloca { i8, [15 x i8] }, align 16 ; X86-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP4]], 63
; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = call i8 @__hwasan_generate_tag() ; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = alloca { i8, [15 x i8] }, align 16
; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i64 ; X86-NOSCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 ; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; X86-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP7]], -9079256848778919937 ; X86-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP6]], -9079256848778919937
; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; X86-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP8]] to ptr ; X86-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP7]] to ptr
; X86-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP6]], 57 ; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; X86-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP7]], [[TMP9]] ; X86-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 57
; X86-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP9]]
; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr ; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr
; X86-NOSCOPE-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP6]] to i8 ; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[ALLOCA_0_TAG]], i64 16)
; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP11]], i64 16) ; X86-NOSCOPE-NEXT: [[TMP11:%.*]] = tail call i1 (...) @cond()
; X86-NOSCOPE-NEXT: [[TMP12:%.*]] = tail call i1 (...) @cond() ; X86-NOSCOPE-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP13:%.*]]
; X86-NOSCOPE-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP15:%.*]] ; X86-NOSCOPE: 12:
; X86-NOSCOPE: 13:
; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; X86-NOSCOPE-NEXT: [[TMP14:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[HWASAN_UAR_TAG]], i64 16)
; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP14]], i64 16)
; X86-NOSCOPE-NEXT: ret i32 0 ; X86-NOSCOPE-NEXT: ret i32 0
; X86-NOSCOPE: 15: ; X86-NOSCOPE: 13:
; X86-NOSCOPE-NEXT: [[TMP16:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[HWASAN_UAR_TAG]], i64 16)
; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP16]], i64 16)
; X86-NOSCOPE-NEXT: ret i32 0 ; X86-NOSCOPE-NEXT: ret i32 0
; ;
; AARCH64-SCOPE-LABEL: @unreachable_exit( ; AARCH64-SCOPE-LABEL: @unreachable_exit(
; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-SCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-SCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP25]], i64 1, i1 false) ; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[ALLOCA_0_TAG]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: [[TMP26:%.*]] = tail call i1 (...) @cond() ; AARCH64-SCOPE-NEXT: [[TMP26:%.*]] = tail call i1 (...) @cond()
; AARCH64-SCOPE-NEXT: br i1 [[TMP26]], label [[TMP27:%.*]], label [[TMP29:%.*]] ; AARCH64-SCOPE-NEXT: br i1 [[TMP26]], label [[TMP27:%.*]], label [[TMP28:%.*]]
; AARCH64-SCOPE: 27: ; AARCH64-SCOPE: 27:
; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SCOPE-NEXT: [[TMP28:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP28]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: ret i32 0 ; AARCH64-SCOPE-NEXT: ret i32 0
; AARCH64-SCOPE: 29: ; AARCH64-SCOPE: 28:
; AARCH64-SCOPE-NEXT: [[TMP30:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP30]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: ret i32 0 ; AARCH64-SCOPE-NEXT: ret i32 0
; ;
; AARCH64-NOSCOPE-LABEL: @unreachable_exit( ; AARCH64-NOSCOPE-LABEL: @unreachable_exit(
; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-NOSCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-NOSCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP25]], i64 1, i1 false) ; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[ALLOCA_0_TAG]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: [[TMP26:%.*]] = tail call i1 (...) @cond() ; AARCH64-NOSCOPE-NEXT: [[TMP26:%.*]] = tail call i1 (...) @cond()
; AARCH64-NOSCOPE-NEXT: br i1 [[TMP26]], label [[TMP27:%.*]], label [[TMP29:%.*]] ; AARCH64-NOSCOPE-NEXT: br i1 [[TMP26]], label [[TMP27:%.*]], label [[TMP28:%.*]]
; AARCH64-NOSCOPE: 27: ; AARCH64-NOSCOPE: 27:
; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-NOSCOPE-NEXT: [[TMP28:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP28]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: ret i32 0 ; AARCH64-NOSCOPE-NEXT: ret i32 0
; AARCH64-NOSCOPE: 29: ; AARCH64-NOSCOPE: 28:
; AARCH64-NOSCOPE-NEXT: [[TMP30:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP30]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: ret i32 0 ; AARCH64-NOSCOPE-NEXT: ret i32 0
; ;
; AARCH64-SHORT-SCOPE-LABEL: @unreachable_exit( ; AARCH64-SHORT-SCOPE-LABEL: @unreachable_exit(
; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0
; AARCH64-SHORT-SCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1 ; AARCH64-SHORT-SCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1
; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP20]], i32 15
; AARCH64-SHORT-SCOPE-NEXT: store i8 [[TMP25]], ptr [[TMP27]], align 1 ; AARCH64-SHORT-SCOPE-NEXT: store i8 [[ALLOCA_0_TAG]], ptr [[TMP27]], align 1
; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = tail call i1 (...) @cond() ; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = tail call i1 (...) @cond()
; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP31:%.*]] ; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP30:%.*]]
; AARCH64-SHORT-SCOPE: 29: ; AARCH64-SHORT-SCOPE: 29:
; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SHORT-SCOPE-NEXT: [[TMP30:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP30]], i64 1, i1 false)
; AARCH64-SHORT-SCOPE-NEXT: ret i32 0 ; AARCH64-SHORT-SCOPE-NEXT: ret i32 0
; AARCH64-SHORT-SCOPE: 31: ; AARCH64-SHORT-SCOPE: 30:
; AARCH64-SHORT-SCOPE-NEXT: [[TMP32:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP32]], i64 1, i1 false)
; AARCH64-SHORT-SCOPE-NEXT: ret i32 0 ; AARCH64-SHORT-SCOPE-NEXT: ret i32 0
; ;
; AARCH64-SHORT-NOSCOPE-LABEL: @unreachable_exit( ; AARCH64-SHORT-NOSCOPE-LABEL: @unreachable_exit(
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0
; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1 ; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP20]], i32 15
; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[TMP25]], ptr [[TMP27]], align 1 ; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[ALLOCA_0_TAG]], ptr [[TMP27]], align 1
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP28:%.*]] = tail call i1 (...) @cond() ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP28:%.*]] = tail call i1 (...) @cond()
; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP31:%.*]] ; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP30:%.*]]
; AARCH64-SHORT-NOSCOPE: 29: ; AARCH64-SHORT-NOSCOPE: 29:
; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP30:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP30]], i64 1, i1 false)
; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0 ; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0
; AARCH64-SHORT-NOSCOPE: 31: ; AARCH64-SHORT-NOSCOPE: 30:
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP32:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP32]], i64 1, i1 false)
; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0 ; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0
; ;
%1 = alloca i8, align 1 %1 = alloca i8, align 1
call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1) call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1)
%2 = tail call i1 (...) @cond() #2 %2 = tail call i1 (...) @cond() #2
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: 3:
call void @use(ptr nonnull %1) #2 call void @use(ptr nonnull %1) #2
call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1) call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1)
ret i32 0 ret i32 0
4: 4:
ret i32 0 ret i32 0
} }
define dso_local i32 @diamond_lifetime() local_unnamed_addr sanitize_hwaddress { define dso_local i32 @diamond_lifetime() local_unnamed_addr sanitize_hwaddress {
; X86-SCOPE-LABEL: @diamond_lifetime( ; X86-SCOPE-LABEL: @diamond_lifetime(
; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; X86-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; X86-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; X86-SCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 ; X86-SCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
; X86-SCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57 ; X86-SCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57
; X86-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP3]], 63 ; X86-SCOPE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; X86-SCOPE-NEXT: [[TMP4:%.*]] = alloca { i8, [15 x i8] }, align 16 ; X86-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP4]], 63
; X86-SCOPE-NEXT: [[TMP5:%.*]] = call i8 @__hwasan_generate_tag() ; X86-SCOPE-NEXT: [[TMP5:%.*]] = alloca { i8, [15 x i8] }, align 16
; X86-SCOPE-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i64 ; X86-SCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; X86-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 ; X86-SCOPE-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; X86-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP7]], -9079256848778919937 ; X86-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP6]], -9079256848778919937
; X86-SCOPE-NEXT: [[TMP8:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; X86-SCOPE-NEXT: [[TMP7:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; X86-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP8]] to ptr ; X86-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP7]] to ptr
; X86-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP6]], 57 ; X86-SCOPE-NEXT: [[TMP8:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; X86-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP7]], [[TMP9]] ; X86-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 57
; X86-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP9]]
; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr ; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr
; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP4]]) ; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP5]])
; X86-SCOPE-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP6]] to i8 ; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[ALLOCA_0_TAG]], i64 16)
; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP11]], i64 16) ; X86-SCOPE-NEXT: [[TMP11:%.*]] = tail call i1 (...) @cond()
; X86-SCOPE-NEXT: [[TMP12:%.*]] = tail call i1 (...) @cond() ; X86-SCOPE-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP13:%.*]]
; X86-SCOPE-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP15:%.*]] ; X86-SCOPE: 12:
; X86-SCOPE: 13:
; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; X86-SCOPE-NEXT: [[TMP14:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[HWASAN_UAR_TAG]], i64 16)
; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP14]], i64 16) ; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP5]])
; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP4]]) ; X86-SCOPE-NEXT: br label [[TMP14:%.*]]
; X86-SCOPE-NEXT: br label [[TMP17:%.*]] ; X86-SCOPE: 13:
; X86-SCOPE: 15: ; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[HWASAN_UAR_TAG]], i64 16)
; X86-SCOPE-NEXT: [[TMP16:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP5]])
; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP16]], i64 16) ; X86-SCOPE-NEXT: br label [[TMP14]]
; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP4]]) ; X86-SCOPE: 14:
; X86-SCOPE-NEXT: br label [[TMP17]]
; X86-SCOPE: 17:
; X86-SCOPE-NEXT: ret i32 0 ; X86-SCOPE-NEXT: ret i32 0
; ;
; X86-NOSCOPE-LABEL: @diamond_lifetime( ; X86-NOSCOPE-LABEL: @diamond_lifetime(
; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; X86-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; X86-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 ; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57 ; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 57
; X86-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i64 [[TMP3]], 63 ; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = alloca { i8, [15 x i8] }, align 16 ; X86-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = and i8 [[TMP4]], 63
; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = call i8 @__hwasan_generate_tag() ; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = alloca { i8, [15 x i8] }, align 16
; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i64 ; X86-NOSCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP4]] to i64 ; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; X86-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP7]], -9079256848778919937 ; X86-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP6]], -9079256848778919937
; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; X86-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP8]] to ptr ; X86-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = inttoptr i64 [[TMP7]] to ptr
; X86-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP6]], 57 ; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; X86-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP7]], [[TMP9]] ; X86-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 57
; X86-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP9]]
; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr ; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP10]] to ptr
; X86-NOSCOPE-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP6]] to i8 ; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[ALLOCA_0_TAG]], i64 16)
; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP11]], i64 16) ; X86-NOSCOPE-NEXT: [[TMP11:%.*]] = tail call i1 (...) @cond()
; X86-NOSCOPE-NEXT: [[TMP12:%.*]] = tail call i1 (...) @cond() ; X86-NOSCOPE-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP13:%.*]]
; X86-NOSCOPE-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP14:%.*]] ; X86-NOSCOPE: 12:
; X86-NOSCOPE: 13:
; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; X86-NOSCOPE-NEXT: br label [[TMP15:%.*]] ; X86-NOSCOPE-NEXT: br label [[TMP14:%.*]]
; X86-NOSCOPE: 13:
; X86-NOSCOPE-NEXT: br label [[TMP14]]
; X86-NOSCOPE: 14: ; X86-NOSCOPE: 14:
; X86-NOSCOPE-NEXT: br label [[TMP15]] ; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP5]], i8 [[HWASAN_UAR_TAG]], i64 16)
; X86-NOSCOPE: 15:
; X86-NOSCOPE-NEXT: [[TMP16:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8
; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP4]], i8 [[TMP16]], i64 16)
; X86-NOSCOPE-NEXT: ret i32 0 ; X86-NOSCOPE-NEXT: ret i32 0
; ;
; AARCH64-SCOPE-LABEL: @diamond_lifetime( ; AARCH64-SCOPE-LABEL: @diamond_lifetime(
; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-SCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-SCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) ; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP25]], i64 1, i1 false) ; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[ALLOCA_0_TAG]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: [[TMP26:%.*]] = tail call i1 (...) @cond() ; AARCH64-SCOPE-NEXT: [[TMP26:%.*]] = tail call i1 (...) @cond()
; AARCH64-SCOPE-NEXT: br i1 [[TMP26]], label [[TMP27:%.*]], label [[TMP29:%.*]] ; AARCH64-SCOPE-NEXT: br i1 [[TMP26]], label [[TMP27:%.*]], label [[TMP28:%.*]]
; AARCH64-SCOPE: 27: ; AARCH64-SCOPE: 27:
; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SCOPE-NEXT: [[TMP28:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP28]], i64 1, i1 false) ; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]]) ; AARCH64-SCOPE-NEXT: br label [[TMP29:%.*]]
; AARCH64-SCOPE-NEXT: br label [[TMP31:%.*]] ; AARCH64-SCOPE: 28:
; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SCOPE-NEXT: br label [[TMP29]]
; AARCH64-SCOPE: 29: ; AARCH64-SCOPE: 29:
; AARCH64-SCOPE-NEXT: [[TMP30:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8
; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP30]], i64 1, i1 false)
; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]])
; AARCH64-SCOPE-NEXT: br label [[TMP31]]
; AARCH64-SCOPE: 31:
; AARCH64-SCOPE-NEXT: ret i32 0 ; AARCH64-SCOPE-NEXT: ret i32 0
; ;
; AARCH64-NOSCOPE-LABEL: @diamond_lifetime( ; AARCH64-NOSCOPE-LABEL: @diamond_lifetime(
; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-NOSCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-NOSCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP25]], i64 1, i1 false) ; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[ALLOCA_0_TAG]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: [[TMP26:%.*]] = tail call i1 (...) @cond() ; AARCH64-NOSCOPE-NEXT: [[TMP26:%.*]] = tail call i1 (...) @cond()
; AARCH64-NOSCOPE-NEXT: br i1 [[TMP26]], label [[TMP27:%.*]], label [[TMP28:%.*]] ; AARCH64-NOSCOPE-NEXT: br i1 [[TMP26]], label [[TMP27:%.*]], label [[TMP28:%.*]]
; AARCH64-NOSCOPE: 27: ; AARCH64-NOSCOPE: 27:
; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-NOSCOPE-NEXT: br label [[TMP29:%.*]] ; AARCH64-NOSCOPE-NEXT: br label [[TMP29:%.*]]
; AARCH64-NOSCOPE: 28: ; AARCH64-NOSCOPE: 28:
; AARCH64-NOSCOPE-NEXT: br label [[TMP29]] ; AARCH64-NOSCOPE-NEXT: br label [[TMP29]]
; AARCH64-NOSCOPE: 29: ; AARCH64-NOSCOPE: 29:
; AARCH64-NOSCOPE-NEXT: [[TMP30:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP30]], i64 1, i1 false)
; AARCH64-NOSCOPE-NEXT: ret i32 0 ; AARCH64-NOSCOPE-NEXT: ret i32 0
; ;
; AARCH64-SHORT-SCOPE-LABEL: @diamond_lifetime( ; AARCH64-SHORT-SCOPE-LABEL: @diamond_lifetime(
; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) ; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0
; AARCH64-SHORT-SCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1 ; AARCH64-SHORT-SCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1
; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP20]], i32 15
; AARCH64-SHORT-SCOPE-NEXT: store i8 [[TMP25]], ptr [[TMP27]], align 1 ; AARCH64-SHORT-SCOPE-NEXT: store i8 [[ALLOCA_0_TAG]], ptr [[TMP27]], align 1
; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = tail call i1 (...) @cond() ; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = tail call i1 (...) @cond()
; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP31:%.*]] ; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP30:%.*]]
; AARCH64-SHORT-SCOPE: 29: ; AARCH64-SHORT-SCOPE: 29:
; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SHORT-SCOPE-NEXT: [[TMP30:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP30]], i64 1, i1 false) ; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]]) ; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP31:%.*]]
; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP33:%.*]] ; AARCH64-SHORT-SCOPE: 30:
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP20]])
; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP31]]
; AARCH64-SHORT-SCOPE: 31: ; AARCH64-SHORT-SCOPE: 31:
; AARCH64-SHORT-SCOPE-NEXT: [[TMP32:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP32]], i64 1, i1 false)
; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]])
; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP33]]
; AARCH64-SHORT-SCOPE: 33:
; AARCH64-SHORT-SCOPE-NEXT: ret i32 0 ; AARCH64-SHORT-SCOPE-NEXT: ret i32 0
; ;
; AARCH64-SHORT-NOSCOPE-LABEL: @diamond_lifetime( ; AARCH64-SHORT-NOSCOPE-LABEL: @diamond_lifetime(
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]])
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP3]] to ptr
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 ; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP10]], ptr [[TMP11]], align 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP3]], 56
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 8
; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]]
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 ; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP16]], ptr [[TMP2]], align 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP3]], 4294967295
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr ; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1
; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 56 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP8]], 56
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() ; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_UAR_TAG:%.*]] = trunc i64 [[TMP19]] to i8
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = alloca { i8, [15 x i8] }, align 16
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_TAG:%.*]] = call i8 @__hwasan_generate_tag()
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64
; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935 ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_NOTAG:%.*]] = and i64 [[TMP21]], 72057594037927935
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = lshr i64 [[ALLOCA_0_NOTAG]], 4
; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP22]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_SHADOW:%.*]] = getelementptr i8, ptr [[TMP18]], i64 [[TMP22]]
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = shl i64 [[TMP20]], 56 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = zext i8 [[ALLOCA_0_TAG]] to i64
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = or i64 [[TMP21]], [[TMP23]] ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 56
; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP24]] to ptr ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[ALLOCA_0_NOTAG]], [[TMP24]]
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 ; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to ptr
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[ALLOCA_0_SHADOW]], i32 0
; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1 ; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, ptr [[TMP26]], align 1
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP20]], i32 15
; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[TMP25]], ptr [[TMP27]], align 1 ; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[ALLOCA_0_TAG]], ptr [[TMP27]], align 1
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP28:%.*]] = tail call i1 (...) @cond() ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP28:%.*]] = tail call i1 (...) @cond()
; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP30:%.*]] ; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP30:%.*]]
; AARCH64-SHORT-NOSCOPE: 29: ; AARCH64-SHORT-NOSCOPE: 29:
; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]])
; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP31:%.*]] ; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP31:%.*]]
; AARCH64-SHORT-NOSCOPE: 30: ; AARCH64-SHORT-NOSCOPE: 30:
; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP31]] ; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP31]]
; AARCH64-SHORT-NOSCOPE: 31: ; AARCH64-SHORT-NOSCOPE: 31:
; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP32:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i8 ; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[HWASAN_UAR_TAG]], i64 1, i1 false)
; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[ALLOCA_0_SHADOW]], i8 [[TMP32]], i64 1, i1 false)
; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0 ; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0
; ;
%1 = alloca i8, align 1 %1 = alloca i8, align 1
call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1) call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1)
%2 = tail call i1 (...) @cond() #2 %2 = tail call i1 (...) @cond() #2
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
3: 3:
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