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[RISCV] Add missing constraints for vwsll
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Authored by 4vtomat on Apr 24 2023, 11:33 PM.

Details

Summary

Add missing early clobber and widen constraints for vector crypto instruction: vwsll

Diff Detail

Event Timeline

4vtomat created this revision.Apr 24 2023, 11:33 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 24 2023, 11:33 PM
4vtomat requested review of this revision.Apr 24 2023, 11:33 PM
craig.topper added inline comments.Apr 24 2023, 11:40 PM
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
142

I don't think we usually indent after let when there aren't curly braces involved.

4vtomat updated this revision to Diff 516639.Apr 24 2023, 11:59 PM

Resolved Craig's comment.

Can you add assembler tests for this?

4vtomat updated this revision to Diff 516694.Apr 25 2023, 12:53 AM

Resolved Craig's comment:

  • Added invalid instruction test case for vwsll
This revision is now accepted and ready to land.Apr 25 2023, 8:45 PM
This revision was automatically updated to reflect the committed changes.