[RISCV] Pass data EEW instead of index EEW to V*Sched for indexed loads and stores

[nitinjohnraj]

Summary

The output operand for these classes depends on two of the arguments passed to the constructors:

1. The EEW
2. The data LMUL

If we pass the data EEW, we can derive the number of elements of the vector. We can derive no useful information from the index EEW and the data LMUL alone. Perhaps in the future we will need to pass the index EEW as well to derive some other information, but we have no need of it now.

[craig.topper]

Please write a description

The basic idea here is that EEW and EMUL used in a sched class name should refer to the same operand so they can be used to calculate the number of elements. If they refer to separate operands they're useless. It could be argued that the sched class name should contain 3 or all 4 of the pieces of information about the data and index eew and lmul, but we intend to leave that until we have a usage for it.

[michaelmaitland]

LGTM.

[craig.topper]

Blocking until a description is added.

[craig.topper]

LGTM

[michaelmaitland]

Just an observation here, no need to be addressed in this commit but I am curious as what is the variable case conventions for .td files. I see we use both pascal case and camel case here. The tablegen program reference does not say anything about what the convention is.

[nitinjohnraj]

Fixed parent revision

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

foreach dataEEW = EEWList in {
           defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar Vreg = dataEMUL.vrclass;
           defvar IdxVreg = idxEMUL.vrclass;
           defvar HasConstraint = !ne(dataEEW, idxEEW);
           defvar Order = !if(Ordered, "O", "U");
           let VLMul = dataEMUL.value in {
             def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
               VPseudoILoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint>,
-              VLXSched<idxEEW, Order, DataLInfo, IdxLInfo>;
+              VLXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
             def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_TU":
               VPseudoILoadNoMaskTU<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint>,
-              VLXSched<idxEEW, Order, DataLInfo, IdxLInfo>;
+              VLXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
             def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
               VPseudoILoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint>,
               RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
-              VLXSched<idxEEW, Order, DataLInfo, IdxLInfo>;
+              VLXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
           }
         }
       }
     }
   }
 }
 
 multiclass VPseudoUSStore {
foreach dataEEW = EEWList in {
           defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret;
           defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar Vreg = dataEMUL.vrclass;
           defvar IdxVreg = idxEMUL.vrclass;
           defvar Order = !if(Ordered, "O", "U");
           let VLMul = dataEMUL.value in {
             def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
               VPseudoIStoreNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,
-              VSXSched<idxEEW, Order, DataLInfo, IdxLInfo>;
+              VSXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
             def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
               VPseudoIStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,
-              VSXSched<idxEEW, Order, DataLInfo, IdxLInfo>;
+              VSXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
           }
         }
       }
     }
   }
 }
 
 multiclass VPseudoVPOP_M {
foreach dataEEW = EEWList in {
           defvar IdxVreg = idxEMUL.vrclass;
           defvar Order = !if(Ordered, "O", "U");
           let VLMul = dataEMUL.value in {
             foreach nf = NFSet<dataEMUL>.L in {
               defvar Vreg = SegRegClass<dataEMUL, nf>.RC;
               def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
                 VPseudoISegLoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
                                       nf, Ordered>,
-                VLXSEGSched<nf, idxEEW, Order, DataLInfo>;
+                VLXSEGSched<nf, dataEEW, Order, DataLInfo>;
               def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_TU" :
                 VPseudoISegLoadNoMaskTU<Vreg, IdxVreg, idxEEW, idxEMUL.value,
                                         nf, Ordered>,
-                VLXSEGSched<nf, idxEEW, Order, DataLInfo>;
+                VLXSEGSched<nf, dataEEW, Order, DataLInfo>;
               def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
                 VPseudoISegLoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
                                     nf, Ordered>,
-                VLXSEGSched<nf, idxEEW, Order, DataLInfo>;
+                VLXSEGSched<nf, dataEEW, Order, DataLInfo>;
             }
           }
         }
       }
     }
   }
 }