[RISCV] Remove is*Branch instruction flags from C_JR

[jobnoorman]

Summary

As discussed in 1d1b3c49531b, instruction flags set in the *.td files
are under-approximations. For C_JR, isBranch and isConditionalBranch are
set even though it is used for for returns which are not considered
branches.

This patch proposes to remove those flags from C_JR. More detailed
analysis can be implemented in RISCVMCInstrAnalysis.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoC.td

def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000>,
              Sched<[WriteLDD, ReadMemBase]> {
   let Inst{6-5} = imm{4-3};
   let Inst{4-2} = imm{8-6};
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),
                       "c.jr", "$rs1">, Sched<[WriteJmpReg]> {
-  let isBranch = 1;
   let isBarrier = 1;
   let isTerminator = 1;
-  let isIndirectBranch = 1;
   let rs2 = 0;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1,
     isAsCheapAsAMove = 1 in
 def C_MV : RVInst16CR<0b1000, 0b10, (outs GPRNoX0:$rs1), (ins GPRNoX0:$rs2),
                       "c.mv", "$rs1, $rs2">,
            Sched<[WriteIALU, ReadIALU]>;