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Differential D147724

[AArch64][SVE] Extend predicated fadd/fsub patterns to negative zero
ClosedPublic

Authored by dmgreen on Apr 6 2023, 9:53 AM.

Details

Reviewers
david-arm
sdesmalen
paulwalker-arm
c-rhodes
efriedma
Commits
rG9af92455f36f: [AArch64][SVE] Extend predicated fadd/fsub patterns to negative zero
Summary

This add -0.0 patterns for fadd and fsub, to go with D147723. The fsub pattern is only added for completeness.

Diff Detail

Event Timeline

dmgreen created this revision.Apr 6 2023, 9:53 AM
Herald added a reviewer: efriedma. · View Herald TranscriptApr 6 2023, 9:53 AM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: psnobl, hiraditya, kristof.beyls, tschuett. · View Herald Transcript
dmgreen requested review of this revision.Apr 6 2023, 9:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 6 2023, 9:53 AM
Harbormaster completed remote builds in B224049: Diff 511459.Apr 6 2023, 9:54 AM
paulwalker-arm accepted this revision.Apr 11 2023, 9:13 AM
This revision is now accepted and ready to land.Apr 11 2023, 9:13 AM
Matt added a subscriber: Matt.Apr 11 2023, 11:44 AM
dmgreen mentioned this in rGb0f89f09f2be: [AArch64] Extend testing for folding fadd to predicated SVE insinstructions. NFC.Apr 12 2023, 3:00 AM
This revision was landed with ongoing or failed builds.Apr 12 2023, 11:44 AM
Closed by commit rG9af92455f36f: [AArch64][SVE] Extend predicated fadd/fsub patterns to negative zero (authored by dmgreen). · Explain Why
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG9af92455f36f: [AArch64][SVE] Extend predicated fadd/fsub patterns to negative zero.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
6 lines
test/
CodeGen/
AArch64/
30 lines

Diff 511459

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

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def AArch64cls_mt : PatFrags<(ops node:$pg, node:$op, node:$pt), [(int_aarch64_sve_cls node:$pt, node:$pg, node:$op)]>; def AArch64cls_mt : PatFrags<(ops node:$pg, node:$op, node:$pt), [(int_aarch64_sve_cls node:$pt, node:$pg, node:$op)]>;
def AArch64cnot_mt : PatFrags<(ops node:$pg, node:$op, node:$pt), [(int_aarch64_sve_cnot node:$pt, node:$pg, node:$op)]>; def AArch64cnot_mt : PatFrags<(ops node:$pg, node:$op, node:$pt), [(int_aarch64_sve_cnot node:$pt, node:$pg, node:$op)]>;
def AArch64not_mt : PatFrags<(ops node:$pg, node:$op, node:$pt), [(int_aarch64_sve_not node:$pt, node:$pg, node:$op)]>; def AArch64not_mt : PatFrags<(ops node:$pg, node:$op, node:$pt), [(int_aarch64_sve_not node:$pt, node:$pg, node:$op)]>;
def AArch64fmul_m1 : EitherVSelectOrPassthruPatFrags<int_aarch64_sve_fmul, AArch64fmul_p>; def AArch64fmul_m1 : EitherVSelectOrPassthruPatFrags<int_aarch64_sve_fmul, AArch64fmul_p>;
def AArch64fadd_m1 : PatFrags<(ops node:$pg, node:$op1, node:$op2), [ def AArch64fadd_m1 : PatFrags<(ops node:$pg, node:$op1, node:$op2), [
(int_aarch64_sve_fadd node:$pg, node:$op1, node:$op2), (int_aarch64_sve_fadd node:$pg, node:$op1, node:$op2),
(vselect node:$pg, (AArch64fadd_p (SVEAllActive), node:$op1, node:$op2), node:$op1), (vselect node:$pg, (AArch64fadd_p (SVEAllActive), node:$op1, node:$op2), node:$op1),
(AArch64fadd_p_nsz (SVEAllActive), node:$op1, (vselect node:$pg, node:$op2, (SVEDup0))) (AArch64fadd_p_nsz (SVEAllActive), node:$op1, (vselect node:$pg, node:$op2, (SVEDup0))),
(AArch64fadd_p (SVEAllActive), node:$op1, (vselect node:$pg, node:$op2, (SVEDupNeg0)))
]>; ]>;
def AArch64fsub_m1 : PatFrags<(ops node:$pg, node:$op1, node:$op2), [ def AArch64fsub_m1 : PatFrags<(ops node:$pg, node:$op1, node:$op2), [
(int_aarch64_sve_fsub node:$pg, node:$op1, node:$op2), (int_aarch64_sve_fsub node:$pg, node:$op1, node:$op2),
(vselect node:$pg, (AArch64fsub_p (SVEAllActive), node:$op1, node:$op2), node:$op1), (vselect node:$pg, (AArch64fsub_p (SVEAllActive), node:$op1, node:$op2), node:$op1),
(AArch64fsub_p (SVEAllActive), node:$op1, (vselect node:$pg, node:$op2, (SVEDup0))) (AArch64fsub_p (SVEAllActive), node:$op1, (vselect node:$pg, node:$op2, (SVEDup0))),
(AArch64fsub_p_nsz (SVEAllActive), node:$op1, (vselect node:$pg, node:$op2, (SVEDupNeg0)))
]>; ]>;
def AArch64shadd : PatFrags<(ops node:$pg, node:$op1, node:$op2), def AArch64shadd : PatFrags<(ops node:$pg, node:$op1, node:$op2),
[(int_aarch64_sve_shadd node:$pg, node:$op1, node:$op2), [(int_aarch64_sve_shadd node:$pg, node:$op1, node:$op2),
(AArch64shadd_p node:$pg, node:$op1, node:$op2)]>; (AArch64shadd_p node:$pg, node:$op1, node:$op2)]>;
def AArch64uhadd : PatFrags<(ops node:$pg, node:$op1, node:$op2), def AArch64uhadd : PatFrags<(ops node:$pg, node:$op1, node:$op2),
[(int_aarch64_sve_uhadd node:$pg, node:$op1, node:$op2), [(int_aarch64_sve_uhadd node:$pg, node:$op1, node:$op2),
(AArch64uhadd_p node:$pg, node:$op1, node:$op2)]>; (AArch64uhadd_p node:$pg, node:$op1, node:$op2)]>;
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llvm/test/CodeGen/AArch64/sve-fp-combine.ll

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ret <vscale x 2 x double> %fsub ret <vscale x 2 x double> %fsub
} }
define <vscale x 8 x half> @fadd_h_sel_negzero(<vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x i1> %mask) { define <vscale x 8 x half> @fadd_h_sel_negzero(<vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: fadd_h_sel_negzero: ; CHECK-LABEL: fadd_h_sel_negzero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #32768 // =0x8000 ; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: mov z2.h, w8
; CHECK-NEXT: sel z1.h, p0, z1.h, z2.h
; CHECK-NEXT: fadd z0.h, z0.h, z1.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%nz = fneg <vscale x 8 x half> zeroinitializer %nz = fneg <vscale x 8 x half> zeroinitializer
%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x half> %b, <vscale x 8 x half> %nz %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x half> %b, <vscale x 8 x half> %nz
%fadd = fadd <vscale x 8 x half> %a, %sel %fadd = fadd <vscale x 8 x half> %a, %sel
ret <vscale x 8 x half> %fadd ret <vscale x 8 x half> %fadd
} }
define <vscale x 4 x float> @fadd_s_sel_negzero(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x i1> %mask) { define <vscale x 4 x float> @fadd_s_sel_negzero(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x i1> %mask) {
; CHECK-LABEL: fadd_s_sel_negzero: ; CHECK-LABEL: fadd_s_sel_negzero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000 ; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: mov z2.s, w8
; CHECK-NEXT: sel z1.s, p0, z1.s, z2.s
; CHECK-NEXT: fadd z0.s, z0.s, z1.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%nz = fneg <vscale x 4 x float> zeroinitializer %nz = fneg <vscale x 4 x float> zeroinitializer
%sel = select <vscale x 4 x i1> %mask, <vscale x 4 x float> %b, <vscale x 4 x float> %nz %sel = select <vscale x 4 x i1> %mask, <vscale x 4 x float> %b, <vscale x 4 x float> %nz
%fadd = fadd <vscale x 4 x float> %a, %sel %fadd = fadd <vscale x 4 x float> %a, %sel
ret <vscale x 4 x float> %fadd ret <vscale x 4 x float> %fadd
} }
define <vscale x 2 x double> @fadd_d_sel_negzero(<vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x i1> %mask) { define <vscale x 2 x double> @fadd_d_sel_negzero(<vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x i1> %mask) {
; CHECK-LABEL: fadd_d_sel_negzero: ; CHECK-LABEL: fadd_d_sel_negzero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000 ; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT: mov z2.d, x8
; CHECK-NEXT: sel z1.d, p0, z1.d, z2.d
; CHECK-NEXT: fadd z0.d, z0.d, z1.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%nz = fneg <vscale x 2 x double> zeroinitializer %nz = fneg <vscale x 2 x double> zeroinitializer
%sel = select <vscale x 2 x i1> %mask, <vscale x 2 x double> %b, <vscale x 2 x double> %nz %sel = select <vscale x 2 x i1> %mask, <vscale x 2 x double> %b, <vscale x 2 x double> %nz
%fadd = fadd <vscale x 2 x double> %a, %sel %fadd = fadd <vscale x 2 x double> %a, %sel
ret <vscale x 2 x double> %fadd ret <vscale x 2 x double> %fadd
} }
define <vscale x 8 x half> @fsub_h_sel_negzero(<vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x i1> %mask) { define <vscale x 8 x half> @fsub_h_sel_negzero(<vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: fsub_h_sel_negzero: ; CHECK-LABEL: fsub_h_sel_negzero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #32768 // =0x8000 ; CHECK-NEXT: fsub z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: mov z2.h, w8
; CHECK-NEXT: sel z1.h, p0, z1.h, z2.h
; CHECK-NEXT: fsub z0.h, z0.h, z1.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%nz = fneg <vscale x 8 x half> zeroinitializer %nz = fneg <vscale x 8 x half> zeroinitializer
%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x half> %b, <vscale x 8 x half> %nz %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x half> %b, <vscale x 8 x half> %nz
%fsub = fsub nsz <vscale x 8 x half> %a, %sel %fsub = fsub nsz <vscale x 8 x half> %a, %sel
ret <vscale x 8 x half> %fsub ret <vscale x 8 x half> %fsub
} }
define <vscale x 4 x float> @fsub_s_sel_negzero(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x i1> %mask) { define <vscale x 4 x float> @fsub_s_sel_negzero(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x i1> %mask) {
; CHECK-LABEL: fsub_s_sel_negzero: ; CHECK-LABEL: fsub_s_sel_negzero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000 ; CHECK-NEXT: fsub z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: mov z2.s, w8
; CHECK-NEXT: sel z1.s, p0, z1.s, z2.s
; CHECK-NEXT: fsub z0.s, z0.s, z1.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%nz = fneg <vscale x 4 x float> zeroinitializer %nz = fneg <vscale x 4 x float> zeroinitializer
%sel = select <vscale x 4 x i1> %mask, <vscale x 4 x float> %b, <vscale x 4 x float> %nz %sel = select <vscale x 4 x i1> %mask, <vscale x 4 x float> %b, <vscale x 4 x float> %nz
%fsub = fsub nsz <vscale x 4 x float> %a, %sel %fsub = fsub nsz <vscale x 4 x float> %a, %sel
ret <vscale x 4 x float> %fsub ret <vscale x 4 x float> %fsub
} }
define <vscale x 2 x double> @fsub_d_sel_negzero(<vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x i1> %mask) { define <vscale x 2 x double> @fsub_d_sel_negzero(<vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x i1> %mask) {
; CHECK-LABEL: fsub_d_sel_negzero: ; CHECK-LABEL: fsub_d_sel_negzero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000 ; CHECK-NEXT: fsub z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT: mov z2.d, x8
; CHECK-NEXT: sel z1.d, p0, z1.d, z2.d
; CHECK-NEXT: fsub z0.d, z0.d, z1.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%nz = fneg <vscale x 2 x double> zeroinitializer %nz = fneg <vscale x 2 x double> zeroinitializer
%sel = select <vscale x 2 x i1> %mask, <vscale x 2 x double> %b, <vscale x 2 x double> %nz %sel = select <vscale x 2 x i1> %mask, <vscale x 2 x double> %b, <vscale x 2 x double> %nz
%fsub = fsub nsz <vscale x 2 x double> %a, %sel %fsub = fsub nsz <vscale x 2 x double> %a, %sel
ret <vscale x 2 x double> %fsub ret <vscale x 2 x double> %fsub
} }
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